JPS58189649U - Stereo-monaural switching circuit - Google Patents
Stereo-monaural switching circuitInfo
- Publication number
- JPS58189649U JPS58189649U JP8678082U JP8678082U JPS58189649U JP S58189649 U JPS58189649 U JP S58189649U JP 8678082 U JP8678082 U JP 8678082U JP 8678082 U JP8678082 U JP 8678082U JP S58189649 U JPS58189649 U JP S58189649U
- Authority
- JP
- Japan
- Prior art keywords
- switching transistor
- stereo
- switching
- switching circuit
- monaural
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案に係るステレオ−モノラル切換え回路を示
す図である。
９２はＩＦ増幅・検波回路、３はマルチプレックス復調
回路、ＴＲ工、ＴＲ２は第１、第２スイツチングトラン
ジスタ、Ｄはダイオード（レベルシフト手段）、４は時
定数回路。The drawing is a diagram showing a stereo-monaural switching circuit according to the present invention. 92 is an IF amplification/detection circuit, 3 is a multiplex demodulation circuit, TR construction, TR2 are first and second switching transistors, D is a diode (level shift means), and 4 is a time constant circuit.
Claims (1)
御されるスイッチングトランジスタを設け、このスイッ
チングトランジスタの出力にてステレオ−モノラルの切
換えを行うステレオ−モノラル切換え回路であって、前
記スイッチングトランジスタを受信レベルを示す信号に
応答してオン・オフ制御される第１スイツチングトラン
ジスタト、この第１スイツチングトランジスタの出力に
て制御される第２スイツチングトランジスタにて構成し
前記第１スイツチングトランジスタの出力と前記第２ス
イツチングトランジスタの入力間に、レベルシフト手段
と時定数回路を挿入したことを特徴とするスオレオーモ
ノラル切換え回路。A stereo-monaural switching circuit includes a switching transistor that is controlled on and off in response to the received level of a radio broadcast signal, and performs stereo-monaural switching using the output of the switching transistor, the circuit receiving the switching transistor. The first switching transistor is controlled on and off in response to a signal indicating the level, and the second switching transistor is controlled by the output of the first switching transistor. A stereophonic switching circuit characterized in that a level shift means and a time constant circuit are inserted between the output and the input of the second switching transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8678082U JPS58189649U (en) | 1982-06-10 | 1982-06-10 | Stereo-monaural switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8678082U JPS58189649U (en) | 1982-06-10 | 1982-06-10 | Stereo-monaural switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58189649U true JPS58189649U (en) | 1983-12-16 |
| JPS6241476Y2 JPS6241476Y2 (en) | 1987-10-23 |
Family
ID=30095548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8678082U Granted JPS58189649U (en) | 1982-06-10 | 1982-06-10 | Stereo-monaural switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58189649U (en) |
-
1982
- 1982-06-10 JP JP8678082U patent/JPS58189649U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6241476Y2 (en) | 1987-10-23 |
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