JPS58189579A - Snooze circuit - Google Patents

Abstract

PURPOSE:To enable the selection of a desired snooze time by forming a set signal for the snooze time and producing an alarm sound at the snooze time. CONSTITUTION:The digital signal corresponding to a set snooze time is generated by a monostable multivibrator 3 and a circuit 5 for forming the set signal for the snooze time according to the operation times of a switch SW2 for setting the snooze time and the corresponding gates G3-G6 of a gate circuit 8 are controlled. The corresponding reference signals T1, T2- such as 2min, 4min- outputted by a shift register 6 of a reference signal generator which is subjected to shift control with the 2-minute pulses in response to a snooze switch SW1 are applied to the gates G3-G6 and an alarm sound is produced upon lapse of the snooze time corresponding to the setting after the generation of the alarm sound by the time coincidence signal. Thus, the desired snooze time is selectively set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a snooze circuit employed in, for example, an electronic watch.

[Technical background of the invention]

2. Description of the Related Art In recent years, electronic devices and the like that have an alarm function and are capable of notifying a predetermined time by means of a broadcast have become widespread. By the way, for example, in the case of an electronic watch, when a buzzer is used to notify the current time, even if the buzzer stops ringing once due to the operation to stop the buzzer, it will be notified after a while (e.g., 3 to 9 minutes). (after), a snooze circuit is used to trigger a repeating alarm that sounds the buzzer again.

[Problems with background technology]

However, in conventional snooze circuits, the time it takes for the above-mentioned buzzer to sound again (hereinafter referred to as the snooze time) is fixed and cannot be changed according to the user's wishes. It was inconvenient because of this.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a snooze circuit that can set a desired snooze time.

[Summary of the invention]

That is, the present invention provides a snooze time setting switch.

A switch is provided, and when the switch is operated, a desired snooze time setting signal is generated, and this signal is used to control the generation of an alarm output at the desired snooze time. It is possible to set the snooze time.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In the snooze circuit applied to the electronic watch shown in FIG. This is a monomulti circuit that generates t4 pulses SP1 to SP3 of a predetermined width controlled at the timing of . The monomulti circuit 1 generates the alarm coincidence signal generated when the alarm setting time and the current time match, based on the timing control by the system/4rus P1, and the monomulti circuit 2 It's called a snooze switch! The snooze switch signal generated by turning on the system pulse P
Pulse SP based on timing control by sK
x, and the monomulti circuit 3 generates a pulse 8Pl based on the timing control of the snooze time setting switch signal generated by pressing the snooze time setting key switch ffl using the system pulse SP3. 4 is an alarm drive dirt signal generation circuit that generates an alarm drive f-) signal (for example, buzzer drive signal BD8), which is from the mono multi-circuit 1, X8P.
IK is set and the arm S from mono multi circuit 2
PY t * consists of a flip-flop FF that is reset by the alarm-off switch signal when the alarm-off switch SWs is turned on, and an inverter 13 that inverts the output of the flip-flop FF and obtains the buzzer drive signal BD8. has been done. Therefore, this buzzer drive signal BD8 is either input to the snooze circuit or the alarm off switch s after the alarm match signal is output.
It will be output for the time until wl is input. 5
is Pinery Cow/Li BCl, BCl and Inverter IS
? A signal C1+C which is configured by Z4 and counts the .lsis SPm from the mono multi-circuit S by a pinary counter J1lc1*BCI and represents the number of times the snooze time setting switch so-called 3 is turned on.
A snooze time setting signal generation circuit that sends B as a snooze time setting signal, 6 is a 5-bit shift register SR
, ~8R8, reads the power level ``1'' by a shift pulse generated every unit time (for example, 2 minutes pulse generated every 2 minutes) after the alarm signal is generated, and performs a shift operation, and shifts each shift register. From SR, to 8R, five types of reference times (2 minutes, 4 minutes) are set in the above unit time steps.
reference time signal T1~ representing minutes, 6 minutes, 8 minutes, 10 minutes)
This is a reference time signal generation circuit that generates Ts. This generation circuit has the function of bringing the signals T1 to T to the power supply level +v every two minutes. Note that the shift registers SRI to SR of this generation circuit do not always operate, but only when the alarm off switch SW3 is input and when the snooze switch SW is activated.

It is reset 10 minutes after the alarm match signal is input, and does not operate until the next alarm coincidence signal is generated, and is reset when the snooze switch SW1 is input. This is to prohibit the buzzer from sounding when it has no meaning, and in order to execute this operation, a prohibition circuit 7 consisting of a shift register S, an inverter I, and an OR circuit ORtoORB was created by VT Corporation. ing. I is and'f) Gs~G
The buzzer drive circuit 9 is a dirt circuit composed of a f-) circuit 8 and an or-dart G- circuit.
The buzzer 10 connected to operates. Table, above ando) Gl~G? As shown in the figure, the buzzer drive signal B
DS.

Reference time signals T1 to T4, snooze time film constant signal CI+
In addition to inputs C and °σ-5ect, a modulation signal with a frequency of 4 kHz, for example, is input.

Next, the operation of the snooze circuit configured as described above will be explained with reference to the time charts of FIGS. 2 and 3.

The time chart in FIG. 2 shows the case where the snooze switch 8W1 is not input. Now, when an alarm coincidence signal is input to the monomulti circuit 1, a no-no pulse SP1 is generated at the system/f pulse PIO timing. In response to this alarm signal SPm, the alarm drive signal generating circuit 4 outputs a buzzer drive signal BDS.

In addition, the prohibited circuit 10 from the above Dulse 5PIK
When the shift register SR reads the power supply +V (“1” level) input, its output “1#” is the inverter I.

It is inverted and becomes @"0", which becomes one input of the OR circuit ORm. On the other hand, since the snooze switch 8W1 remains off, the mono multi circuit jO output is also at the "0" level, and therefore the OR path oi and o output are also at the "O level". When the signal generation circuit 6 becomes operational and p1 time elapses, the signal generation circuit 6 becomes operational and the Kq number T 1 r
T! .
Since the modulation signal is sent to the buzzer drive circuit 9 through γ and the OR gate G, the buzzer 9 sounds.

Then, when the alarm off switch gws is turned on,
! The data drive signal BDS is stopped, the shift register SR of the inhibition circuit 1 is reset and its output becomes 'm01', and the inverter sO output becomes 11', and the OR circuit 0R
When the IO output becomes 11m, the reference time signal generation circuit C becomes reset state 1aK. Therefore, no modulation signal is output from the gate circuit 8, and the p1 signal 10 no longer sounds.

31st! The time chart shows the case where the snooze switch ff= is input. In this case, in advance, turn on the snooze time setting switch SW an appropriate number of times to generate the pulse SPs from the monomulti circuit 3 an appropriate number of times, and set the Δinary counter BC1* BC of the snooze time setting circuit 5.
Counting is performed using l, and signal cl="0-zcl2"
The following explanation assumes that the snooze time is set to 2 minutes by setting "1", C, = "0", (, m"l". When the signal is input to the multi-circuit 1, the !day drive signal BDS opens the cyand 'y'>Gy as described above, and the modulation signal passes through this, so the buzzer IQ is driven. After this, the snooze switch 8W+ When turned on, the pulse SP is generated from the monomulti circuit 2, the flip-flop FF is reset, and the buzzer drive signal BD8 is no longer generated.At this time, the pulse SP that has passed through the OR circuit ORI
, the reference time signal generation circuit 6 is temporarily reset.

will be played. After this reset, the circuit - receives a 2-minute pulse generated 2 minutes after the generation of the alarm coincidence signal, and can sequentially generate the reference time signals T1+T1...Ts at 2-minute intervals. On the other hand, as mentioned above, since the snooze time setting switch SW sets the snooze time setting to 2 minutes in advance, the snooze opening time signal creation circuit 5 generates a signal corresponding to the snooze setting time of 2 minutes = 1.
01, C = "1", C, = "0', C = "1" are created and sent to the r-) circuit 8. Therefore, the r-) circuit 8 receives the reference time signal A modulation signal is sent out through the reference time signal T0 generated from the generation circuit 6 through the reference time signal T0, and the buzzer 10 is driven during the period of the reference time signal Tl.

After this, when the snooze switch IV1 is turned on again, the above-described operation is repeated.

However, the alarm off signal generated when the alarm off switch SWI is turned on instead of the snooze switch Swl, or the shift register SR is reset via the circuit OR when the snooze switch SWl is turned on as described in 9 above. , the output of this shift register 8R1f is inverted to ``1'' by the inverter I, and then passed through the OR circuit OR to the shift register 8R1~
Since SR, is reset, the time reference signal T1~
T1 will no longer occur.

According to the snooze circuit, the snooze time can be arbitrarily changed according to the user's wishes using the snooze time setting switch and switch SW1, which is very convenient. Tsu-*h, c
- As can be seen from circuit 1, the snooze time setting signal can be set to Tm (4 minutes) as the snooze time, and if c1=@i# and Cs='m1#, then T1
(6 minutes), c1=-11m, c, == @ 1#
and hrdT<Cs minutes) can be selected.

Note that in the above embodiment, the binary counter BOB*
The setting time was determined in 4 stages using BC2, but by adding a non-inari counter, it was set to 8 stages.
It can be increased to 16 levels. in this case,
Naturally, the number of reference time signal generation circuits 60 and shift registers SR will also be increased accordingly. Furthermore, it is possible to display the signal from the snooze time setting signal generation circuit 5 through a decoder or the like.

〔Effect of the invention〕

As explained above, according to the snooze circuit of the present invention, the snooze time can be easily set according to the user's wishes, so it is very convenient when applied to a watch.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a snooze circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation of the circuit shown in FIG. 1. 1-1... Mono multi circuit, 4... Alarm drive date signal generation circuit, 6... Snooze time setting signal generation circuit, 6... Reference time signal generation circuit, 7... Inhibition circuit, I ...f-) circuit, 9... buzzer drive circuit, 1
0-buzzer, s'w1...snooze switch, sw snow-snooze time membrane foot switch, SWS...alarm off switch.

Claims (3)

[Claims] (1) An alarm drive f-) signal generation circuit that generates an alarm drive 1M" -+- signal at the alarm setting time, an alarm off switch and a snooze switch that generate a signal to stop the operation of this circuit, and a snooze switch. A time setting switch, a snooze time setting signal generation circuit that outputs a snooze time setting signal under the control of the snooze time setting switch, and an operation that sequentially generates a plurality of reference time signals at predetermined time intervals through the operation of the snooze switch. a reference time signal generating circuit which is set to an operation start standby state after generation of the plurality of signals and by operation of the alarm off switch, and each reference time signal output from this circuit to create the snooze time setting signal. This f-) is controlled by the snooze time setting signal from the circuit.
1. A snooze circuit comprising: a dirt circuit that performs alarm drive control based on the output obtained by the control or the alarm drive dirt signal. (2) The snooze circuit according to claim 1, wherein the snooze time setting signal generation circuit uses a binary counter that counts the number of times the snooze switch is operated. (3) The reference time signal generating circuit is characterized in that the reference time signal generating circuit is a shift register or the like which operates according to a shift/roll pulse that occurs at fixed time intervals after the alarm setting time. Snooze circuit.