JPS5818944A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5818944A JPS5818944A JP11682881A JP11682881A JPS5818944A JP S5818944 A JPS5818944 A JP S5818944A JP 11682881 A JP11682881 A JP 11682881A JP 11682881 A JP11682881 A JP 11682881A JP S5818944 A JPS5818944 A JP S5818944A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- package
- metal material
- ceramic package
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はセラミック・パッケージの上面全体又は両長手
方向のセラミック面を金属で覆うことＫよシパソケージ
最端部の破損を防、止することを特徴とするＤＩＰ型（
デュアルインラインパッケージ：ＤｕａｌＩｎ−レｎｅ
ｐａｃｋａｇｅ ）半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a DIP type (DIP type) characterized by covering the entire top surface or both longitudinal ceramic surfaces of a ceramic package with metal to prevent damage to the outermost end of the package.
Dual in-line package: DualIn-line
package) relates to semiconductor devices.
元来セラミックは硬度は高いが衝撃に対してはもろいも
のである。このため、従来の半導体集積回路等のセラミ
ックパッケージでＤＩＰ型のものでは特性チェックの測
定の際、信頼性確認のだめの衝撃試験及びケースに収納
して運搬する際に衝撃が加えられると、パッケージ最端
部や、パッケージ端部のリードが破損し、外観不良、気
密性不良及び電気的特性不良となることが度々あるとい
う難点があった。本発明の目的は、セラミック・パッケ
ージの上面全体又は両長手力向のセラミック面を硬度は
セラミックに比較して低くても耐衝撃性に優れた金属材
で覆うことによって取扱い中に加えられる衝撃から半導
体装置の要部、特にセラミックパッケージの最端部やセ
ラミック中の導電配線及びリード線を有効に保護するよ
りにしたことを特徴とするものである。以下に本発明の
実施例をセラミックパッケージを用いたＤＩＰ型半導体
装置について説明する。第１図において、１は金属製キ
ャップ、２はキャップと同材質のリング、３はセラミッ
クパッケージ、４はリードである。すなわち、セラミッ
クパッケージ３の上面にリング２を燻材で取付け、その
上にキャップ１を載せて電気溶接によシ一体に固定した
ものである。このように、半導体装置のセラミックパッ
ケージの上面を金属製キャップ１で覆ったため、取扱い
中に衝撃を受けた場合でも、パッケージの最端部及びリ
ードを保護してその破損を防止するととができる。Ceramic is inherently hard, but it is brittle against impact. For this reason, with conventional DIP type ceramic packages for semiconductor integrated circuits, etc., if shock is applied during characteristic check measurements, during shock tests to confirm reliability, and when transported in a case, the package may There is a problem in that the ends and the leads at the ends of the package are often damaged, resulting in poor appearance, poor airtightness, and poor electrical characteristics. The object of the present invention is to protect the entire upper surface of a ceramic package or the ceramic surfaces in both longitudinal directions with a metal material that has lower hardness than ceramic but has excellent impact resistance, thereby protecting the ceramic package from shocks applied during handling. The present invention is characterized in that it effectively protects the main parts of the semiconductor device, especially the extreme end of the ceramic package, and the conductive wiring and lead wires inside the ceramic. Embodiments of the present invention will be described below regarding a DIP type semiconductor device using a ceramic package. In FIG. 1, 1 is a metal cap, 2 is a ring made of the same material as the cap, 3 is a ceramic package, and 4 is a lead. That is, the ring 2 is attached to the top surface of the ceramic package 3 using smoked wood, the cap 1 is placed on top of the ring 2, and the cap 1 is fixed integrally by electric welding. As described above, since the top surface of the ceramic package of the semiconductor device is covered with the metal cap 1, even if the package receives a shock during handling, the extreme end of the package and the leads can be protected and their damage can be prevented.
第２図は、セラミックパッケージ３の上面を金属製キャ
ップ１で覆うとともにセラミックパッケージ３の両長手
方向のセラミック面の一部を金属材５で覆ったものであ
る。これによってセラミックパッケージ乙の長手方向に
加わる機械的衝撃を金属材５で緩和し、パッケージの破
損を防止することができる。なお、金属材はセラミック
パッケージの上面全体又は両長手方向のセラミック面の
いずれか一方を穆ってもよい。In FIG. 2, the top surface of the ceramic package 3 is covered with a metal cap 1, and a portion of the ceramic surface in both longitudinal directions of the ceramic package 3 is covered with a metal material 5. As a result, the mechanical impact applied in the longitudinal direction of the ceramic package B can be alleviated by the metal material 5, and damage to the package can be prevented. Note that the metal material may cover the entire top surface of the ceramic package or either one of the ceramic surfaces in both longitudinal directions.
本発明は以上のようにセラミックパッケージの上面又は
両長手方向のセラミック面の少くとも一方を金属材で覆
ったので、取扱い中における衝撃力から半導体装置の要
部を保護でき、セラミックパッケージの最端部やパッケ
ージ端部の破損を防止して歩留りを向上し、半導体隼積
回路の信頼性を高めることができる効果を有するもので
ある。As described above, the present invention covers the top surface of the ceramic package or at least one of the ceramic surfaces in both longitudinal directions with a metal material, so that the main parts of the semiconductor device can be protected from impact force during handling. This has the effect of preventing damage to the parts and package ends, improving yield, and increasing the reliability of semiconductor integrated circuits.
【図面の簡単な説明】
第１図は本発明の一実施例を示すり、 １．Ｐ、型半導
体集積回路の分解斜視図、第２図は他の実施例を１・・
金属製キャップ ３・・セラミックパッケージ４・・・
リード ５・・・金属材特許出願人 日本電
気株式会社
代 理 人 弁理ト 菅 野 中BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an embodiment of the present invention. FIG. 2 is an exploded perspective view of a P type semiconductor integrated circuit.
Metal cap 3...Ceramic package 4...
Lead 5...Metal material patent applicant NEC Corporation Representative Patent attorney Naka Kanno
Claims (1)
手方向のセラミック面を金属材で覆うことを特徴とする
半導体装置。(1) A semiconductor device characterized in that the entire upper surface or both longitudinal ceramic surfaces of a ceramic pancage are covered with a metal material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11682881A JPS5818944A (en) | 1981-07-25 | 1981-07-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11682881A JPS5818944A (en) | 1981-07-25 | 1981-07-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5818944A true JPS5818944A (en) | 1983-02-03 |
Family
ID=14696625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11682881A Pending JPS5818944A (en) | 1981-07-25 | 1981-07-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818944A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0351602A2 (en) * | 1988-07-18 | 1990-01-24 | Motorola, Inc. | Ceramic semiconductor package having crack arrestor patterns |
| FR2638935A1 (en) * | 1988-11-04 | 1990-05-11 | Thomson Csf | PROTECTIVE METHOD FOR MAINTAINING STANDARD ELECTRONIC COMPONENTS WITH HIGH PRESSURES AND ELECTRONIC MODULE HAVING PROTECTED COMPONENTS |
| US5703397A (en) * | 1991-11-28 | 1997-12-30 | Tokyo Shibaura Electric Co | Semiconductor package having an aluminum nitride substrate |
-
1981
- 1981-07-25 JP JP11682881A patent/JPS5818944A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0351602A2 (en) * | 1988-07-18 | 1990-01-24 | Motorola, Inc. | Ceramic semiconductor package having crack arrestor patterns |
| FR2638935A1 (en) * | 1988-11-04 | 1990-05-11 | Thomson Csf | PROTECTIVE METHOD FOR MAINTAINING STANDARD ELECTRONIC COMPONENTS WITH HIGH PRESSURES AND ELECTRONIC MODULE HAVING PROTECTED COMPONENTS |
| US5703397A (en) * | 1991-11-28 | 1997-12-30 | Tokyo Shibaura Electric Co | Semiconductor package having an aluminum nitride substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8284016B2 (en) | Array type chip resistor | |
| US4467345A (en) | Semiconductor integrated circuit device | |
| EP0590986A1 (en) | Lead-on-chip inner lead bonding lead frame, bonding method and apparatus | |
| US7352062B2 (en) | Integrated circuit package design | |
| JP6665996B2 (en) | Chip resistor | |
| JPS5818944A (en) | Semiconductor device | |
| US4818821A (en) | Brazed leaded package | |
| US5334553A (en) | Telecommunication equipment protector | |
| KR102356802B1 (en) | Paste for forming resist layer of chip resistor and chip resistor | |
| US20030205821A1 (en) | Chip package capable of reducing moisture penetration | |
| KR20230144969A (en) | Discrete power semiconductor package | |
| EP0102988A4 (en) | Integrated circuit lead frame. | |
| JPH01164054A (en) | Integrated circuit | |
| JPH10284500A (en) | Electrode structure of surface mounted device | |
| US20080024264A1 (en) | Metal oxide varistor | |
| KR100246730B1 (en) | Chip barristor and its setting apparatus | |
| JP3372169B2 (en) | Semiconductor package | |
| JPH05259345A (en) | Protective device for integrated circuit combined with auxiliary support | |
| KR0158618B1 (en) | Pattern of semiconductor chip | |
| JP2793553B2 (en) | Package for semiconductor device | |
| JPS60109256A (en) | Plastic semiconductor device | |
| JPH11312772A (en) | Lead frame, semiconductor device and electronic equipment | |
| JPS617638A (en) | Semiconductor device | |
| JPH0680749B2 (en) | Semiconductor integrated circuit device | |
| JPS6223674B2 (en) |