JPH10284500A - Electrode structure of surface mounted device - Google Patents

Electrode structure of surface mounted device

Info

Publication number
JPH10284500A
JPH10284500A JP9093764A JP9376497A JPH10284500A JP H10284500 A JPH10284500 A JP H10284500A JP 9093764 A JP9093764 A JP 9093764A JP 9376497 A JP9376497 A JP 9376497A JP H10284500 A JPH10284500 A JP H10284500A
Authority
JP
Japan
Prior art keywords
electrode
solder bump
gravity
center
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9093764A
Other languages
Japanese (ja)
Other versions
JP3758289B2 (en
Inventor
Akihiro Niimi
新美　　彰浩
Shoji Ozoe
祥司 尾添
Seiji Fujino
誠二 藤野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
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Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP09376497A priority Critical patent/JP3758289B2/en
Publication of JPH10284500A publication Critical patent/JPH10284500A/en
Application granted granted Critical
Publication of JP3758289B2 publication Critical patent/JP3758289B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
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Abstract

PROBLEM TO BE SOLVED: To realize an improvement in connection reliability in a mounted condition through a simple structure. SOLUTION: A plurality of electrode pads 4 are provided on the mounting surface of a flip chip 1 so as to have a rectangular configuration. These electrode pads 4, respectively, have solder bump electrodes 2 (barrier metals 6 alone are shown) thereon. Each of the electrode pads 4 has an approximately elliptic shape, which has a larger area than that of the barrier metal 6 of the solder bump electrode 2. Each of extending portions 4a is set in a form being extended by a predetermined length in the direction of a barycentric position G with respect to the distribution of the group of the solder bump electrodes 2. An extension measure P of the individual extending portions 4a in the direction of the barycentric position G is set at a value in proportion to 1.1<th> power of the distance between the barycentric position G and the bump electrode 2 corresponding to the extending portion 4a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、フリップチップな
どのように複数のはんだバンプ電極を備えた表面実装素
子の電極構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a surface mount device having a plurality of solder bump electrodes such as a flip chip.

【０００２】[0002]

【従来の技術】例えば半導体ベアチップ実装技術の一つ
であるフリップチップにおいては、半導体チップの実装
面に配置された電極パッド上にはんだバンプ電極を形成
し、そのはんだバンプ電極を配線基板側の電極パッドに
対し押し付けた状態で接続するようにしている。2. Description of the Related Art For example, in a flip chip as one of semiconductor bare chip mounting techniques, a solder bump electrode is formed on an electrode pad arranged on a mounting surface of a semiconductor chip, and the solder bump electrode is connected to an electrode on a wiring board side. The connection is made while pressing the pad.

【０００３】[0003]

【発明が解決しようとする課題】上記のようなフリップ
チップにおいては、半導体チップ及び配線基板間を接合
するはんだ部分に作用する熱応力（半導体チップと配線
基板との線膨張係数の差に伴う熱応力）により発生する
歪みを、当該はんだ部分の変形により緩和する構造とな
っている。しかしながら、はんだ部分の温度が低下した
状態では、はんだが硬化して変形し辛くなるため、上記
のような歪み緩和効果を十分に期待できなくなり、場合
によっては、電極パッドが半導体チップ上で滑ることに
起因した電極の位置ずれや断線を来たすなど、実装状態
での接続信頼性が低下するという問題点があった。In the above-mentioned flip chip, thermal stress acting on a solder portion for joining the semiconductor chip and the wiring board (heat due to a difference in linear expansion coefficient between the semiconductor chip and the wiring board). This is a structure in which distortion caused by stress is reduced by deformation of the solder portion. However, in the state where the temperature of the solder portion is lowered, the solder hardens and becomes hard to deform, so that the above-described strain relief effect cannot be sufficiently expected, and in some cases, the electrode pad slips on the semiconductor chip. For example, there is a problem that connection reliability in a mounted state is deteriorated, such as displacement of an electrode or disconnection caused by the above.

【０００４】このような問題点に対処するために、従来
では、半導体チップに極力近い線膨張係数を備えた配線
基板材料を選定することが行われているが、実際には、
両者の線膨張係数を完全に一致させることが不可能であ
るため、前述したような問題点を確実に解決することは
困難であった。In order to deal with such a problem, conventionally, a wiring board material having a linear expansion coefficient as close as possible to that of a semiconductor chip has been selected.
Since it is impossible to completely match the linear expansion coefficients of the two, it has been difficult to reliably solve the above-mentioned problems.

【０００５】また、上記問題点を解決するために、特開
平６−１７７１３４号公報に見られる技術が考えられて
いる。即ち、この公報には、ＩＣウエハ（半導体チッ
プ）上の電極パッドとこれを被覆するバリアメタル層と
の間の外周部分に、ポリイミド樹脂またはエポキシ系樹
脂より成る樹脂層を介在させ、はんだ部分に作用する熱
応力に起因した歪みを、上記樹脂層の変形により吸収す
る構成となっている。In order to solve the above problem, a technique disclosed in Japanese Patent Application Laid-Open No. Hei 6-177134 has been considered. That is, in this publication, a resin layer made of a polyimide resin or an epoxy resin is interposed in an outer peripheral portion between an electrode pad on an IC wafer (semiconductor chip) and a barrier metal layer covering the same, and a solder portion is The strain caused by the acting thermal stress is absorbed by the deformation of the resin layer.

【０００６】しかしながら、この構成では、全体の構成
が複雑化して製造コストが高くなるという欠点があり、
しかも、樹脂層の弾性率と一般的にはアルミニウムが利
用される電極パッドの弾性率との差が大きいという事情
があるため、バリアメタル層と電極パッドの接合部にお
いて逆に応力集中を来たして電極パッドにダメージが加
えられる可能性が高くなるものであり、前述した問題点
を確実に解決できるとはいえないものであった。However, this configuration has a disadvantage that the overall configuration is complicated and the manufacturing cost is high.
In addition, since there is a large difference between the elastic modulus of the resin layer and the elastic modulus of the electrode pad generally made of aluminum, stress is concentrated at the junction between the barrier metal layer and the electrode pad. The possibility that the electrode pad is damaged is increased, and it cannot be said that the above-mentioned problem can be surely solved.

【０００７】本発明は上記のような事情に鑑みてなされ
たものであり、その目的は、電極パッドの形状に変更を
加えるだけの簡単な構成によって、実装状態での接続信
頼性の向上を実現できるようになる表面実装素子の電極
構造を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to improve the connection reliability in a mounted state by a simple configuration in which the shape of an electrode pad is simply changed. It is an object of the present invention to provide an electrode structure of a surface mount device which can be used.

【０００８】[0008]

【課題を解決するための手段】上記のような目的を達成
するために、請求項１記載の発明のように、はんだバン
プ電極が形成された複数の電極パッドのうちの少なくと
も１個以上に、上記はんだバンプ電極群の分布に関して
の重心位置方向若しくはこれと反対の方向へ延長された
形状の張り出し部を形成する構成を採用できる。In order to achieve the above object, at least one of a plurality of electrode pads on which solder bump electrodes are formed is provided as described above. It is possible to adopt a configuration in which a projecting portion having a shape extended in the direction of the center of gravity with respect to the distribution of the solder bump electrode group or in the direction opposite thereto is employed.

【０００９】一般的に、素子本体の実装面に配置された
複数の電極パッド上にはんだバンプ電極を形成して成る
表面実装素子を配線基板に実装した場合には、線膨張係
数差に起因した熱応力による歪みがはんだ部分の変形に
よって緩和されるものであるが、そのはんだ部分の温度
が大きく低下してはんだが硬化した状態では、上記した
熱応力緩和機能が不十分になる。この場合、一般的な表
面実装素子にあっては、素子本体の線膨張係数より配線
基板の線膨脹係数が大きいという事情があるため、上記
のようにはんだ部分の温度が低下した状態では、電極パ
ッドに対して、はんだバンプ電極群の分布に関しての重
心位置方向へ移動させようとする力が作用するものであ
り、当該電極パッドと素子本体との間には、上記のよう
な移動を押し止めようとする拘束力が働く。In general, when a surface mount device having solder bump electrodes formed on a plurality of electrode pads arranged on a mounting surface of a device body is mounted on a wiring board, a difference in linear expansion coefficient is caused. Although the distortion due to the thermal stress is alleviated by the deformation of the solder portion, when the temperature of the solder portion is greatly reduced and the solder is hardened, the above-described thermal stress relaxing function becomes insufficient. In this case, in a general surface mount device, the linear expansion coefficient of the wiring board is larger than the linear expansion coefficient of the device body. The force acting to move the solder bump electrode group in the direction of the center of gravity with respect to the distribution of the solder bump electrode group acts on the pad, and the above-described movement is suppressed between the electrode pad and the element body. The binding force that tries to work.

【００１０】上記拘束力は、電極パッドと素子本体との
間の接合面積の大きさに依存するものであるが、複数の
電極パッドのうちの少なくとも１個以上に、はんだバン
プ電極群の分布に関しての重心位置方向へ延長された形
状の張り出し部を形成する構成としておけば、当該張り
出し部が形成された電極パッドについては、これと素子
本体との間に働く拘束力が、上記重心位置方向について
大きくなる。[0010] The binding force depends on the size of the bonding area between the electrode pad and the element body. At least one of the plurality of electrode pads has a distribution with respect to the distribution of the solder bump electrode group. If the configuration is such that a projecting portion extending in the direction of the center of gravity of the electrode pad is formed, for the electrode pad on which the projecting portion is formed, the restraining force acting between the electrode pad and the element body is limited in the direction of the center of gravity. growing.

【００１１】このように、張り出し部が形成された電極
パッドにあっては大きな拘束力が得られるため、その電
極パッドが素子本体上で滑ることに起因した位置ずれや
断線を来たす虞がなくなり、実装状態での接続信頼性が
向上するようになる。しかも、このような効果を得るた
めに、電極パッドの形状に変更を加えるだけで済むか
ら、製造コストが高騰する虞がなくなる。As described above, since a large restraining force is obtained in the electrode pad on which the overhanging portion is formed, there is no possibility that the electrode pad may be displaced or disconnected due to sliding on the element body. The connection reliability in the mounted state is improved. Moreover, in order to obtain such an effect, it is only necessary to change the shape of the electrode pad, so that there is no possibility that the manufacturing cost will increase.

【００１２】尚、素子本体の線膨張係数が配線基板の線
膨脹係数より大きい場合には、複数の電極パッドのうち
の少なくとも１個以上に、はんだバンプ電極群の分布に
関しての重心位置方向と反対の方向へ延長された形状の
張り出し部を形成する構成とすれば良いものである。When the coefficient of linear expansion of the element body is larger than the coefficient of linear expansion of the wiring board, at least one of the plurality of electrode pads is opposite to the direction of the center of gravity with respect to the distribution of the solder bump electrode group. It is only necessary to adopt a configuration in which a projecting portion having a shape extended in the direction of is formed.

【００１３】また、一般的に、実装状態においてはんだ
部分に作用する熱応力は、はんだバンプ電極群の分布に
関しての重心位置と各はんだバンプ電極との間の距離が
長い場合ほど大きくなるという事情があるから、請求項
２記載の発明のように、前記張り出し部を、少なくとも
上記重心位置との間の距離が最も長い状態にあるはんだ
バンプ電極と対応した電極パッドに形成することが望ま
しくなる。In general, the thermal stress acting on the solder portion in the mounted state increases as the distance between the position of the center of gravity in the distribution of the solder bump electrode group and each solder bump electrode increases. Therefore, as in the second aspect of the present invention, it is desirable that the overhanging portion is formed on an electrode pad corresponding to the solder bump electrode in which at least the distance from the position of the center of gravity is longest.

【００１４】これと同じ事情を考慮すると、前記張り出
し部を複数の電極パッドに形成した場合には、請求項３
記載の発明のように、各張り出し部の張り出し寸法を、
前記重心位置との間の距離が長い状態にあるはんだバン
プ電極に対応したものほど長くなるように設定すること
が望ましい。In view of the same situation, when the overhanging portion is formed on a plurality of electrode pads, a third aspect is provided.
Like the described invention, the overhang dimension of each overhang is
It is desirable that the distance from the position of the center of gravity is set to be longer as the distance corresponding to the solder bump electrode in the state of being longer.

【００１５】[0015]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

（第１の実施形態）図２には、表面実装素子としてのフ
リップチップ１に設けられるはんだバンプ電極２部分の
縦断面構造が示されている。この図２において、Ｓｉチ
ップ３（本発明でいう素子本体に相当）の実装面には、
内部配線層の一部をなす電極パッド４、並びに内部配線
層を電極パッド４の開口部を残して覆う絶縁保護膜５が
形成されている。尚、電極パッド４を含む内部配線層
は、例えばＡｌ−Ｓｉ１％により厚さ１．３３μｍ程度
に形成され、絶縁保護膜５は、例えばＰ−ＳｉＮにより
厚さ１．６μｍ程度に形成される。(First Embodiment) FIG. 2 shows a vertical sectional structure of a solder bump electrode 2 provided on a flip chip 1 as a surface mount element. In FIG. 2, the mounting surface of the Si chip 3 (corresponding to the element body in the present invention) has
An electrode pad 4 which forms a part of the internal wiring layer, and an insulating protective film 5 which covers the internal wiring layer except for the opening of the electrode pad 4 are formed. The internal wiring layer including the electrode pad 4 is formed with, for example, Al-Si 1% to a thickness of about 1.33 μm, and the insulating protection film 5 is formed with, for example, P-SiN to have a thickness of about 1.6 μm.

【００１６】上記絶縁保護膜５上には、これに形成され
た前記開口部を中心とした形状のＴｉ製バリアメタル６
が、蒸着或いはスパッタにより０．３μｍ程度の厚さに
形成されている。このバリアメタル６上には、厚さ３０
μｍ程度のきのこ状の下地金属７が例えばＣｕメッキに
より形成され、当該下地金属７上に、略半球形状のはん
だバンプ８が形成され、以てはんだバンプ電極２が構成
されている。On the insulating protection film 5, a Ti barrier metal 6 having a shape centered on the opening formed therein is formed.
Is formed to a thickness of about 0.3 μm by vapor deposition or sputtering. On the barrier metal 6, a thickness of 30
A mushroom-shaped base metal 7 of about μm is formed by, for example, Cu plating, and a substantially hemispherical solder bump 8 is formed on the base metal 7, thereby forming the solder bump electrode 2.

【００１７】上記のように構成されたはんだバンプ電極
２は、フリップチップ１の実装面に複数個配置されるも
のである。具体的には、フリップチップ１の実装面を概
略的に示す図１のように、矩形状をなすフリップチップ
１の周縁部分には、複数個の電極パッド４が矩形状配置
となるように設けられるものであり、これら電極パッド
４上に、はんだバンプ電極２（説明の便宜上、バリアメ
タル６のみを示す）が形成される。尚、電極パッド４
は、フリップチップ１の回路形成領域１ａに対して前記
内部配線層（図示せず）を介して接続されている。A plurality of solder bump electrodes 2 configured as described above are arranged on the mounting surface of the flip chip 1. Specifically, as shown in FIG. 1 schematically showing the mounting surface of the flip chip 1, a plurality of electrode pads 4 are provided in a rectangular portion on the periphery of the flip chip 1 having a rectangular shape. The solder bump electrodes 2 (only the barrier metal 6 is shown for convenience of explanation) are formed on the electrode pads 4. The electrode pad 4
Are connected to the circuit formation region 1a of the flip chip 1 via the internal wiring layer (not shown).

【００１８】この場合、各電極パッド４は、はんだバン
プ電極２のバリアメタル６より大きな面積を有した形
状、具体的にはバリアメタル６の周縁部からはみ出した
張り出し部４ａを備えた楕円近似形状に形成されてお
り、特に、各張り出し部４ａは、はんだバンプ電極２群
の分布に関しての重心位置Ｇ方向へ所定の寸法だけ延長
された形状に設定されている。In this case, each electrode pad 4 has a shape having an area larger than the barrier metal 6 of the solder bump electrode 2, specifically, an elliptical approximation having an overhang 4 a protruding from the peripheral edge of the barrier metal 6. In particular, each overhang portion 4a is set to have a shape extended by a predetermined dimension in the direction of the center of gravity G with respect to the distribution of the solder bump electrodes 2 group.

【００１９】上記張り出し部４ａにおける重心位置Ｇ方
向への延長部分の張り出し寸法Ｐ（図１、図２参照）
は、重心位置Ｇとの間の距離ΔＳが長い状態にあるはん
だバンプ電極２に対応したものほど長くなるように設定
される。具体的には、各張り出し部４ａの張り出し寸法
Ｐは、重心位置Ｇと当該張り出し部４ａに対応するはん
だバンプ電極２との間の距離ΔＳの１．１乗に比例した
値に設定される。つまり、上記張り出し寸法Ｐは、重心
位置Ｇ及びはんだバンプ電極２間の距離ΔＳと、当該張
り出し寸法Ｐとの関係を示す図３中の斜線帯の範囲に収
まるように設定される。The extension P of the extension of the extension 4a in the direction of the center of gravity G (see FIGS. 1 and 2).
Is set so that the distance corresponding to the solder bump electrode 2 whose distance ΔS from the center of gravity G is longer is longer. Specifically, the overhang dimension P of each overhang 4a is set to a value proportional to the 1.1 power of the distance ΔS between the center of gravity position G and the solder bump electrode 2 corresponding to the overhang 4a. That is, the overhang dimension P is set so as to fall within the range of the hatched area in FIG. 3 showing the relationship between the center of gravity position G and the distance ΔS between the solder bump electrodes 2 and the overhang dimension P.

【００２０】上記した本実施例の構成によれば、以下に
述べるような作用・効果が得られることになる。即ち、
フリップチップ１を配線基板に実装した状態では、それ
らの線膨張係数差に起因した熱応力による歪みが、はん
だバンプ電極２のはんだ部分の変形によって緩和される
ものであるが、そのはんだ部分の温度が大きく低下して
はんだが硬化した状態では、上記した熱応力緩和機能が
不十分になる。この場合、配線基板が例えばアルミナ基
板であった場合には、その線膨張係数が７ｐｐｍ程度で
あるのに対して、フリップチップ１を構成するＳｉチッ
プ３の線膨張係数は３．５ｐｐｍ程度であるため、上記
のようにはんだ部分の温度が低下した状態では、電極パ
ッド４に対して、はんだバンプ電極２群の分布に関して
の重心位置Ｇ方向へ移動させようとする力が作用するも
のであり、当該電極パッド４とＳｉチップ３との間に
は、上記のような移動を押し止めようとする拘束力が働
く。According to the configuration of the present embodiment described above, the following operations and effects can be obtained. That is,
In the state where the flip chip 1 is mounted on the wiring board, the distortion due to the thermal stress caused by the difference between the linear expansion coefficients is reduced by the deformation of the solder portion of the solder bump electrode 2. When the solder is hardened due to a large decrease in the thermal stress, the above-mentioned thermal stress relaxation function becomes insufficient. In this case, when the wiring substrate is, for example, an alumina substrate, its linear expansion coefficient is about 7 ppm, whereas the linear expansion coefficient of the Si chip 3 constituting the flip chip 1 is about 3.5 ppm. Therefore, in the state where the temperature of the solder portion is lowered as described above, a force to move the electrode pad 4 in the direction of the center of gravity G with respect to the distribution of the solder bump electrode 2 group acts on the electrode pad 4. A restraining force acts between the electrode pad 4 and the Si chip 3 so as to suppress the movement as described above.

【００２１】上記拘束力は、電極パッド４とＳｉチップ
３との間の接合面積の大きさに依存するものであるが、
複数の電極パッド４のそれぞれに、上記重心位置Ｇ方向
へ延長された形状の張り出し部４ａを形成する構成とな
っているから、電極パッド４とＳｉチップ３との間に働
く拘束力が、上記重心位置Ｇ方向について大きくなる。
この場合、張り出し部４ａにあっては、重心位置Ｇと反
対方向の部分では引張方向の拘束力を受ける関係上、ク
ラックを生ずる可能性があるが、重心位置Ｇ方向の部分
では圧縮方向の拘束力を受ける関係上、クラックを生じ
難いものである。従って、電極パッド４の重心位置Ｇ方
向への張り出し寸法Ｐは、クラックの発生防止に大きく
寄与するものであり、その寸法効果が大きくなる。The above-mentioned binding force depends on the size of the bonding area between the electrode pad 4 and the Si chip 3.
Since each of the plurality of electrode pads 4 has a configuration in which the projecting portion 4 a extending in the direction of the center of gravity G is formed, the restraining force acting between the electrode pad 4 and the Si chip 3 is limited to the above-described range. It increases in the direction of the center of gravity G.
In this case, in the protruding portion 4a, a crack may be generated in a portion in a direction opposite to the center of gravity G due to receiving a restraining force in a tensile direction. Cracks are unlikely to occur because of the force. Accordingly, the overhang dimension P of the electrode pad 4 in the direction of the center of gravity position G greatly contributes to the prevention of the occurrence of cracks, and the dimensional effect is increased.

【００２２】このように、各電極パッド４において大き
な拘束力が得られる結果、それらの電極パッド４がＳｉ
チップ３上で滑ることに起因した位置ずれや断線を来た
したり、或いは電極パッド４の周囲を覆うように設けら
れている絶縁保護膜５にクラックが発生するなどの虞が
なくなり、実装状態での接続信頼性が向上するようにな
る。As described above, a large restraining force is obtained in each of the electrode pads 4, and as a result, the electrode pads 4
There is no danger of displacement or disconnection due to slipping on the chip 3 or cracking of the insulating protective film 5 provided so as to cover the periphery of the electrode pad 4. Connection reliability is improved.

【００２３】因みに、図４には、重心位置Ｇとの間の距
離ΔＳが例えば１．９８mmに設定されたはんだバンプ電
極２を備えたフリップチップ１について、張り出し寸法
Ｐが異なるサンプルを複数個用意し、これらのサンプル
を配線基板（アルミナ基板）に実装した状態で温度サイ
クル試験を行った結果を示す。但し、温度サイクルの条
件は−４０℃〜＋１２５℃各３０分、データサンプリン
グは５００回、１０００回、１５００回の温度サイクル
終了時に行った。この図４からは、張り出し寸法Ｐが図
３中の斜線帯の範囲に収まるサンプル（張り出し寸法Ｐ
が２９μｍ程度より大きいサンプル）については、電極
パッド４の位置ずれが全く発生していないことが理解で
きる。In FIG. 4, a plurality of samples having different overhang dimensions P are prepared for the flip chip 1 having the solder bump electrodes 2 whose distance ΔS from the center of gravity G is set to, for example, 1.98 mm. The results of performing a temperature cycle test with these samples mounted on a wiring board (alumina substrate) are shown. However, the temperature cycle conditions were −40 ° C. to + 125 ° C. for 30 minutes each, and data sampling was performed at the end of 500, 1000, and 1500 temperature cycles. From FIG. 4, a sample in which the overhang dimension P falls within the range of the hatched area in FIG.
It can be understood that no positional displacement of the electrode pad 4 has occurred at all for the sample of which is larger than about 29 μm).

【００２４】また、本実施例によれば、上記のような効
果を得るために、電極パッド４の形状に変更を加えるだ
けで済むから、従来のように全体の構成が複雑化する虞
がなくなり、製造コストの高騰を抑制できるようにな
る。Further, according to this embodiment, in order to obtain the above-mentioned effects, it is only necessary to change the shape of the electrode pad 4, so that there is no danger that the overall configuration becomes complicated as in the prior art. Thus, it is possible to suppress a rise in manufacturing cost.

【００２５】（第２の実施形態）尚、上記第１実施例で
は、電極パッド４を楕円近似形状としたが、これに限定
されるものではなく、例えば本発明の第２実施例を示す
図５のように矩形状の電極パッド４′を設ける構成とし
ても良い。この場合においても、電極パッド４′の張り
出し部４ａ′における重心位置Ｇ方向への延長部分の張
り出し寸法Ｐを、その重心位置Ｇとの間の距離ΔＳが長
い状態にあるはんだバンプ電極２に対応したものほど長
くなるように設定することになる。(Second Embodiment) In the first embodiment, the electrode pad 4 has an elliptical shape. However, the present invention is not limited to this. For example, the figure shows a second embodiment of the present invention. 5, a rectangular electrode pad 4 'may be provided. Also in this case, the overhang dimension P of the extension of the electrode pad 4 'in the direction of the center of gravity G in the overhang portion 4a' corresponds to the solder bump electrode 2 in which the distance ΔS from the center of gravity G is long. It will be set to be longer as you do.

【００２６】（第３の実施形態）また、本発明の第３実
施例を示す図６のように、第１実施例における電極パッ
ド４に代えて、多角形状の電極パッド４″を設ける構成
としても良い。この場合においても、電極パッド４″の
張り出し部４ａ″における重心位置Ｇ方向への延長部分
の張り出し寸法Ｐを、その重心位置Ｇとの間の距離ΔＳ
が長い状態にあるはんだバンプ電極２に対応したものほ
ど長くなるように設定することになる。(Third Embodiment) As shown in FIG. 6 showing a third embodiment of the present invention, a configuration in which a polygonal electrode pad 4 ″ is provided instead of the electrode pad 4 in the first embodiment. In this case as well, the extension dimension P of the extended portion of the electrode pad 4 ″ in the direction of the center of gravity G at the projecting portion 4a ″ is determined by the distance ΔS from the center of gravity G
Is set to be longer as the solder bump electrode 2 is longer.

【００２７】（その他の実施形態）尚、本発明は上記し
た実施例に限定されるものではなく、次のような変形ま
たは拡張が可能である。例えば第１実施例においては、
複数の電極パッド４の全てに、重心位置Ｇ方向への延長
部分を備えた張り出し部４ａを形成する構成としたが、
少なくとも１個の電極パッド４に対して延長部分を備え
た張り出し部４ａを形成する構成としても、ある程度の
効果が得られるものである。(Other Embodiments) The present invention is not limited to the above-described embodiment, but can be modified or expanded as follows. For example, in the first embodiment,
Although the overhanging portion 4a having an extension in the direction of the center of gravity G is formed on all of the plurality of electrode pads 4,
Some effect can be obtained even when the overhanging portion 4a having the extension is formed for at least one electrode pad 4.

【００２８】この場合、上記張り出し部４ａを、少なく
とも上記重心位置Ｇとの間の距離ΔＳが最も長い状態に
あるはんだバンプ電極２と対応した電極パッド４に形成
する構成としても良い。つまり、フリップチップ１の実
装状態において最も大きな熱応力が作用するのは、重心
位置Ｇとの間の距離ΔＳが最も長い状態にあるはんだバ
ンプ電極２と対応した電極パッド４であるから、少なく
ともこの電極パッド４に張り出し部４ａを形成する構成
とすれば、所期の目的を達成することが可能になるケー
スも出てくる。In this case, the overhanging portion 4a may be formed on the electrode pad 4 corresponding to the solder bump electrode 2 in which the distance ΔS between the center of gravity G and the center of gravity G is longest. That is, in the mounting state of the flip chip 1, the largest thermal stress acts on the electrode pad 4 corresponding to the solder bump electrode 2 in which the distance ΔS between the center of gravity G and the center of gravity is the longest. If the overhanging portion 4a is formed on the electrode pad 4, there may be cases where the intended purpose can be achieved.

【００２９】内部配線層を多層構造としたフリップチッ
プに適用する場合には、実装面に対し最も傾斜が大きく
なる内部配線層（一般的には最上層の内部配線層）に対
応した電極パッドに対して、第１実施例と同様の張り出
し部を形成する構成とすれば良い。When the present invention is applied to a flip chip having an internal wiring layer having a multilayer structure, an electrode pad corresponding to an internal wiring layer (generally, the uppermost internal wiring layer) having the largest inclination with respect to the mounting surface is used. On the other hand, the overhanging portion may be formed in the same manner as in the first embodiment.

【００３０】表面実装素子の例としてフリップチップ１
を挙げたが、電極パッド及びこの電極パッド上に形成さ
れたはんだバンプ電極を備えた表面実装素子（例えば半
導体用パッケージ、受動チップ部品など）に広く適用で
きるものである。Flip chip 1 is an example of a surface mount device.
However, the present invention can be widely applied to a surface mount device (for example, a semiconductor package, a passive chip component, or the like) including an electrode pad and a solder bump electrode formed on the electrode pad.

【００３１】複数の電極パッドが設けられる素子本体の
線膨張係数が、その実装用の配線基板の線膨脹係数より
大きい場合には、温度が低下した状態時において、電極
パッドに対し、はんだバンプ電極群の分布に関しての重
心位置方向と反対の方向へ移動させようとする力が作用
することになるから、複数の電極パッドのうちの少なく
とも１個以上に、はんだバンプ電極群の分布に関しての
重心位置方向と反対の方向へ延長された形状の張り出し
部を形成する構成とすれば良いものである。When the linear expansion coefficient of the element body on which a plurality of electrode pads are provided is larger than the linear expansion coefficient of the wiring board for mounting the same, the solder bump electrode is placed on the electrode pad when the temperature is lowered. Since a force to move in the direction opposite to the direction of the center of gravity with respect to the distribution of the group acts, at least one or more of the plurality of electrode pads has the position of the center of gravity with respect to the distribution of the solder bump electrode group. What is necessary is just to make it the structure which forms the overhang | projection part extended in the direction opposite to the direction.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施例を示すフリップチップの概
略的正面図FIG. 1 is a schematic front view of a flip chip showing a first embodiment of the present invention.

【図２】フリップチップにおけるはんだバンプ電極部分
の縦断面図FIG. 2 is a longitudinal sectional view of a solder bump electrode portion in a flip chip.

【図３】はんだバンプ電極群の分布に関しての重心位置
及びはんだバンプ電極間の距離と、電極パッドの張り出
し部の張り出し寸法との関係を示す特性図FIG. 3 is a characteristic diagram showing the relationship between the position of the center of gravity and the distance between the solder bump electrodes with respect to the distribution of the solder bump electrode group, and the overhang dimension of the overhang portion of the electrode pad.

【図４】温度サイクル試験の結果を示す図FIG. 4 is a diagram showing the results of a temperature cycle test.

【図５】本発明の第２実施例を示す図１相当図FIG. 5 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

【図６】本発明の第３実施例を示す図１相当図FIG. 6 is a view corresponding to FIG. 1, showing a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１…フリップチップ（表面実装素子）、２…はんだバン
プ電極、３…Ｓｉチップ（素子本体）、４、４′、４″
…電極パッド、４ａ、４ａ′、４ａ″…張り出し部、８
…はんだバンプを示す。DESCRIPTION OF SYMBOLS 1 ... Flip chip (Surface mount element), 2 ... Solder bump electrode, 3 ... Si chip (Element body), 4, 4 ', 4 "
... Electrode pads, 4a, 4a ', 4a "... Overhang, 8
... Indicates a solder bump.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 素子本体の実装面に複数の電極パッドを
配置すると共に、各電極パッド上にはんだバンプ電極を
形成して成る表面実装素子の電極構造において、 前記複数の電極パッドのうちの少なくとも１個以上に、
前記はんだバンプ電極群の分布に関しての重心位置方向
若しくはこれと反対の方向へ延長された形状の張り出し
部を形成したことを特徴とする表面実装素子の電極構
造。1. An electrode structure for a surface mount device comprising a plurality of electrode pads arranged on a mounting surface of an element body and solder bump electrodes formed on each electrode pad, wherein at least one of the plurality of electrode pads is provided. One or more
An electrode structure for a surface-mounted element, wherein a protruding portion extending in the direction of the center of gravity with respect to the distribution of the solder bump electrode group or in the direction opposite thereto is formed. 【請求項２】 前記張り出し部は、少なくとも前記重心
位置との間の距離が最も長い状態にあるはんだバンプ電
極と対応した電極パッドに形成されることを特徴とする
請求項１記載の表面実装素子の電極構造。2. The surface mount device according to claim 1, wherein the overhang portion is formed on an electrode pad corresponding to a solder bump electrode in a state where at least a distance from the position of the center of gravity is longest. Electrode structure. 【請求項３】 前記張り出し部は複数の電極パッドに形
成され、 各張り出し部は、前記重心位置との間の距離が長い状態
にあるはんだバンプ電極に対応したものほど張り出し寸
法が長くなるように設定されることを特徴とする請求項
１記載の表面実装素子の電極構造。3. The overhanging portion is formed on a plurality of electrode pads, and each overhanging portion has a longer overhanging dimension corresponding to a solder bump electrode having a longer distance from the position of the center of gravity. The electrode structure of a surface mount device according to claim 1, wherein the electrode structure is set. 【請求項４】 複数形成された張り出し部は、それぞれ
の張り出し寸法が、前記重心位置と当該張り出し部に対
応するはんだバンプ電極との間の距離の１．１乗に比例
した値に設定されることを特徴とする請求項３記載の表
面実装素子の電極構造。4. A plurality of overhanging portions each having an overhanging dimension set to a value proportional to the 1.1 power of the distance between the position of the center of gravity and the solder bump electrode corresponding to the overhanging portion. The electrode structure of a surface mount device according to claim 3, wherein:
JP09376497A 1997-04-11 1997-04-11 Electrode structure of surface mount device Expired - Fee Related JP3758289B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09376497A JP3758289B2 (en) 1997-04-11 1997-04-11 Electrode structure of surface mount device

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Application Number Priority Date Filing Date Title
JP09376497A JP3758289B2 (en) 1997-04-11 1997-04-11 Electrode structure of surface mount device

Publications (2)

Publication Number Publication Date
JPH10284500A true JPH10284500A (en) 1998-10-23
JP3758289B2 JP3758289B2 (en) 2006-03-22

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6736306B2 (en) 2001-02-05 2004-05-18 Samsung Electronics Co., Ltd. Semiconductor chip package comprising enhanced pads
JP2006513648A (en) * 2003-01-20 2006-04-20 エプコス　アクチエンゲゼルシャフト Small board surface electrical components
US8022556B2 (en) 2003-01-20 2011-09-20 Epcos Ag Electrical component having a reduced substrate area
WO2013085492A1 (en) * 2011-12-06 2013-06-13 Intel Corporation Shaped and oriented solder joints
US9233835B2 (en) 2011-12-06 2016-01-12 Intel Corporation Shaped and oriented solder joints
US9564412B2 (en) 2011-12-06 2017-02-07 Intel Corporation Shaped and oriented solder joints
EP3246940A1 (en) * 2016-05-19 2017-11-22 MediaTek Inc. Semiconductor package assembly
CN107403786A (en) * 2016-05-19 2017-11-28 联发科技股份有限公司 Semiconductor package
US10199318B2 (en) 2016-05-19 2019-02-05 Mediatek Inc. Semiconductor package assembly
US10468341B2 (en) 2016-05-19 2019-11-05 Mediatek Inc. Semiconductor package assembly
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