JPS58188134A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPS58188134A JPS58188134A JP7086682A JP7086682A JPS58188134A JP S58188134 A JPS58188134 A JP S58188134A JP 7086682 A JP7086682 A JP 7086682A JP 7086682 A JP7086682 A JP 7086682A JP S58188134 A JPS58188134 A JP S58188134A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- film
- wiring
- stepping
- silica
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 235000014121 butter Nutrition 0.000 claims 1
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 24
- 239000010408 film Substances 0.000 abstract 5
- 239000010409 thin film Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000010410 layer Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、牛導体集積回路（以下単に集積回路という）
の製造方法に関し、特に集積回路基板の一生面側に形成
される金属配線の写真蝕刻（フォトリソグラフィという
）に関する。[Detailed Description of the Invention] The present invention relates to a conductor integrated circuit (hereinafter simply referred to as an integrated circuit).
The present invention relates to a manufacturing method, and particularly to photolithography of metal wiring formed on the entire surface of an integrated circuit board.
従来、集積回路の金属配線形成は、牛導体基板の一生面
側に金属Ｍを被着後、フォトレジストを塗布し、目合せ
無光を行なってフォトレジストをパターニングし、この
フォトレジストをマスクとして金緘膜を蝕刻することに
より行なわれていた。Conventionally, metal wiring for integrated circuits has been formed by depositing metal M on the entire surface of a conductor substrate, applying photoresist, performing alignment without light, patterning the photoresist, and using this photoresist as a mask. This was done by etching the gold membrane.
しかしながら、集積回路の集積度が増加し、構造も多層
構造となってきている。構造が多層になるにつれ、集積
回路基板表面に段差が増加し、多層構造上に形成される
金属配線の７オ） ＩＪングラフィも非常に困難となる
。特に、金属配線が微細となり配線間隔が非常に小さく
なった場合、通常ポジ型のフォトレジストが用いられる
が、ポジ型のフォトレジストを金属配線のフォトリング
ラフィとして使用すると１段差底部のフォトレジストは
厚くなりフォトレジストは光が照射されても段差が大き
いと未露光となり、金属配線間が短絡してしまうという
不都合が生ずる。さらに、金属被膜は反射率が大きい為
、微細な配線パターンそのもののフォトリングラフィが
行ない難い。However, the degree of integration of integrated circuits has increased, and their structures have become multilayered. As the structure becomes more multilayered, the number of steps on the surface of the integrated circuit board increases, making it extremely difficult to perform IJ printing of metal wiring formed on the multilayer structure. In particular, when metal wiring becomes fine and the wiring spacing becomes very small, a positive type photoresist is usually used, but when a positive type photoresist is used for photolithography of metal wiring, the photoresist at the bottom of the one step difference is Even if the photoresist becomes thick and has large steps even if it is irradiated with light, the photoresist will not be exposed to light, causing the inconvenience of short-circuiting between metal wirings. Furthermore, since the metal film has a high reflectance, it is difficult to perform photolithography of the fine wiring pattern itself.
すなわち、第１図により従来の集積回路の金属配線形成
の一例を説明する。第１図において、１■Ｐ型シリコン
基板、２はＮ十拡散層、３はゲート酸化膜、４け一層目
のポリシリコン電電、５は層間絶縁膜、６は２層目のポ
リシリコン電極、７は層間絶縁膜、８Ｆｉアル＜ニウム
の金属配線で、絶縁膜７の上に一様にアルオニウムを被
着後、ポジ型の７オトレジスト１０ｍ、１０ｂをマスク
として異方性のドライエ、チングによシ形成されたもの
である。That is, an example of the formation of metal wiring in a conventional integrated circuit will be explained with reference to FIG. In FIG. 1, 1 is a P-type silicon substrate, 2 is an N+ diffusion layer, 3 is a gate oxide film, 4 is a first-layer polysilicon electrode, 5 is an interlayer insulating film, 6 is a second-layer polysilicon electrode, 7 is an interlayer insulating film, 8Fi Al<Nium metal wiring. After uniformly depositing Al on the insulating film 7, anisotropic dry etching and etching are performed using positive type 7 photoresist 10m and 10b as a mask. It was formed.
ところで、第１図において、フォトレジスト１０ａと１
０ｂの間が急峻な段差部となっており、この段差底部は
フォトレジスト塗布時に厚くなり１このフォトレジスト
のパターニングの際、厚い段差底部の７オトレジストの
一部分１０８は未露光となって溶解されずに残る。し九
がって、このレジメ）ＩＯＣの下側のアルミニウム（以
下アルミと略称する）８ｍは蝕刻されずに残ることにな
る。By the way, in FIG. 1, photoresists 10a and 1
There is a steep step between 0 and 0b, and the bottom of this step becomes thick when photoresist is applied.1 When patterning this photoresist, a part 108 of the photoresist at the bottom of the thick step becomes unexposed and is not dissolved. remains in Therefore, under this regime, 8 m of aluminum (hereinafter abbreviated as aluminum) below the IOC will remain unetched.
なお、微細な配線パターンの工、チングの場合。In addition, in the case of machining and chiming of fine wiring patterns.
異方性のドライエ、チを行うので、段差壁面のアルミも
、垂直方向だけからエツチングを受けるので一部壁面に
博く残ることＫなり、段差をはさむ両配線が短絡する危
険性が起る。Since anisotropic dry etching is performed, the aluminum on the step wall is also etched only from the vertical direction, so that a portion of the aluminum remains on the wall, creating a risk of short-circuiting between the two wirings sandwiching the step.
本発明の目的は、段差の大きい多層構造を有する集積回
路のフォトリゾグラフィにおいて、段差底部のフォトレ
ジストの除去不完全による配線間の短絡事故を有効に防
止できる集積回路の製造方法を揚供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an integrated circuit that can effectively prevent short-circuit accidents between wiring lines due to incomplete removal of photoresist at the bottom of a step in photolithography of an integrated circuit having a multilayer structure with large steps. be.
本発明の製造方法は、半導体基板の一生面側に金属膜４
ｊｉ！を形成する際に、前記半導体基板の一生面側に金
属配線用金属膜を被着後前記金属膜の上にシリカフィル
ムを塗布し、このシリカフィルムを写真蝕刻により蝕刻
し、つぎに前記金属膜を蝕刻し、金輌配紳パターンを形
成するものである。In the manufacturing method of the present invention, a metal film 4 is formed on the whole surface side of a semiconductor substrate.
ji! When forming the semiconductor substrate, a metal film for metal wiring is deposited on the whole side of the semiconductor substrate, a silica film is applied on the metal film, the silica film is etched by photolithography, and then the metal film is formed on the semiconductor substrate. It is etched to form a gold medallion pattern.
つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.
第２図は本発明の一実施例の工程途中段階の断面図であ
る。第２図において、第１図に示す例との違いは、アル
ミの金属配線８の上にシリカフィルム１１を塗布してい
る。シリカフィルム１１はフォトレジストと同様に段差
底部で厚くなるという特性があるので１段差底部にシリ
カフィルム１１の傾斜がつき、シリカフィルム１１の上
に被着したフォトレジストに光照射を行った場合、フォ
トレジストが段差底部に残ることはなくなる。フォトレ
ジストをマスクとしてシリカフィルム１１を除去し、さ
らにアルミ８を異方性のドライエ、チング法で除去する
。この場合５段差壁面にはアルミが僅か歿るが１段差底
部のアルずは完全に除去されるので段差部を間にし九ア
ル々配線８．８間の短絡はなくなる。FIG. 2 is a sectional view of an embodiment of the present invention at an intermediate stage in the process. In FIG. 2, the difference from the example shown in FIG. 1 is that a silica film 11 is coated on the aluminum metal wiring 8. The silica film 11 has a characteristic that it becomes thicker at the bottom of the step like a photoresist, so when the silica film 11 is inclined at the bottom of the step and the photoresist deposited on the silica film 11 is irradiated with light, No photoresist remains at the bottom of the step. The silica film 11 is removed using a photoresist as a mask, and the aluminum 8 is further removed using an anisotropic dry etching method. In this case, there is a slight amount of aluminum on the 5-step wall surface, but the aluminum at the bottom of the 1-step difference is completely removed, so there is no short circuit between the 9-aluminum wires 8 and 8 across the step.
さらに、アルミに塗布し之シリカフィルムによりアルミ
の反射が防止できるので微細なフォトレジストパターン
が精度よく形成できる。Furthermore, since the silica film applied to the aluminum can prevent reflection of the aluminum, a fine photoresist pattern can be formed with high precision.
第１図は従来の集積回路の金属配線形成を説明する工程
途中の一段階の断面図、第２図は本発明の一実施例の工
程途中の一段階の断面図である。
１ ・・・Ｐ型シリコン基板、２・・・・・・Ｎ＋拡散
層、３・・・・・・ゲート酸化膜、４・・・・・・一層
目ポリシリコン電極、５，７・・・・・・層間絶縁膜、
６・・・・・・２層目ポリシリコン電極、８・・・・・
・アルンの金属配線、１０暑。
１０ｂ フォトレジスト膿、１１ ・・・シリカフ
ィルム。FIG. 1 is a cross-sectional view of one step in the process for explaining the formation of metal wiring in a conventional integrated circuit, and FIG. 2 is a cross-sectional view of one step in the process of an embodiment of the present invention. 1... P-type silicon substrate, 2... N+ diffusion layer, 3... gate oxide film, 4... first layer polysilicon electrode, 5, 7... ...interlayer insulating film,
6... Second layer polysilicon electrode, 8...
・Arun's metal wiring, 10 heat. 10b Photoresist pus, 11...Silica film.
Claims (1)
集積回路の製造方法において、前記午導体基板の一主面
側圧金属配線用金属膜を被着後前記金属膜の上にシリカ
フィルムを塗布し、とのシリカフィルムを写真蝕刻によ
り蝕刻し、つぎ罠金属膜を蝕刻し金属配線バターｙを形
成することを特徴とする集積回路の製造方法。A method for manufacturing an integrated circuit including a step of forming a lateral pressure metal wiring on one main surface of the conductor substrate, after depositing a metal film for the lateral pressure metal wiring on one main surface of the conductor substrate, a silica film is placed on the metal film. A method for producing an integrated circuit, comprising coating the silica film, etching the silica film by photolithography, and then etching the trap metal film to form a metal wiring butter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7086682A JPS58188134A (en) | 1982-04-27 | 1982-04-27 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7086682A JPS58188134A (en) | 1982-04-27 | 1982-04-27 | Manufacture of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58188134A true JPS58188134A (en) | 1983-11-02 |
Family
ID=13443906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7086682A Pending JPS58188134A (en) | 1982-04-27 | 1982-04-27 | Manufacture of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58188134A (en) |
-
1982
- 1982-04-27 JP JP7086682A patent/JPS58188134A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2803999B2 (en) | Method for manufacturing fine pattern of semiconductor device | |
| JPH09181059A (en) | Manufacture of fine pattern of semiconductor device | |
| JPS6211068B2 (en) | ||
| JPS58188134A (en) | Manufacture of integrated circuit | |
| JPH0458167B2 (en) | ||
| JPS633453B2 (en) | ||
| JPS5828735B2 (en) | hand tai souchi no seizou houhou | |
| JPS61113062A (en) | Photomask | |
| KR0144019B1 (en) | Forming method of metal connection in semiconductor | |
| KR100214261B1 (en) | Method for forming metal wiring in semiconductor device | |
| KR930006133B1 (en) | M.o.s. contact hole forming method | |
| KR970002430B1 (en) | Photoresist patterning method of semiconductor device | |
| JPH0123944B2 (en) | ||
| KR100252757B1 (en) | Method of forming metal pattern | |
| KR100329605B1 (en) | Method for manufacturing metal wiring in semiconductor device | |
| JP2809274B2 (en) | Method for manufacturing semiconductor device | |
| JPS61137345A (en) | Manufacture of semiconductor device | |
| JPH0574951A (en) | Manufacture of semiconductor device | |
| JP2811724B2 (en) | Etching method | |
| JPS61117832A (en) | Manufacture of semiconductor device | |
| JPH03127827A (en) | Manufacture of semiconductor device | |
| JPH03263834A (en) | Manufacture of semiconductor device | |
| JPS60106132A (en) | Formation of pattern | |
| JPH09186233A (en) | Manufacture of semiconductor device | |
| JPS59103343A (en) | Manufacture of semiconductor device |