JPS58187990A - Image processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to an example: - A double scratch processing device used in an airport surveillance radar, etc., which simultaneously displays radar video signals, alphanumeric characters, special symbols, etc. using a rask scanning method. Regarding.

[Technical background of the invention and its problems]

As is well known, indicators used in airport surveillance radars display characters or special symbols that indicate the position of the 0 column, aircraft name, altitude, etc., processed by a computer and a function generator. Recently, an increasing number of indicators of this type are based on the rask scanning method, which is low in cost and easy to downsize.In this method, the refresh memory for storing digital image data such as the characters or special symbols is equal to the image resolution. Although this is necessary, recent improvements in IC technology have made it possible to realize large-capacity memory elements at low cost, making it possible to fully put such an indicator into practical use.

By the way, when displaying data such as symbols on this type of indicator, this data is written into the reflex memory in sequence and read out in correspondence with scanning. When changing the written data, new data is written after erasing the data written to the memory. In this case, if the frequency of data changes is low, it is sufficient to wait until the next data is displayed. General interaction! There is no problem with this method for a rask scanning type indicator called a type. However, when displaying targets and various types of signals obtained from radar images as described above on an indicator using the rask scanning method, these signals, etc. must be changed every time the target moves, and this frequency is at least 125 ms. It may be done in units of In the case of 9, if the contents of the memory are not changed during the period from displaying one frame of rask scanning to displaying the next frame, the display screen will flicker. Generally, this is possible by performing erasing and writing to the memory during the vertical synchronization period (pulsing period) of the display screen and increasing the writing speed of this memory. However, the memory reload/write speed is MO8
Even in an IC, the processing speed is about 0.5 μS, and the processing speed of a function generator that generates various singels is about OL 1 μ3 at maximum.

Therefore, since the processing speed of the function generator is faster than the memory speed, it is difficult to prevent the display screen from flickering unless the memory speed is equivalently increased and as much data as possible is written during the blanking period. It is.

[Purpose of the invention]

This invention was made based on the above circumstances, and its purpose is to equivalently increase the writing speed of memory so that data that moves or changes rapidly can be displayed without flickering on the screen. The present invention aims to provide an image processing device.

[Summary of the invention]

This invention divides the memory into a plurality of memory blocks and memory planes corresponding to the processing speed of the function generator, and uses the divided memory to address the point data that constitutes the display code output from the function generator. By time-divisionally specifying , it is possible to synchronize a function generator with a fast processing speed with a memory with a slow read/write cycle, and equivalently increase the read speed of the memory.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, data D output from an external device such as a computer is stored in a refresh data memory. This data change is carried out at any time and in any period using the external 7a device, and the minimum period for this change is 125 m3. This stored data is stored in the second
As shown in FIG. li] This data is processed for each non-bill class 8i, and the classification code ID for circles, straight lines, etc., and the center coordinates ΔX, ΔY9 for circles, radius Δ! , Δy, and in the case of a straight line, the length Δ! , Δy to lN. The data stored in this refresh data memory 11 is
The signals are sequentially read out during the vertical blanking period of the indicator 18 (shown in FIG. 10 (0)) and supplied to the function generator 12 for each data block (5 words). This function generator 1
2 is constructed as shown in FIG.

In FIG. 3, the data of each block read from the refresh data memory 11 is stored in a register 12.
1, and the data in this register 121 is stored in the function generating circuit 12.1. supplied to This function generating circuit 12. is a circuit called a refraction digital differential analyzer, which outputs and processes various types of thin lines, etc. as point data based on the supplied data. That is, if it is a straight line, as shown in Figure 4 (a) l2, if it is a circle, as shown in Figure 4 (h), these non-bills are sequentially output as a plurality of point data in the direction of the arrow (2).Actual output Therefore, each point # (address) of these point data corresponds to the storage location (at °
The signals are divided and outputted to the X position register 12, BeY position register 124, respectively, in accordance with the address). Each of these registers 12. , 124 are constructed as shown in FIGS. 5(a), (b) and r. Register 12. ．． The lower 4 bits P^ of 1!4 indicate the plane address and block address of the register 12. ．． 12° each upper pitch) MA
x and MA l indicate each memory address of the memory 14. The address of the point data output in this format is supplied to the write controller 13, and a high level signal (luminance information) is written to the specified address of the refresh/arm turn memory 14 via the write controller 1s. be included.

By the way, in general, the function generation circuit 12. As mentioned above, the processing speed is faster than the continuous read/write cycle of the memory 14, and when one screen of memory is written by specifying one set of write addresses, the function generation occurs in the read/write cycle of the memory 14. The speed is limited, and it becomes impossible to operate faster than this.Therefore, the memory 14 is divided into several pieces, one screen is allocated using the divided memory 14, and the divided memory 14 By operating in a time-division manner, it is possible to equivalently increase the write speed of the memory 14.

The configuration of the refresh motherboard memory 14 will be described below. As shown in FIG. 6, the screen of the indicator 18 is composed of 512×512=256 bits in the vertical and horizontal directions. The data for one screen is stored in four memory blocks (J4.. as shown in FIG. 7).

24,. 74. ．． 144).

This memory block 14. ~14. has four memory planes of 16 bits each (741a to 141d, 14
**~14*d, 143&~14@d, 144*~14
46), and the memory block 141 has a first scanning line, a $5 scanning line, a ninth scanning line, etc. shown in FIG.
・The address corresponding to the 509th scanning line is assigned,
Memory block 14 has 2nd scan line, 6th scan line...
- An address corresponding to the 510th scanning line is allocated. Furthermore, the memory block 141 includes a third scanning line, a seventh scanning line, and a seventh scanning line.
Scanning line: An address corresponding to the 511th scanning line is allocated, and the memory block 144 has the address corresponding to the 4th scanning line, the 8th scanning line, etc.
Scanning line: An address corresponding to the 512th scanning line is assigned. To further explain the memory block 141, the first scanning line is allocated to each memory plane 141a to 141d every four pits as shown in FIG. In other words, addresses corresponding to 1 pit, 5 pits, . . . 509 bits are assigned to the memory plane 14 Sumirebatake, addresses corresponding to 2 bits, 6 pits, . Addresses corresponding to 4 bits, 8 bits, . . . 512 pits are assigned to the memory plane 141d.

The refresh master turn memory 14 configured as described above is connected to the input controller 13 as shown in FIG.
The following write operation is performed. That is, the X position register 12. of the function generator 12. , X position register 12
The data stored in 4 is stored in the current position register 131. Among these, memory addresses MAx and MAm shown in FIG. 5(&)(b) are address registers CIJ, .
13m.

No. 13, 73. ), and a predetermined address is represented by the combined value of MAI and MA. Also.

Three block addresses and f lane address FA are each decoder 13. ．． 13. is supplied to and decoded.

This decoder 13. designates a corresponding memory block from memory blocks 14° to 144 based on the three block addresses, and this output signal is sent to the address register 13. ~13. is supplied to the corresponding one as a date signal. In addition, 13 decoders are installed in each memory block 14 based on 712,711 players.
．． ~144 memory planes (14a ae 14
n b * J 4 n c * 14 n d)
(However, for wolves, 1.2.3.4) is specified.

Therefore, these decoders 13. ．． 13. by 1
memory blocks and one memory plane in this memory block are specified, one location of this specified memory plane is specified by an address register,
A high level signal is written to this designated address. By sequentially performing such operations, it becomes possible to sequentially write high level signals into the refresh pattern memory 14 in correspondence with the address data sequentially output from the function generator 12. That is, if the processing speed of the function generator Hxx is, for example, 125 μs and the read/write cycle of the refresh pattern memory 14 is, for example, 0.5 μs, the processing speed of the function generator 12 and the processing speed of the refresh pattern memory 14 can be completely controlled. It becomes possible to operate synchronously.

When the write operation is performed as described above, the fresh Δturn memory 14 is transferred to the indicator 18 as shown in FIG. 10(d).
is read out in synchronization with raster scanning during the display period. That is, the synchronization signal generator 15 shown in FIG. 1 outputs the vertical synchronization signal (2) and horizontal synchronization signal H necessary for raster scanning, and also outputs the address of the refresh/turn memory 14 in response to raster scanning. The specified address data is output. This address data WA is shown in FIG. 5(a).
It has the same configuration as the output data of the function generator 12 shown in (b). This address data W is supplied to a continuation controller 16, and the data stored in the refresh pattern memory 14 is read out via the readout controller 16.

That is, this read controller 16 has the same configuration as the loading controller 13 shown in FIG. 9, and the block address and plane address specified by the address data W are decoded by the decoder,
Data at the address specified by the memory address in the address data W is read from the memory plane specified by the plane address.

The data sequentially generated in this way is supplied to the synthesizer 11 together with the vertical synchronizing signal v1 and the horizontal synchronizing signal H output from the synchronizing signal generator 15, and these synchronizing signals v,
Synthesized with H.

This combined signal is supplied to the indicator 18 and displayed.

In addition, FIG. 10(a) shows the vertical synchronization signal, and FIG. 10(b) shows the vertical synchronization signal.
indicates a vertical drive waveform.

Depending on the configuration described in F, the refresh arm turn memory 14
four memory blocks 14. ~144, and each memory block 14. ~144 is further divided into four memory planes 14n*~14nd (where n = 112
#314), and this memory block 141~
144, memory planes 14na to 74nd, and addresses within memory planes 14na to 14na can be specified, respectively. Therefore, data can be written in response to the output of the function generator 12, which has a speed four times faster than the read/write cycle of the refresh memory 14, so that targets with short movement or change periods can be written. It can be displayed without flickering on the entire screen.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide an image processing apparatus that can increase the memory write speed under equal constraints and can display data that moves on a tatami mat or changes rapidly without flickering on the screen.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of an image processing device according to the present invention, FIG. 2 is a diagram shown for explaining the contents of data supplied from an external device, and FIG. 3 is a configuration diagram of a function generator. Figures 4(a) and 1(b) are diagrams showing the operation of the function generator, and Figures 5(a) and (b) are diagrams showing the operation of the function generator, respectively.
FIG. 5 shows the output format of the function generator, respectively. FIGS. 6 and 7 are diagrams shown to explain the display screen and memory allocation for the display screen, respectively. FIG. 8 shows the configuration of the refresh arm turn memory. 9 is a diagram showing the structure of the write controller and refresh pattern memory.
0 (&) to (d) are diagrams shown for explaining the present invention in detail, respectively. 11... Refresh-data memory, 12... Function generator, 13... Write controller, 14... Refresh arm turn memory, 141-144... Memory block, 1411-14xa, 14* *~14*a. 14sa to l4s4, 144t to 144d...Memory grain, 15...Synchronizing signal generator, 1σ...Reading controller, 18...Indicator.

Claims (1)

[Claims] A first memory for storing digitized display code data; and a third output function that reads out the display code data during the vertical blanking period of the indicator and converts the display code based on this data into addresses of a plurality of point data. a generator, a second memory divided into a plurality of memory blocks and memory planes corresponding to the processing speed of this function generator, and a memory block, memory plane, and memory address of this memory for the point data. A write controller that writes a predetermined signal specified by an address in a time-division manner, a continuous controller that sequentially reads out the written signal corresponding to the rask scan during the display period of the indicator, 1. An image processing device comprising: an indicator that displays a signal.