GB2180128A - Window graphics system - Google Patents

Window graphics system Download PDF

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Publication number
GB2180128A
GB2180128A GB8521421A GB8521421A GB2180128A GB 2180128 A GB2180128 A GB 2180128A GB 8521421 A GB8521421 A GB 8521421A GB 8521421 A GB8521421 A GB 8521421A GB 2180128 A GB2180128 A GB 2180128A
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store
bus
priority
pixel
data
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GB2180128B (en )
GB8521421D0 (en )
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Richard J Westmore
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ANAMARTIC Ltd
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ANAMARTIC Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14Display of multiple viewports

Abstract

The system comprises a plurality, e.g. some tens or hundreds, of microframe stores 10, each having the capacity to store one "pane" of a window in world-space, where a pane occupies a relatively small rectangular area of the display screen, say around 10%. A graphics processor 11 and store controller 12 enable data to be written into the microframe stores and also to send to each store coordinate values defining its position in screen space. Video data is read out from the stores onto a pixel bus 18 synchronously relative to sync pulses on a line 15 so as to place the image provided by each store in the correct location on the screen. The full screen image is synthesized from the contributions from the MF stores which can be assigned arbitrarily to different viewports and different bit planes for the pixel bus 18. Whether or not a store writes onto the pixel bus can be determined by a priority contest, using a priority number passed from store to store on a priority bus 19. <IMAGE>

Description

SPECIFICATION Window graphics system The present invention relates broadly to window graphics systems, that is to say systems enabling independ entlygenerated image data pertaining to a plurality of windows in "world space" to be displayed in a plurality of viewports, which are rectangular areas of a display. It is well known to provide images on a rasterscan display screen from a frame store, also referred to as a frame buffer, which stores one or more bits per pixel.

Windows may be software defined by appropriate manipulation of the data written into a frame store butthis requires extensive memory operations, in particular bit-blocktransfer operations to perform scrolling and other window movement functions. This is eithertime-consuming if performed by a general-purpose processor, or expensive if performed by a high-performance bit-blocktransfer processor.

Various techniques are known to assist in updating image data, dealing with hidden surface removal in representing objects which partially obscure each other and superimposing a small image (especially a cursor) in a variable position. These include use of multiple planeframe stores, use of video mixing under different logical functions to overlay opaque and transparent images and provision of registers to indicatethe coordinate position of an image plane relative to the screen coordinate system. This latter feature provides a transformation between "world space" and "screen space" defined by the coordinate systems of a frame store and the screen respectively. In particular a window in world space may be transformed to a viewport in screen space.

It is known to provide stores for areas less than full screen size, e.g. a cursorstore.

The object of the present invention is to provide a frame store assembly for a raster-scan displaywhich makes it possible to achieve very flexible, high-speed window graphics with relatively simple control means.

According to the present invention there is provided a frame store assembly for a raster-scan display comprising a plurality of like bit-plane memory devices, each capable of storing pixel image date for a part area ofthe display, meansforwriting image data independently into the memory devices, and a pixel bus routed through each memory devices, each such device comprising programmable control means operable synchronously with respectto synchronising signalsforthe raster-scan display to read out on to the pixel bus selected data from the memory device at times which are determined by the programming of the memory device and thus cause the read-out data to provide video data for a selected part area ofthe display, whereby the display is synthesized from the read-out data from selected memory devices.

It will be convenient to adopt the following terminology. Each said memory device is a micro-frame store, abbreviated herein as MF store. Each MF store stores one "pane" in world space. The control means of a piu rality of M F stores may be programmed in such away that the panes fit together to form window. In screen space a viewport is formed from one or more "tiles". A pane contains image data for one tile only; a tile can displayall, part or noneofthe data in a pane. ApluralityofMFstores may be assigned to the same pane to provide a plurality of bits per pixel.

Since the contribution of an MFstore to the display depends upon the way in which its control means is programmed it becomes possible to define whatever windows are required and to assign as many MFstores to a pane as are required to provide the desired number of bits per pixel (upto a given maximum). Onlythose MF stores which are needed for a given application need be used. As will be explained below, it becomes very simpleto deal with the problem of overlapping windows.

The embodiment ofthe invention to be described below has thefollowing features and advantages: The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a diagram ofawindowandaviewport, Figure2 is a diagram showing the relationship between one pane of a window and one tile of a viewport, Figure 3 is a block diagram of one embodiment of the invention, Figurelis a more detailed blockdiagram of one MFstore, FigureS is a schematic block diagram of an embodiment of a MF store memory array, Figure 6 is a block diagram of a scanline section of a video output unit, Figure 7 is a block diagram of a pixel-rate section of the video output unit, Figure 8is a block diagram ofafirstsignal generating circuit of the scanline section of Figure 6, Figure 9 is a block diagram of a second signal generating circuit, Figure lOis a block diagram of an alternative second signal generating circuit, Figure 7 7 shows a priority resolution unit of Figure 7 in more detail, Figure 12 shows a normal/inverse video circuit of Figure 7.

Figure 18shows part of Figure 5 in more detail, Figure 14 shows an output function control circuit of Figure 7 in more detail, Figure 75is a block diagram of pixel combination logic included in Figure 7, and Figure 16shows part of Figure 15 in more detail.

Figure 1 shows a windowW composed of twelve panes P(0,0) to P(3,2), disposed within the area of a screen Sat a location defined by the coordinates x0, y0 of the top left-hand corner of the viewport. Although screen graphics are often related, so far as user software is concerned,to a bottom left origin, it is convenient in implementing the present invention to work with a top left origin, given the normal scanning pattern of a raster-scan display. The positions of the individual panes can be specified by their individual origin coor dinates xc,y0, x1,y0, x0,y1 and soon.

Aviewport V (shaded) is shown superimposed on the window W. The viewport consists of the whole ofthe pane P(2,1 ) and parts ofthe eight surrounding panes. The viewport is divided into nine tiles separated bythe parts of the partitions between tiles drawn in heavy lines. The viewport is displayed by reading out selected contents ofthe MF stores corresponding to the relevant panes P(1,0), P(2,0), P(3,0), P(1,1) etc at the correct times relative to the synchronizing signals which define the screen origin (0,0).

Figure 2 illustrates the most general case which can arise when a viewport of one tile T is set wholly inside a window of one pane P. The origin of the tile is shown asT(x,y) and the origin of the pane is shown as P(x,y), both in screen coordinates. T(x,y) is offset from P(x,y) by two quantities, the pixel offset O(x) and the scanline offset O(y). The size ofthe tile is specified by two quantities, the pixel extent E(x) and the scanline extent E(y).

In terms ofthe time bases ofthe raster-scan display, times tot4 in each line scan correspond to left and right edges ofthe pane and tilewhile scanning lines ii to 14correspond to top and bottom edges ofthe pane and tile. For simplicity the well-known considerations which arise when interlaced scanning is used are not discussed here.

The problem of extracting the required data from the MF store (or stores) holding the pane P can now be understood as follows. The counters which read outthe contents ofthe MF store have to be synchronized so asto move on during t1 tot4 in each of lines 11 to 14. The output bit stream has to be multiplexed into the output video stream only during t2to t3 in each of lines 1 2to 13. The means for achieving this will be described below.

It wiil be noted that there is redundancy in the information shown in Figure 2. The control means of a MF store can be programmed with P(x, y) and T(x,y) orwith either of these coordinate pairs pl us O(x) and O(y). If P(x,y) is not needed for its own sake it is possible to use T(x,y) direct or P(x,y) in conjunction with O(x) and O(y).

It is also necessaryto program E(x) and E(y).

The screen may have a size of the order of 1000 x 000 pixels or 2000 x 2000 pixels. Convenient sizes forthe MF stores may then be 16k bits (128 x 128 bit panes) or 64k bits 256 x 256 bit panes). To create a full screen 8 x8 = 64 MFstores may be required for one bit per pixel. To provide a plurality of bits per pixel morestoresare required, of the orderof hundreds of MFstoresfor a high pixel resolution, high colour resolution system. For example up to eight bits per pixel may be required for a system which utilizes a colour look-up table to transform 8-bit parallel video data into R, G and B colourvalues.Foreven greater colour resolution eight bits per pixel may be required for each of R, G and B, enabling the intensity of each colour two be specified independently for each pixel and to an 8-bit resolution.

The MF stores may define rectangular panes with the same aspect ratio as the screen (as implied by Figures 1 and 2), but it may be more convenientto utilize stores which define square panes, as implied bythe numerical examples given above.

Figure3 is an overall blockdiagram ofan embodimentofthe invention.A pluralityofMFstores 10 are disposed in a linear array along various buses and lines to be described below. A host graphics processor 11 communicates with the M F stores 10 by way of a store controller 12. Specifically, commands (including parameters) are sent on a command line 13. Frame and line synchronizing pulses are sent on a line 14. These reach the most remote MFstore 10Z and return to the first store 10anon a line l5forreasons which wi I I become apparent below. Image data to be written into MFstores issentout on a line bus 16. Image data can also be read outofa store backtothe host on a line or bus 17.By means ofthe command line 13 and data-in line 16 it is possible to set up each MF store to produce its own video signals for possible insertion on to a pixel bus 18. Whether insertion takes place or not is determined in part by priority contests. A priority bus 19 carries a priority numberfrom MFstoreto MFstore. The buses 18 and 19 run from the most remote store 10Z tothe first store 1 0A and video generation is synchronous with the syncsignals on the returning syncs out line 15.

Figure 4 shows the main sections of one MF store 10, namely a communication interface 20, a local control unit 21, a memory array 22 and a video output unit 23. No detailed description will be given ofthe communication interface 20, nor of the processor 11 or controller 12 of Figure 3. The present invention is not concerned with the high level processing of graphics commands, nor with the way in which commands are passed to the MF stores. This may be implemented in ways well known in themselves in computer bus systems. It is sufficient for an understanding of the present invention to realize that the computer can write values into any of the registers shown in the more detailed drawings, addressing such values to the registers individually.

Moreover use may be made of well known facilities for sending global commands and group commands which are obeyed by a particular group of devices. An example of a complete repertoire of control operations will be given below. Firstly, however, the basic elements ofthe system which enable video data to be output on to the pixel bus will be described.

The command line 13 and data lines 16 and 17 may be clocked through one bit buffers inthecommunication interfaces 20. In each such interface, decoding circuits are tapped off the command line for affecting address comparisons and command decoding. Commands may thus be pipelined down the line 13.

The memory array 22 is essentially a conventional bit-plane video RAM into which image data can be written via the local control unit. The video output unit 23 accepts selected data from selected rows ofthe memory array 22 and serializes such data for possible insertion on to the pixel bus 18. The video output unit comprises a section operating at scanline rate and a section operating at pixel rate, and will be fully described below. Firstly however, a brief description of the memory array 22 will be given for completeness.

Figure 5 is a schematicblockdiagram ofthe memory array 22 of one MFstore 10. The array is a4 by4array of RAM cells 45, each of which may have a capacity of 1 bits for 128 x 128 bit panes or a capacity of 4k bitsfor 256 x 256 bit panes. Assuming theformer alternative, each cell 45 is a 32-row by 32-column memory array requiring a 5-bit row address and a 5-bit column address. Three registers are accessible to the graphics store controller, namely a 16-bit data register 46 to which data may be sent on a DATA IN 16 and from which data may be read a DATA OUT 17, an address register47 to which a 10-bit address may be sent and a 16-bitenable register48.The commands and parameters line 13 enables the registers to be loaded as required and also enables the communications interface 20 and local control unit 21 to provide READ and WRITE signals. The read and write operationstake place asfollows. Forsimplicity the relevantconnections are shown only tothe top left-hand corner RAM cell 45.

The REM cells 45 are addressed in parallel bythe address register 47. The bits ofthe data register 46 are in one-to-one correspondence with the RAM cells 45 and, when WRITE is asserted, the bits in the data register are written via data in DIN lines into the addressed locations ofthe sixteen cells. This is subject to the cells being enabled. The bits of the enable register48 are also in one-to-one correspondence with the RAM cells45 and provide enable signals EN to the cells. The enable register 48 can be setup as a kind of maskwhich enables only a block of the cells 45. In line drawing the data in the enable register indicates those pixels which lie on the path of the line. The write cycle then writes data onlyto the enabled cells.

When READ is asserted, the contents ofthe addressed locations of the enabled RAM cells are transferred on data out DOUT lines to the corresponding bit positions in the data register46.

The features of the memory array 22 so far described relate to its communications with the MF store controller 12 and hence the graphics processor 11. Means are provided, in a manner known perse,forindependent read-out of data to the video output unit 23. These comprise four32-bitshift registers 50 into which a complete row of data from corresponding columns ofthe RAM cells 45 may be parallel-written over highways 51. The RAM cells 45 may be dynamic RAM refreshed in conventional manner, with avoidance of conflicts between refresh and data transfers over the highways 51. These transfers take place under control of a PLOAD signal, a RD ROW (read row) signal and ROW ADDRESS, which are generated in a manner described below.

RD ROW in conjunction with the ROWADDRESS read the selected row on to the highways 51 and PLOAD parallel-loads the row into the shift registers 50.

The shift registers 50 are clocked in parallel by pulses on a line 53, namely quarter pixel rate pulses PXCLK/ 4, when the registers are enabled by PX. As will be described below, PX defines the time in each scanline corresponding to the horizontal dimension ofthe pane. The bits clocked out ofthe shift registers 50 are parallel loaded into a 4-bit shift register 55 which is clocked by pixel rate pulses PXCLK on a line 56. The output from the shift register 55 is pixel rate video data PXL which is returned to the video output unit 23. This part of the memory array 22 is shown more fully in Figure 13, described below.

The memory array 22 does not have to be a square array.

Another possible arrangement is a linear array comprising only one set offour RAM cells 45. Howeverthis defines a horizontally-long, vertically narrow pane. A square or near square rectangular pane has the advan tage thatfastvertical, as well as horizontal, line-drawing will be possible. There may be redundant cells 45 and meansforallocating a spare cell in place of a defective cell, a technique well known in LSI memory devices.

PXL consists, in each frame, of 128 bursts of 128 pixel pulses each occurring at the correct times in 128 consecutive scanlinesto define the pane P, assuming the specific embodiment of Figure6and a not interlaced raster. If interlaced scanning is employed there will be 64 odd-line bursts in odd fields and 64 even-line bursts in even fields.

The bursts of pixel pulses haveto be appropriately gated to select onlythose pulses which pertain to the tile T (Figure 2). The pulses may also be selectively inverted provide normal or inverse video and provision may be made for replication of pixels independently in the horizontal and vertical directions, as determined by zoom factors. Expansion of an image by this technique is well known. In the case of 2 x 2zoom,forexample, each pixel is duplicated in each line to expand each burst of 128 pulses into a burst of 256 pulses and each burst is moreover repeated on two consecutive scanlines.

The video output unit 23 which provides these and other facilities will now be described. It consists of a scanline section (Figure 6) and a pixel-rate section (Figure7). The scanline section comprises a set of registers 60 into which the following values can be written (via the local control unit21): PANE(Y) Thescanlinenumber1, (Figure2) OFFSET(Y) 0(y) in Figure2 EXTENT (Y) E(y) in Figure 2 ZOOM (Y) The vertical zoom factor Avertical pane control unit 61 is responsive to the values in these registers and to the horizontal and vertical synchronizing pulses HSYNC and VSYNC to provide the following signals:: ROWADDRESST The address in the memoryarray22 ofthe curent row within the tile T (Figure 2) RD A read signal accompanying ROW ADDRESS T PLOAD Asignal commanding loading of a row from the memory array 22 into the pixel-rate section TY Asignal which remains true during the lines 12to (13-1 ) which are involved in thetitleT ENABLE REFRESH A strobe which enables a conventional refresh control circuit 62 The refresh circuit 62 provides the following signals: ROW ADDRESS R The current row refresh address REF RID A read signal accompanying ROW ADDRESS R RSEL A selection signal.

The selection signal R SEL controls two multiplexers 63 and 64 which, when a refresh operation mistaking place, route ROW ADDRESS Tto ROW ADDRESS and route RF RD to RD ROW, these output signals being input to the memory-array 22 as already described with reference to Figure 5. When no refresh operation mistaking place, the multiplexers 63 and 64 route ROW ADDRESS Tto ROW ADDRESS and route RD to RD ROW.

The pixel-rate section is shown in Figure 7. A circuit 70 MICRO-FRAME STORE DATA OUTPUT represents the registers 50 and 55 of Figure 5, described morefullywith reference to Figure 13 below. The pixel rate section includesvarious registers 71 to 75 which are loaded with thefollowing quantities via the local control unit 21: PANE (X) The number corresponding to ta (Figure 2) OFFSET (X) 0(x) in Figure 2 EXTENT (X) E(x) in Figure 2 ZOOM (X) The horizontal zoom factor OUTPUT FUNCTION Selects various modes of handling PXL BUS ALLOCATION Determines which pixel lines in the pixel bus 18 are affected by PXL PRIORITY Determines the priority of the MF store relative to the other MF stores.

The registers 71, i.e. the firstthree registers listed above control a horizontal pane control circuit76which also receives TYand outputs PX and TX where PX extends from t1 tot4 (Figure 2) and TX extends fromt2tot3, so asto markoffthe pane and tile respectively within a scanning line.

PX enables data to be clocked outfrom the circuit 70 as PXL in responseto a clock PXCLKZOOM. Azoom control circuit 77 is a controlled divider which divides PXCLK, the pixel rate clock, by the zoom factorto produce PXCLKZOOM. The zoom factor will commonly be unity, but when horizontal enlargement by a factor of 2,3..., the zoom factor is set accordingly, so that PXCLK ZOOM is half the rate, a third the rate, and soon, of PXCLK. Thus, reverting to Figure 5, the signals on lines 53 and 56 are only PXCLKI4 and PXCLKwhen the horizontal zoom factor is unity. In the more general case the inputs are: (PXCLKZOOM)/4 = PXCLK/4m(1ine 53) and PXCLKZOOM = PXCLK/m (line 56) where m is the horizontal zoom factor.

PXL is passed through a circu it 78 which selectively inverts PXLto provide PXLO and can also clamp PXLO high or low. The function performed by the circuit 78 is determined by an output function control circuit 79 in accordance with the contents of the OUTPUT FUNCTION register 73. PXLO is fed to pixel combination logic 80 for insertion on to the pixel bus 18 subjectto three sets of conditions: (1) PXLO affects only those pixel lines selected by the BUS ALLOCATION register 74.

(2) The mode of insertion can be overwrite, logical AND, logical OR, exclusive OR or their inverses. The mode is also selected by the outputfunction register 73 and control unit 79.

(3) Insertion onlytakes place during a signal ENABLE INSERTION provided by a priority resolution unit 81 which compares the number on the priority bus 19 with the priority number in the register 75 during the interval marked by TX.

The vertical pane control 61 of Figure 6 will now be described more fully with reference to Figures 8to 10.

Two registers 85 and 86 are loaded from the local control unit 21 with the following two parameters respectively: T(Y)ADDRESS The address in the memory array 22 ofthefirst row within thetileT ZOOM(Y) The vertical zoom factor.

The T(Y)ADDRESS is loaded into a counter 87 at the beginning of each frame byVSYNC. During TYthe counter 87 counts HSYNC, or a sub-multiple of HSYNC as determined by ZOOM (Y), and the parallel output of the counter is ROW ADDRESS T.

The ZOOM(Y) register 86 controls a programmable counter 88 so as to select the division factorthereofin accordance with the vertical zoom factor n, which may be 1,2,3 etc. It follows that the same row address is used n times.

HSYNC is also applied to a chain of monostable circuits 89,90,91 which respectively provide RD, PLOAD and ENABLE REFRESH in rapid succession. However RD and PLOAD are gated with TY in AND gates 92 and 93 so as to be output only during the vertical extent ofthe tile T.

Figure 9 shows one embodimentofthe part ofthevertical pane control 61 which generatesTY, namelyfor the case in which P(y) is used in conjunction with O(y) to determineT(y) (Figure 2). The circuit comprises registers 95,96 and 97 into which are written, via the local control unit 21, the following values respectively: P(Y) O(Y) E(Y) These quantities are loaded into corresponding counters 98,99 and 100 at the beginning of each frame by VSYNCwhich also clears a PY latch 101, clears an OY latch 102 and sets a TYenable latch 103. The countersare all clocked by HSYNC but are selectively enabled. Considerthe counter 98 to be enabled.It counts scanning lines (HSYNC) and the value of P(Y) is such that the counter reaches its terminal count at line 17 (Figure 2), whereupon the latch 101 is set to provide PY. The enabling signal forthe counter 98 is provided via an AND gate 104 by visible range check circuit 105 which performs simple range checking on P(Y) to determine whether the pane P (Figure 2) is at least partially within the visible screen area, so far as vertical coordinates are concerned. If not, the counter98 is never enabled and TY is never emitted. When the counter 98 reaches its terminalcountand sets the latch 101, it also disables itselfvia an inverter 106 andtheAND gate 104.

PY provided by the latch 101 enables the O(Y) counter 99 via an AND gate 107. This counter reaches its terminal count at line 12 (Figure 2) and thereupon sets the latch 102 and disables itself via an inverter 108 and the AND gate 107. The signal OY provided bythe latch 102 then provides TY byway of an AND gate 1 09which is enabled by the set latch 103. OY also enables the counter 100 via an AND gate 110. When this counter reaches its terminal count it disables itselfvia an inverter 111 and the AND gate 110 and also clears the latch 103. The AND gate 109 is therefore disabled and TY isterminated.

it will be appreciated that the quantities P(Y) and O(Y) loaded into the registers 95 and 96 must be complementary to the quantities P(y) and O(y) of Figure 2 ifthe counters counts upwardly.

As already noted, use may be made of T(y) rather than P(y) and O(y). The alternative circuit of Figure loins then employed. T(Y) and E(Y) are entered in registers 115 and 116 and loaded into corresponding counters 117 and 118 byVSYNC. Latches 119 and 120 are cleared and set respectively byVSYNC. So long as itis enabled by a visible range check circuit 121,the counter 117 counts HSYNC until it reaches terminal count when itdisables itself via inverter 122 and AND gate 123 and sets the latch 119. TYisthen provided by an AND gate 124 enabled by the set latch 120.

The latch 119 enables the counter 118. When this counter reaches its terminal count it disables itself via an inverter 125 and an AND gate 126 and clears the latch 120 to disable the AND gate 124 and terminateTY.

The horizontal pane control circuit 76 of Figure 7 will not be described in detail since it is essentially the same as the circuit of Figure 9 but with P(Y), O(Y) and E(Y) replaced by P(X), O(X) and E(X), and VSYNC and HSYNC replaced by HSYNC and PXCLK respectively. Moreoverthe AND gate 104 has to have a third input, namelyTY.

PX and TX are taken from the latch 101 and the gate 109 respectively.

It is assumed, by way of example, that the priority bus 19 is eight bits wide. This bus inputs a bus priority nu mber A to the priority resolution unit 81 which receives the MF store priority number B from the register 75.

So long as TX is false, the MF store priority number B is ignored, ENABLE INSERTION is force false and the input bus priority number A is passed on to the next priority resolution unit as the output bus priority number Z. If TX is true, a priority contest takes place, ENABLE INSERTION is true if the MF store priority number B has higher priority than the bus priority numberA, otherwise ENABLE INSERTION is false, and Z is outputas whichever of A and B has the higher priority. Higher priority may correspond to a larger number (maximum priority resolution) orto a smaller number (minimum priority resolution).

An example ofthe priority resolution unit81 is shown in Figure 11.The bits ofthe numbers A, B, and Zwill be denoted as follows: A = a1 ... a ...

B = b1 ... bj ... b8 Z = Z1 ... Zj ... Z8 where the subscripts 1 and 8denote the most and least significant bits respectively andjdenotes a general bit.

The priority resolution unit80 comprises eight bit logic unitsT1 toT8. Considering the general unity1, it receives the bits aj and bj and outputs zj. The unity also receives inputs 1 anddj from the next more significant units 1 and outputs ci and do tithe next less significant unit. The signal cj indicateswhether ornot priority has been resolved at the unity or at a unit of higher significance and dj indicates,when priority has been resolved, in whose favour. The final bit d8 constitutes the ENABLE INSERTION signal. zj becomes a for the priority resolution unit ofthe next MF store.

One set of equations defining the structure forT1 in the case of minimum priority resolution is asfollows: cj=cj.l + (ajObj) (1) dj = cj.t.dj.i + aj.cj-1 (2) z; = aj.bj + Cj.i (bj.dj 1 + a1. dj-1) (3) The convention assumed is that 0.1 = 0 means "not resolved" while c. = 1 means "resolved". If q 1 = Othe valueofdj is without significance. If cj-1 = 1,thendj = 1 meansthe device has won the priority contest whereas dj 1 = 0 means the bus has won the priority contest.

The provision ofthe initial values c0 and d0 will now be considered. c0 is the signal TX whiled0 is tied to logical 0. This causes ENABLE INSERTION to be forced false by TX false, whereas during TX true, ENABLE INSERTION is true only if the MF store priority number B has higher priority than the bus priority numberA, (savethatthe state of ENABLE INSERTION is delayed eight bits relativeto the state ofTX).

A fuller explanation ofthe priority resolution unit, and an example which resolves in favour of the maximum priority number, will be found in our copending application 8518130, entitled "Priority Resolution System".

The priority resolution unit as described with reference to Figure 11 is a pipelined unit operating with the most significant bus priority bit a1 eight bits early relative to the pixel at which the priority resolution obtains. A non-pipelined unit could equally well be used, in which the cand d signals would ripple through the bit logic units T1 toT8.

Figure 12 shows the circuit 78 of Figure 7. A multiplexer 130 is controlled by two bits from the outputfunction control circuit 79 to select as PXLO either PXL, PXL inverted by an inverter 131, HIGH or LOW.

Figure 13 shows the microframe store data output circuit 70 in more detail. The shift registers 50 and 55 have parallel-load terminals PL, shift enable inputs EN, shift clock inputs CLK and data outputs DO. The shift registers 50 are parallel-loaded from the highways 51 in response to PLOAD.

PXCLKZOOM from the zoom control circuit 77 is fed to a shift clock generator 54 which is essentially a two-bit (divide-by-four) counter producing an outputCLK (atthe same rate as PXCLK ZOOM) on the line 56 and a quarter-rate output CLK/4 on the line 53. The counter is reset by PLOAD to establish the phase of CLK/4 correctly.

PX enables the registers 50 to clock outtheircontents in responseto CLK/4which parallel-loads each group of four bits from DO of the registers 50 into the register 55. This register is permanently enabled and clocked by CLKto feed out PXL.

Figure 14 is a diagram ofthe outputfunction control circuit 79. This consists of a decoder 134, e.g. a PROM, which is addressed by the contents ofthe outputfunction register 73 and ENABLE INSERTION from the priority resolution circuit 81. The decoder provides two output bits controlling the multiplexer 130 (Figure 12) in the normal/inverse circuit 78. The decoder 134furthermore provides three bits FUNCTION CONTROL controlling the pixel combination logic 80 which is shown in Figure 15.

Figure 15 is drawn forthe case of an 8-bit wide pixel bus 18. The bus comprises PIXEL BUS IN (0) to (7) onthe input side and PIXEL BUS OUT (0) to (7) on the output side. For each bit, a function block 136 receives PIXEL BUS IN (n) and PXLO and provides PIXEL BUS OUT(n) in a manner determined in partbythefunction control signal from the output function control circuit 79 and in part by a corresponding bit ofthe bus allocation register 74. If this bit is zero, the function block 136 simply passes PIXEL BUS IN (n) to PIXEL BUS OUT (n) but, if the bit is one, PXLO can influence PIXEL BUS OUT(n) in a manner determined bythefunction control signal.

Figure 16 shows one embodiment of the function block 136.

A multiplexer 137 provides PIXEL BUS OUT(n) and is controlled by the allocation bit (n) from the register74.

When this bit is zero, the multiplexer selects PIXEL BUS IN (n) but, when the bit is one, it selects the output of an 8-to-1 multiplexer 138 which is controlled by the 3-bit function control signal applied to all function blocks 136 in parallel from the output function control circuit 79.The eight inputs to the multiplexer 138 are as follows: (1) PIXEL BUS IN (n) (2) PXLO (3)TheAND of PXLO and PIXEL BUS In (n) provided by an AND gate 139 (4) The inverse of (3) provided by an inverter 140 (5) The OR of PXLO and PIXEL BUSI N (n) provided by an OR gate 141 (6) The inverse of (5) provided by an inverter 142 (7) The exclusive OR of PXLO and PIXEL BUS IN (n) provided by an exclusive OR gate 143 (8) The inverse of (7) provided by an inverter 144 The decoder 134 (Figure 14) always selects input (1) ofthe multiplexer 138 when ENABLE INSERTION is false, so that PIXEL BUS OUT (n) then equals PIXEL BUS IN (n).

An alternative to Figures 14 and 16 is to dispense with the decoder 134 and to enterfully-decoded control signals in the outputfunction register 73 for providing the signals to control the multiplexer 130 in Figure 12 and the multiplexer 138 in Figure 16. The ENABLE INSERTION signal then acts directly in the pixel combination logic80. For example in Figure 16, the multiplexer 137 can be controlled not by allocation bit (n) itself, but by the AND ofthis bitwith ENABLE INSERTION.

Although the asemblage of MF stores 10 may be the sole means of putting video data on to the pixel bus 18 it is also possible to supplement the MF stores with one or more full frame stores, which may be assigned a minimum priority value. Other video data may of course be put on the pixel bus for combination with MF store data.

It is a simple matter with the described system to provide a variety of scrolling and such operations. A viewport and the image displayed therein may be moved together over the screen, a process known as dragging. This is achieved by altering the P(X) and/or P(Y) coordinates of the or each pane contributing to the viewport. It is possible to move a viewport over the image data, which does not move, a process known as roaming.This is achieved by altering the O(X) and/or O(Y) coordinate value. It is possible to scroll orpan (sideways scrolling) the image data through a fixed viewport. This is achieved by altering P(X) and/or P(Y) with complementary changes of O(X) and O(Y). Anyone ofthese changes may be set upas a motionvector whereby the relevant coordinate or coordinates is changed by a fixed amount perframe.

In order to facilitate the treatment ofviewports composed of morethan one tile, it is desirableto be able to associate microframe stores pertaining to the same window, in such awaythatgroup addressing may be employed for these stores.

When scrolling an image through a viewport,whether byvertical scrolling orsideways scrolling, continuous scrolling may be achieved by providing one more MF store than is needed to caterforthe viewport, in each column of tiles or each row of tiles. As an MF store moves completely out of the viewport, it is relocated so asto start moving into the viewportfrom the opposite side and is updated with the appropriate image data.

The position of the screen in image space may be shifted by broadcasting an x and/or y offset to the pane coordinates of each MFstore.

Various facilities may be provided to facilitate the processing of image data, such as copying data concurrentlyinto a plurality of MFstores and copying the data from one such store to a plurality ofotherstores.

An example of repertoire of commands follows: Micro-Frame Store Global Control: Set position of micro-frame store Associate micro-frame stores into arbitarywindows Set a motion vector Set position of the screen in image space Write protect micro-frame store image memory Set priority of a micro-frame store Allocate a micro-frame storeto colourchannels.

Micro-frame Store Serial Communications: Copy data from offwaferto 'n' micro-frame stores Copy data from a micro-frame store to off wafer Copy data from a m icro-fra me sto re to 'n' micro-framestores where'n' is any numberfrom 1 to the maximum colourdepth.

Micro-Frame Store Local I/O: Block Access Read all bits in access-array into data register Write all bits in access array from data register Set/Clear/Invert all selected* locations in the access array RowAccess (if more than one row in the access array) Read any row into data register Write any row from data register Set/Clear/lnvert all selected* locations in any row *selection is achieved by 'setting' the corresponding bit in a mask register Micro-Frame Store Video Output Stage: Enable/Disable Output Inverse/Normal Video Transparent/Opaque/Logical Overlays Force Output High/Low 2DZoom Select a rectangular subsection of a micro-frame storeforoutput

Claims (16)

1. A frame store assembly for a raster-scan display comprising a plurality of like bit-plane memory devices, each capable of storing pixel image data for a part area ofthe display, means for writing image data independently into the memory devices, and a pixel bus routed through each memory devices, each such device comprising programmable control means operable synch ronously with respect to synchronising signals for the raster-scan display to read out on to the pixel bus selected data from the memory device attimes which are determined by the programming ofthe memory device and thus cause the read-out data to provide video data for a selected part area of the display, whereby the display is synthesized from the read-out data from selected memory devices.
2. Aframestore assembly according to claim 1,wherein the programmable control means ofeach memory device comprise means forstoring origin coordinates forthe stored part area ofthe display, relative to a screen origin.
3. Aframe store assembly according to claim 1 or 2, wherein the programmable control means of each memory device comprises means for storing coordinate values defining a sub-area of the stored part area and the programmable control means read out on to the pixel bus only the data pertaining to the said sub-area.
4. Aframe store assembly according to claim 3, wherein the programmable control means of each memory device store origin coordinates for the sub-area relative to the origin ofthe part area, and extent coordinates for the sub-area relative to the origin ofthe sub-area.
5. Aframestore assembly according to any of claims 1 to 4, wherein the programmable control means of each memory device include means for assigning the output ofthe device to different combinations of one or more lines ofthe pixel bus.
6. Aframe store assembly according to any of claims 1 to 5, comprising a host processor and command and data bus means routed therefrom through the memory devices for writing image data in the memory devices and sending commands to their programmable control means.
7. Aframe store assembly according to claim 6, wherein the pixel bus is routed through the memory devices in the reverse direction to the command and data bus means.
8. Aframestore assembly according to claim 4and claim 6 or7,wherein the host processor is arranged to effect progressive changes in the horizontal and/or vertical coordinate direction of the part area origin coordinates and/orthe sub-area origin coordinates to effect dragging, roaming, scrolling or panning of a viewport.
9. Aframe store assembly according to claim 8, wherein the hose processor is arranged to associate a plurality of memory devices to define vertically or horizontally contiguous tiles of a viewport and to scroll or pan the image data therethrough by effecting like progressive changes in the vertical or horizontal part area origin coordinate and sub-area origin coordinate of all associated devices.
10. Aframe store assembly according to claim 9, wherein the host processor associates at least one more memory device than the number required to coverthe extent of the viewport and jumps the coordinates of a memory device whose image data has just moved out ofthe viewport so as to assign that memory device to the part of world space whose image data will move into the viewport on continued scrolling or panning.
11. Aframe store assembly according to any of claims 1 to 10, wherein the pixel bus is accompanied through the memory devices by a line carrying the synchronizing signals from device to device.
12. Aframe store according to claim 11, wherein the pixel bus is also accompanied through the memory devices by a priority bus routed through priority resolution units ofthe device.
13. Aframe store according to claim 12, wherein the programmable control means of each memory device include means forstoring a device priority number, each priority resolution unit is adapted to compare with the device priority numberthe incoming bus priority number on the priority bus, to pass on to the priority bus whichever number pertains to the higher priority and to control the introduction of read out data on to the pixel bus in dependence upon the sense of the priority resolution.
14. A frame store according to any of claims 1 to 13, wherein each memory device incudes a video output unit controlled by the programmable control means to select between different modes of introduction of data ontothepixel bus.
15. Aframe store according to any of claims 1 to 11,wherein each memory device comprises a rectangular memory array storing pixel image data fora part area ofthe display which is a plurality of pixels wide and a plurality of pixels high.
16. Aframe store according to any of claims 1 to 11, wherein each memory device comprises a linear memory array storing pixel image data for a part area of the display which is a plurality of pixels wide and one pixel high.
GB8521421A 1985-08-28 1985-08-28 Window graphics system Expired - Fee Related GB2180128B (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0314440A2 (en) * 1987-10-26 1989-05-03 Tektronix, Inc. Graphic display system with secondary pixel image storage
EP0337104A2 (en) * 1988-03-15 1989-10-18 Siemens Nixdorf Informationssysteme Aktiengesellschaft Circuit device for control of raster scan display information
US5047755A (en) * 1987-07-03 1991-09-10 Sharp Kabushiki Kaisha Image information display apparatus
EP0566847A2 (en) * 1992-04-22 1993-10-27 International Business Machines Corporation Multi-media window manager
GB2286071A (en) * 1994-01-31 1995-08-02 Fujitsu Ltd Cache-memory system suitable for data arrayed in multidimensional space
US5699277A (en) * 1996-01-02 1997-12-16 Intel Corporation Method and apparatus for source clipping a video image in a video delivery system
US5822760A (en) * 1994-01-31 1998-10-13 Fujitsu Limited Cache-memory system having multidimensional cache
GB2369760A (en) * 2000-09-26 2002-06-05 Samsung Electronics Co Ltd Multimedia display for a mobile terminal

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047755A (en) * 1987-07-03 1991-09-10 Sharp Kabushiki Kaisha Image information display apparatus
EP0314440A2 (en) * 1987-10-26 1989-05-03 Tektronix, Inc. Graphic display system with secondary pixel image storage
EP0314440A3 (en) * 1987-10-26 1991-03-13 Tektronix, Inc. Graphic display system with secondary pixel image storage
EP0337104A2 (en) * 1988-03-15 1989-10-18 Siemens Nixdorf Informationssysteme Aktiengesellschaft Circuit device for control of raster scan display information
EP0337104A3 (en) * 1988-03-15 1989-10-25 Nixdorf Computer Aktiengesellschaft Circuit device for control of raster scan display information
EP0566847A2 (en) * 1992-04-22 1993-10-27 International Business Machines Corporation Multi-media window manager
EP0566847A3 (en) * 1992-04-22 1994-10-05 Ibm Multi-media window manager.
GB2286071A (en) * 1994-01-31 1995-08-02 Fujitsu Ltd Cache-memory system suitable for data arrayed in multidimensional space
US5822760A (en) * 1994-01-31 1998-10-13 Fujitsu Limited Cache-memory system having multidimensional cache
GB2286071B (en) * 1994-01-31 1998-03-25 Fujitsu Ltd Cache-memory system suitable for processing data arrayed in multidimensional space
US5749089A (en) * 1994-01-31 1998-05-05 Fujitsu Limited Cache-memory system having multidimensional spread cache
US5699277A (en) * 1996-01-02 1997-12-16 Intel Corporation Method and apparatus for source clipping a video image in a video delivery system
GB2369760A (en) * 2000-09-26 2002-06-05 Samsung Electronics Co Ltd Multimedia display for a mobile terminal
GB2369760B (en) * 2000-09-26 2003-03-19 Samsung Electronics Co Ltd Screen display apparatus for a mobile terminal
US7057621B2 (en) 2000-09-26 2006-06-06 Samsung Electronics Co., Ltd. Screen display apparatus and a method for utilizing the screen display apparatus in a mobile terminal

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GB8521421D0 (en) 1985-10-02 grant

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