JPS58182871A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device such as an MOS transistor of high performance and high reliability by forming a source region with an impurity diffused layer and a drain region by the Schottky junction of metal or metal silicide and semiconductor. CONSTITUTION:A fileld oxide film 102, an oxidized film 103, a gate electrode 104, a photoresist pattern 105 are formed on an n type silicon substrate 101, boron ions are implanted to form a p<+> type diffused layer 106 as a source region. The film 103 is selectively etched and removed, an SiO2 film 108 is accumulated, etched, and an SiO2 film 108' remains at the peripheral side of the electrode 104. A Pt film 109 is deposited, heat treatment is performed, a PtSi layer 110 is formed, and a Schottky junction is formed to become a drain region between the layer 110 and the substrate 101. An SiO2 film 111 is accumulated, contacting holes 112,... are opened, and aluminum wirings 113,... are formed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for miniaturization.
This relates to improvements in the structure of semiconductor devices.

[Technical background of the invention and its problems]

In the field of semiconductor devices, the miniaturization of MO3ICs is remarkable. In particular, efforts have been made to reduce the channel length of the gate electrode with a view to improving the switching speed of Mos transistors.

However, as the channel length decreases, the following problems arise due to elemental characteristics.

First, as the channel length decreases, the threshold voltage of the transistor in the short channel region becomes shallower, which is the so-called short channel effect. in particular,
The first diagram shows the relationship between dart channel length and threshold voltage.
As shown by the characteristic line in the figure, the threshold voltage of the transistor drops rapidly in the short channel region, and the threshold voltage fluctuates widely due to slight changes in the device manufacturing process. This is explained by the fact that since the distance between the source and drain becomes shorter, the electric field therebetween becomes stronger, and as a result, the inversion voltage at the surface of the channel region is effectively lowered. Generally, the potential of the substrate forming the channel region is equal to or very close to the potential of the source region, so the source
The electric field between the drains is concentrated and strong in the channel region near the drain, and therefore the threshold voltage decreases most strongly in this region.

The other is that as the channel length decreases, the maximum voltage that can be applied between the source and drain increases, as shown in the characteristic line in Figure 2, which shows the relationship between the dart channel length and the maximum voltage that can be applied between the source and drain. It is a rapid decrease.

As shown in FIG. 3, for example, p+m source and drain regions 5 and 6 are electrically isolated from each other in an n-type semiconductor substrate 1.
When a full voltage is applied to the depletion layer 7, a depletion layer 7 is formed, and when these depletion layers 7 come into contact with each other, they are exposed and a current path is created between the source and drain regions 5 and 6. It is something. As described above, since the potential of the substrate 1 forming the channel region and the potential of the source region 5 are almost equal, the depletion layer 7 mainly occurs near the drain region 6,
It hardly occurs near the source region 5. Note that 2 in FIG. 3 is a field oxide film provided on the substrate 1 for element isolation, and 4 is a dirt oxide film provided on the substrate 1 between the source and drain regions 5 and 6 via the dirt oxide film 3. electrode, 8
9 is an interlayer insulating film, and 9 and 9 are At wirings provided on the interlayer insulating film 8 so as to be connected to the source and drain regions 5 and 6 through the contact holes.

For this reason, recently, as shown in Figure 4, the source
MOS with drain region formed around Schottky junction
) transistors have been developed. That is, 11 in the figure is, for example, an n-type semiconductor substrate. In the island region of the substrate 1 separated by the field oxide film 12, two metal layers (or metal silicide layers) 131 and 13* for forming a Schottky junction that becomes the source and drain regions are electrically connected to each other. It is set up separately. These metal layers 13I,
A dirt electrode 15 is provided on the substrate 11 between the dirt electrodes 132 with a dirt oxide film 14 interposed therebetween. The entire surface is covered with an interlayer insulating film 16, and the metal layer 131 is formed on the insulating film 16 through the contact hole.

13! At wires 17 and 17 are provided to connect with. An equivalent circuit diagram of a MOS (Runnostar) with this structure is shown in Figure 5, where the drain of transistor Q,
Diode D with Schottky junction at the source terminal,
D2 will exist. Such a MOS) transistor is a source.

Since the drain region is formed by a Schottky junction, it is possible to improve the fluctuation of the threshold voltage caused by the decrease in channel length and the limitation of the voltage applied to the drain.

However, in the MO8) Lanzostar, since diodes Dl and D2 are present on both the drain and source sides, the diode D2 on the source side is in the opposite direction to the current direction, limiting the current supply ability from the source region. There was a problem. It should be noted that since the diode D1 present on the drain side is in the forward direction with respect to the current direction, the transis-5=evening operation-hi has almost no effect.

[Purpose of the invention]

The present invention improves the decrease in threshold voltage caused by a decrease in channel length and the decrease in the voltage that can be applied between the source and drain, and prevents the decrease in current supply ability from the source region, resulting in high performance.

The aim is to provide semiconductor devices such as highly reliable MOS transistors.

[Summary of the invention]

The present invention realizes a semiconductor device such as a high performance and highly reliable MOS transistor as described above by forming a source region using an impurity diffusion layer and a drain region using a Schottky junction between a metal or metal silicide and a semiconductor. The main point is to do this.

[Embodiments of the invention]

Next, an example in which the present invention is applied to a p-channel MOB transistor will be described with reference to the manufacturing method shown in FIGS. 6(a) to 6(j).

(1) First, as shown in FIG. 6(a), the n-type silicon base 6
- A field oxide film 102 for separating the substrate 101 was formed by selectively oxidizing the plate 101.

Subsequently, thermal oxidation treatment is performed in an oxygen atmosphere at 1000° C. to form an oxide film 103 with a thickness of 250λ on the island-shaped substrate 10 region (device region) separated by the field oxide film 102.
was grown (as shown in FIG. 6(b)). Subsequently, a platinum silicide film (PTS+ film) with a thickness of 3000X was deposited on the entire surface by sputtering, and then this was deposited using photoetching technology. After turning, PtS is deposited on the oxide film 103.
] A dart electrode 104 was formed (Fig. 6(c)).
(Illustrated).

(I)) Then, selectively etching the 7otrezos) by photoetching method. After forming the turf 105, using the resist pattern 105, the dirt electrode 104, and the field oxide film 102 as a mask, a p-type impurity, such as zolon, is applied at an acceleration voltage of 30 KeV and a dose of I x 10''/c-.
Ions were implanted into the surface of the substrate 101 through the oxide film 103 under the following conditions (as shown in FIG. 6(d)). Subsequently, the photoresist turf 105 was removed and a heat treatment was performed to activate the implanted boron to form a p1 diffusion layer 106 as a source region. Subsequently, a photoresist pattern 107f is formed by photolithography so as to cover the oxide film 103 on the P1 diffusion layer 106, and the oxide film 103 on the planned drain region is formed using the photoresist no-f turn 107, dirt electrode 104, etc. as a mask. was selectively etched away to expose the part of the substrate 101 at that location (see Figure 6).
).

0ii) Next, photoresist pattern 107f
After removal, the entire surface is coated with CVD to a thickness of, for example, 3000X.
An 8IO2 film 10B was deposited (as shown in FIG. 6(f)). Subsequently, the CVD-S+02 film 10B is etched by reactive ion etching (RIE method) to form the 5IO2 film 1.
Etching was performed by a thickness of 0.08η. At this time, Fig. 6 (g)
As shown in the figure, the portion of the substrate 101 in the planned drain region is exposed again, but the Sr deposited on the side surface of the dirt electrode 104
Since the 02 film is thick in the vertical direction, the dart electrode 10
While the 5I02 film 108' remains on the peripheral side of 4,
The oxide film 103 on the source region 106 also remained without being etched.

(iJ) Next, a film 109 having a thickness of, for example, 3000X was deposited on the entire surface by sputtering (as shown in FIG. 6(h)).Subsequently, heat treatment was performed for 20 minutes in a N2 atmosphere at 650°C. , Pt in contact with the exposed silicon substrate 101 reacts with silicon to form a PtS layer 110.
was formed, and a Schottky junction was formed between the Pt5I layer 110 and the substrate 101 to serve as a drain region (as shown in FIG. 60). Thereafter, unreacted PtM is removed with aqua regia, and a CVD-3102 film (interlayer insulating film) 111 with a thickness of, for example, 8000K (7) is deposited on the entire surface.
2... is opened, and Aj wiring 113... is formed by vapor deposition and patterning of an At film to form a p-channel MO8).
A transistor was manufactured (as shown in FIG. 6(j)).

Therefore, the MOS transistor of the present invention is shown in FIG.
), the source region (
(The structure is such that a drain region is formed by a Schottky junction between the Pt5I layer 110 and the silicon substrate 101. In this way, the drain region is formed on the surface of the silicon substrate 101 with a thickness of 2.
(PtS 1 layer 110 to null V Hz of about l OX
source because it is constructed by a tokey junction.

It is possible to prevent the electric field generated by the voltage applied between the drains from concentrating on the channel region near the drains.

As a result, a decrease in inversion voltage near the drain region can be suppressed to a minimum, and a decrease in threshold voltage can be prevented.

In addition, the depletion layer extending from the drain region toward the source region exists near the surface of the channel region, and since this is within a range that can be sufficiently controlled by the voltage applied to the dart electrode 104, the depletion layer extends from the drain region toward the source region. The voltage value that can be applied to the area can be improved. Note that although the source region is formed by the p1 type diffusion layer 106, the potential of the source region is approximately equal to that of the substrate 101, and the depletion layer hardly spreads, so this does not pose a problem.

Furthermore, the source region is formed of p+tj1 diffusion N11o6, and a diode like the conventional structure shown in FIG. not exist. As a result, there is no obstacle that limits the current flowing from the source region to the channel region, making it possible to realize a MOS transistor with sufficient current supply capability.

On the other hand, as in the manufacturing method shown in the embodiment, the IJtsi layer 11
Before depositing the PT film 109 for all 0 and 110 layers, a CVD-8IO2 film 108 is deposited on the peripheral side surface of the dirt electrode 1θ4.
′ remains, the dirt electrode 104 can be connected to the gate electrode 104 without causing a short circuit between the dirt electrode 104 and the drain region.
On the other hand, Ptl l11110 for forming a Schottky junction can be made using a self-aligned line.

Note that in the above embodiment, the dart electrode was formed of Pt51, but the present invention is not limited thereto. For example, W.

It may be formed from polycrystalline silicon doped with metals such as Mo, Pd, and Pt, silicides of these metals except pt, and other impurities such as P, As, and B.

Further, the material that forms the Schottky junction between the drain region and the substrate is not limited to PtSI, but may include metals such as W, Mo, and Pd, or their silicides.

Furthermore, in the above embodiment, a MOS (MOS) using a silicon substrate is used.
Although a transistor has been described, a semiconductor film grown on an insulating substrate, such as an SO8 substrate, may be used, or other semiconductor substrates such as Ge or GaAs may also be used.

The semiconductor device of the present invention has a p-channel M as in the above embodiment.
The present invention is not limited to transistors such as O8), but can be similarly applied to n-channel MO8) transistors, CMO8, and the like.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to improve the decrease in threshold voltage caused by a decrease in channel length and the decrease in the voltage that can be applied between the source and drain, as well as the decrease in current supply ability from the source region. It is possible to provide a semiconductor device such as a MOS (MOS) transistor that can realize high performance and high integration while preventing the above problems.

[Brief explanation of drawings]

Figure 1 is a characteristic diagram showing the relationship between dart channel length and threshold voltage, Figure 2 is a characteristic diagram showing the relationship between dart channel length and maximum applicable voltage between source and drain, and Figure 3 is a characteristic diagram showing the relationship between dart channel length and maximum voltage that can be applied between the source and drain. A cross-sectional view showing a p-channel MO8) transistor, FIG. 4 is a conventional improved p-channel MO8)
5 is an equivalent circuit diagram of the transistor shown in FIG. 4, and FIGS. 6(a) to (j) show manufacturing steps for obtaining a p-channel MOS transistor according to an embodiment of the present invention. FIG. 101...n! Silicon substrate, 102... Field oxide film, 103... Oxide film, 104... Dirt electrode, 106... P1 diffusion layer, 110... Pt51 layer, 113... A/, wiring. Applicant's agent Patent attorney Takehiko Suzue 13- Figure 1 Gate Ch.

Claims (2)

[Claims] (1) Source and drain regions are provided electrically separated from each other on the surface of the semiconductor layer, and a dart electrode is provided via a dart insulating film over a region that includes at least the portion sandwiched between the source and drain regions. 1. A semiconductor device having such a structure, wherein the source region is formed by an impurity diffusion layer, and the drain region is formed by a Schottky junction between a semiconductor and a metal or metal silicide. (2) The semiconductor device according to claim 1, wherein the dart electrode is made of the metal or metal silicide used to form the Schottky junction.