JPS58182769A - State history storage device - Google Patents

Abstract

PURPOSE:To prevent an overflow of a tracer memory, by writing the writing timing to the tracer memory together with the timer value when a signal to be traced varies. CONSTITUTION:When either one of signals 201-20n to be traced has a change, the values of these signals and the count value 33 of a counter circuit 11 of that moment are written to the address of a tracer memory 12 which is shown by a memory address 28. At the same time, the output 26 of an OR gate 6 clears the count value of the circuit 11 and then starts counting time until either one of the signals 201-20n corresponding to the circuits 31-3n having an indication of validity has a change. Furthermore the input 27 of a memory address register 8 is replaced, and the reading address of the memory 12 is replaced. In such a way, the writing is carried out to the memory 12 together with the hitherto time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an internal state history storage device in an information processing device.

Conventionally, when an information processing device detects an abnormality during operation and stops operating, one way to investigate the cause of the failure is to store appropriate signals inside the device until the abnormality is detected as a state history. Tracer memory was used to determine the cause of an abnormality by extracting and analyzing the memory contents at the time an abnormality occurred. This writing of the tracer memory into the memory is generally executed at preset fixed time intervals, so there are cases where equipment operation stalls or a certain signal or state changes within a specified time. In the case of a timeout error, etc., which is detected when the timeout occurs, the tracer memory overflows due to the long time it takes from the event immediately before the timeout until the tracer stops, resulting in valid tracer data, i.e., the timeout. This has the drawback that data around the event immediately before the occurrence of the error does not remain in the tracer memory, making it impossible to perform error analysis using the tracer memory.

An object of the present invention is to prevent the tracer memory from overflowing by writing the state of the traced signal together with the change time, that is, the timer value, when the traced signal changes, instead of writing to the tracer memory at regular intervals. It is an object of the present invention to provide a state history storage device which solves the disadvantage of 74- and which makes it possible to determine the time relationship between each trace signal by reading the timer value.

The state history storage device of the present invention includes a plurality of differentiating circuits that detect a change in value corresponding to each of the traced signals whose state history inside the information processing device is to be stored, and each output of these differentiating circuits. determining means for determining whether each of these states is valid or invalid according to an instruction from the device;
A counter circuit that counts and holds clocked pulses from the device, and when the output of any of the differentiating circuits in a valid state is present in the output of the determination circuit, the state of the traced signal and the output of the counter circuit are determined. Contains a storage tray 711.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

Traced signals 201 to 20n in states to be stored and outputted from the information processing device main body 1 are input to the corresponding differentiating circuits 31 to 3n and the tracer memory 12, respectively. Differential circuit enable instruction signal 211 from this device main body l
-21n are input to the corresponding differentiating circuit effective flip-flops 41-4n, and the signals 231-23n are the outputs of the differentiating circuits 31-3n, and the signals 241-24 are the outputs of the differentiating circuit-enabled flip-flops 41-4n.
n are input to the corresponding AJID gates 51 to 5n, and the outputs 251 to 2 of the D gates 51 to 5n are sent to each person.
5n is input to the JR gate 6.

The tracer enrichment enable signal 29 from the device main body 1 is AN
The clock pulse signal 31 from the device body 1 is the first input of the D gate 9 and 10, and the output 26 of the OR gate 6 is the input of the adder 7, and
This serves as the second input for the gate 9 and a reset input for the counter circuit 11. The output 27 of the adder 7 becomes the input of the address register 8, and the output 28 of the address register 8 becomes the address input of the tracer memory 12 and the other input of the adder 7. The output 3o of the AND gate 9 is input as a write pulse to the tracer memory 12, and the output 32 of the AND gate 10 is input to the counter circuit 11. Become. Further, the tracer memory 120 output 34 is supplied to the device main body 1 as read data.

Next, the present invention will be explained in detail.

First, the differentiating circuit enable instruction signals 211 to 3n corresponding to the differentiating circuits 31 to 3n enabled by an instruction from the main device 1
When 2In becomes "1", the corresponding differential circuit valid instruction 7
Lip 70 knobs 41-4n are set to "l". Then, when the tracer is enabled, signal 29 becomes I-IJ and AND gate 9.1010C1 input becomes "1". Every time the clock pulse signal 31 from the main body becomes "1", the output 31 of the AND game 10 becomes "11", the input of the counter circuit 11 becomes "l", and the count value is updated. Now, when there is a change in any one of the traced signals 201 to 20n, one of the outputs 231 to 23m of the corresponding differentiating circuits 31 to 3n becomes [J. Differential circuit output 2 becomes rlJ here
When the outputs 241 to 24n of the differential circuit valid indicating flip-flops 41 to 4n corresponding to the differential circuits 31 to 23n are "1", the outputs 251 of the corresponding AND games 1-51 to 5n
~251 becomes "1", (the output 26 of the JR gate 6 becomes rlJ), and the tracer memory write pulse 30 of the AND gate 9 becomes "IJ," and as a result, the value of the traced signal 201-2On at that time, the counter circuit The count value 33 of 11 is written to the address of the tracer memory 12 indicated by the memory address 28. At the same time, the output 26 of the OR gate 6 clears the count value of the counter circuit 11, and then the output 26 of the OR gate 6 becomes "1". '', that is, the time until any of the traced signals 20!-2On corresponding to the differentiating circuits 31-3n that are instructed to be enabled changes.Furthermore, the input of the memory address register 8 starts counting. 27 and tracer memory 1
Update the 2nd honor address. In this way, while the tracer valid signal 29 is "1", that is, until an abnormality is detected, the traced signals 201 to 2On are changed every time there is a change in any of the specified traced signals. (counter value) and is written to the tracer memory 12.

In the present invention, the traced signals 201 to 201 to be stored are
2On, the ringing instruction signal 211 specified by the device
.about.2111, it is not necessary to store all the signals to be traced, so the memory can be used efficiently.

As explained above, the present invention is configured such that the tracer memory is written to the tracer memory together with the timer value only when the specified signal changes, thereby preventing the tracer memory from overflowing and obtaining effective trace data for analysis. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1... Main unit, 31-3n... Differential circuit, 41-4n... 7 Rip-n-lop,
51-5n, 9. IO---°-AND gate, 6.
...OR gate, 7...music adder, 8...
... Address register, 11 ... Counter circuit, 12 ... Tracer memory, 201 to 20
B... Traced signal, 211 to 21r+...
... Valid/invalid instruction signal, 29... Tracer valid signal, 30... Memory write signal, 31
. . . Clock pulse, 28 . . . Memory write address signal.

Claims (1)

[Claims] A plurality of differentiating circuits detect changes in values corresponding to each of the traced signals whose state history is to be stored inside the information processing device, and the outputs of these differentiating circuits are a determining means for determining whether each state is valid or invalid; a counter circuit for counting and holding clocked pulses from the device; and when the output of the determining circuit is an output from any of the differentiating circuits in a valid state. A state history storage device comprising: a tracer memory that stores the state of the traced signal and the output of the counter circuit.