JPS58182251A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58182251A
JPS58182251A JP57065134A JP6513482A JPS58182251A JP S58182251 A JPS58182251 A JP S58182251A JP 57065134 A JP57065134 A JP 57065134A JP 6513482 A JP6513482 A JP 6513482A JP S58182251 A JPS58182251 A JP S58182251A
Authority
JP
Japan
Prior art keywords
substrate
recess
conductor
semiconductor
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57065134A
Other languages
Japanese (ja)
Inventor
Yasuro Mitsui
三井　康郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57065134A priority Critical patent/JPS58182251A/en
Publication of JPS58182251A publication Critical patent/JPS58182251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

PURPOSE:To facilitate system design by forming a recess for accommodating semiconductor chips on a metal base material, covering such recess with a dielectric substrate having a bonding area for chips at the lower surface, connecting electrically chips and areas and by connecting it to the transmission line provided at the surface of inductor substrate and forming circuit elements on the surface of substrate. CONSTITUTION:A conductor film 3 for earthing is deposited at the surface of external edge of metal base material 1 having the rear cover 11 and a recess 12 located thereon at the bottom surface and an inductor substrate 2 being provided with a semiconductor chip 5 opposing to the recess 12 is placed while bridging over said film. Electrode terminals provided on a chip 5 are respectively connected to the conductor 41 provided through the substrate 2 with a wire 6 and the edge of conductor 41 exposed to the surface of substrate 2 is connected to a micro strip line 2 provided on the substrate 2. Thereafter, circuit elements such as chip capacitor or semiconductor elements 7 are settled at the location on the line 4. Thereby, productivity of hybric IC's can be enhanced.

Description

【発明の詳細な説明】 乙の発明はマイクロ技半導体装置に関するものである。[Detailed description of the invention] B's invention relates to a micro-technology semiconductor device.

畦しく言えば、マイクロ妓帯のハイプリツＦＩＣ（９）
路の構成方性および構造を提供するものである。To put it bluntly, Hipuritz FIC (9) is a micro-girl belt.
It provides the orientation and structure of the road.

ここでは、マイクロ波牛嚇体本子としてＦ：１ツトキパ
リア静亀昇効単トランジスタ（以−ト、ＳＢＦ凰Ｔ　と
呼ぶ）を使用したハイブリッドＩＣ−細を参〇にとって
説明する。Here, a description will be given of a hybrid IC using an F:1 differential static booster transistor (hereinafter referred to as SBF-T) as the main body of the microwave control device.

一１図番よ、従来のハイブリッドＩＣ圓緬榊戚の一例を
示す斜視図で、５ＩＦＫＴを用いｔコー教増幅器の場合
である。Figure 11 is a perspective view showing an example of a conventional hybrid IC, which is a 5IFKT amplifier.

金属基体（１）上に１婁された晒亀俸ｉ板（幻上に形紙
されるマイクロストリップ−紬（４）で−鮎パターンを
横紙し、　５ＢＦＥＴである半導体チップ（旬を金属ｉ
体（１〕上に１ｉｉｉｌ看し、　５ｉｔｙ訂のに−は細
路パターンとポンディングワイヤ（旬により振−サれて
いる。On a metal substrate (1), a microstrip shaped like a microstrip - pongee (4) - is laid out horizontally, and a semiconductor chip (5BFET) is placed on a metal substrate (1).
The body (1) is shown in 1iiiil, and the 5th edition has a narrow path pattern and a pounding wire (shaded by the season).

ａＩｉＩＥ体基板（２）上には、！ＩＢＦＩＥＴのｔｍ
扼バイアス−圧印加用線路（旬、直流阻止用のチップコ
ンデンサ（７）岬が設けられて一般増一番が横紙される
。On the aIiIE body board (2),! IBFIET tm
A bias-pressure applying line (currently, a chip capacitor (7) for blocking direct current) is provided, and a general expansion line is installed horizontally.

このようにｌｌＩ＆されるハイブリッドＩＣでは。In a hybrid IC that is treated like this.

半導体チップが款−に寓出しているため、ハイブリッド
ｚｃ’に＠ｔＰする揚台には、半４体チップか汚染ある
いは破壊される参故かしばしは圧し、！麺性および作り
性か良くなかった。また、仁のよりな横紙のハイブリッ
ドＩＣを便用する揚台は。Because the semiconductor chip is exposed to the law, it is often the case that half-quadruple chips are contaminated or destroyed on the platform for hybrid ZC' @tP. The quality of the noodles and how they were made was not good. In addition, there is a lift platform that conveniently uses the hybrid IC of Jin's Yorina Yokogami.

気負封止されるケースか１皺となり、システム設訂にお
（ブる自山良か１１１限され、いわゆる使い易さの点に
おいても間−かめった。There was a problem with the case being sealed, and the system design was limited to 111, and so-called ease of use was also taken into consideration.

この発−は上記の点に−みてなされたものであり、駒亀
体基板の＆向に半導体チップを装着し。This development was made in view of the above points, and a semiconductor chip was mounted on the & direction of the bridge body board.

ｈ一体基板の＆−のマイクロストリップ線略と半導体チ
ップの電極リードとは、１６４体基板を負通する導電体
部によって電気的に接続する挙にＪす。The &- microstrip lines of the integrated substrate and the electrode leads of the semiconductor chip are electrically connected by a conductor portion that conducts negative through the 164-unit substrate.

半導体チップが辰血に露出しないハイブリッド菖Ｃの一
成万注および榊造を提供するものである。The present invention provides Isseimanchu and Sakakizo hybrid irises C in which the semiconductor chip is not exposed to blood.

以下１図面の実施例について１１１ＩＩ明する・１１に
２＃Ａはこの発明の一笑施帆であるハイブリッドＩＣを
ボす＃４視図、＃８８図は動２因のハイブリッドＩＣの
裏面の量をはずした状紬をかす裏向図。The embodiment of drawing 1 will be explained below. In 11, 2#A is a perspective view of #4 showing a hybrid IC which is a mock-up of this invention, and #88 is a perspective view showing the amount of the back side of a hybrid IC due to two reasons. A reverse view of the removed pongee.

第４図は１１８図１−１−における断面囚で表置（ロ）
が験雀された状態をボす。Figure 4 is a cross-sectional view of Figure 1-1-118 (b)
The state in which it has been tested is broken.

この実施例では、金属１体に四部−を設け、四部−円で
露出しているｉ亀体基板情）の裏向に半導体デツプの亀
−ホンデイングエリアー、−を杉成し、接地電−のホン
ティンダニリアーは一電体基＆−ノの帳地纒体＠（３）
と接続され、その他の電極ホンディングエリア−は導電
体基板を真逸する金属如の導電体Ｓ−を介して、酩電俸
轟板−ノ上面のマイクロストリップ―略にに！されてい
る。In this embodiment, four parts are provided in one metal body, and a turtle board area of a semiconductor depth is formed on the reverse side of the fourth part exposed by a circle, and a grounding area is formed. The Hontin Daniliar is a monoelectric base &-no paper fabric @ (3)
The other electrode bonding area is connected to the microstrip on the top surface of the electric wire plate through a metal-like conductor S which is connected to the conductor substrate. has been done.

以上のようにｍｈされたハイブリッドＩＣでは。In the hybrid IC that has been mhed as described above.

半畳体チップを装着する部分は回路パターンを形成する
誘電体基板（２）上ｌとは魅気的に接続されているだけ
で完全に分−される躯となり、半導体チップ（旬が従来
構造のように表向に露出しない。このｔこめ、−路パタ
ーンにチップコンデンサ（７）を半出付けする場合、あ
るいは回路パターンの修正時に生じる半導体チップの汚
栄やｋＩＬｍの部数か生じなく、取扱いが容易となり、
ハイブリッド１ｃの庄ｊｉｌｉ！Ｅと［ｉ性の向上が可
能となる。また、このような卿造のハイブリッド１ｃで
は、第６１７に示すようにｍ電体基板す）の表−には電
極−＋−のパターンのみｌｅ成し、半導体チップを装荷
した状態にしておき、所定のハイブリッド１ｃの性能を
実ノ 洟する紬略−子あるいは半導体系子を彼から形成する躯
か可能となる。The part on which the semiconducting chip is mounted is connected to the dielectric substrate (2) on which the circuit pattern is formed, and becomes a completely separate body. When half-attaching the chip capacitor (7) to the - path pattern, or when modifying the circuit pattern, the semiconductor chip will not be contaminated or the number of copies will be reduced, and handling will be difficult. becomes easier,
Hybrid 1c Shojili! It becomes possible to improve E and [i properties. In addition, in such a manufactured hybrid 1c, as shown in No. 617, only the pattern of electrodes -+- is formed on the surface of the electric board (m), and a semiconductor chip is loaded. It becomes possible to form a fabric or a semiconductor device based on the material that simulates the performance of a predetermined hybrid 1c.

すなわち、ＪＲ氷されるハイブリッドＩＣの仕様。In other words, the specifications of the hybrid IC used by JR.

用途に対応して−々の回路パターンを形成出来るｔコめ
、める揚台は増幅ｍ回路、める揚台は軸振器囲路等と石
す図にボす状鯨から柔軟に一緒輛紙が出来る利点かめる
。Various circuit patterns can be formed according to the application, such as the amplifying m-circuit for the merging platform, and the oscillator enclosure for the merging platform, from a boss-shaped whale to a stone diagram. Understand the advantages of making paper.

以上述べたまうに、この発明によれは、庄匪性と信頼性
の艮好なハイブリッドＩＣを１船ｆる◆か出来る事、シ
ステム設計が細石となる等、冥用上大きなｌＦＵ点を１
する。As stated above, this invention has the advantage of being able to produce a hybrid IC with excellent performance and reliability in one ship, and reducing the number of undesirable IFU points, such as the system design being complicated.
do.

【図面の簡単な説明】[Brief explanation of the drawing]

第１丙は、従来のハイブリッドＩＣの一鈴を示す斜視図
、ｍｇｈは、この発明の一夾ｈカをボす斜視囚、第８図
は、＃！２図の６１図、石４１は。 石ｉｔ−の１−１−における断面図、縞す凶はこの発明
のに型例を示す斜視図である。 図において、（υは金属無体、　Ｕ２）はｍ電体基板、
（３）は接地導体族、（４月ばマイクロストリップ＃Ｎ
Ａ絡。 （旬は半導体チップ、（旬はホンディングワイヤ、（１
）はチップコンデンサ、（８）は直扼ノ（イアス箪圧印
加鱒路、（ロ）は表蓋１輪は凹部、−は貢進導電体部、
鶴は電極ホンディングエリア、脅は接地電極ポンディン
グエリア、−は電極−子である。 なお１図中同一行号はそれぞれ１−一または相当部分を
示す。 代場人　烏ｋ　ｇｓ− 第１図 丁 第２図 第３図 第４図 第５図Figure 1 is a perspective view showing the bell of the conventional hybrid IC, mgh is a perspective view showing the power of this invention, and Figure 8 is #! Figure 2, figure 61, stone 41. A cross-sectional view at 1-1- of the stone and a perspective view showing an example of the present invention. In the figure, (υ is metal intangible, U2) is m electric substrate,
(3) is the ground conductor group (April microstrip #N
A connection. (Shun is semiconductor chip, (Shun is honda wire, (1
) is a chip capacitor, (8) is a direct pressure application route, (b) is a concave part of the top cover, - is a tributary conductor part,
The crane is the electrode bonding area, the threat is the ground electrode bonding area, and the symbol - is the electrode. Note that the same line numbers in each figure indicate 1-1 or a corresponding portion. Daibajin Karasu k gs- Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] （υ半導体チップと、この半導体チップとを収容する凹
部を設けた金ｍ基体と、この金ＩＮ基体に１雀さ著しる
誘電体基板とを備え、前記誘電体基板の金ＩＰ４基俸の
１！１ｉＩＩ−に面しｔこ部分に半導体チップのボンデ
ィングエリアを形紙すると共に、　ＩＩＩ記＃ｓ嵐俸基
歓の金に１４基体面と反対の面上に電極端子あるいは伝
送−路を形紙し、Ｉ９Ｔ定の１４１記ボンデイングエリ
アと前起電極端子あるいは伝送−紬とを前記誘電体基板
を貞遍する導電体金属部により電気的に域社し、更に別
記誘電体基板のべ面には回路素子あるいは半導体素子の
いずれかが形成した事を待倣とする半導体装置。(υ Equipped with a semiconductor chip, a gold substrate provided with a recess for accommodating the semiconductor chip, and a dielectric substrate that is similar to the gold IN substrate, the gold IP4 base of the dielectric substrate is 1!Make a bonding area for the semiconductor chip on the t part facing 1i II-, and also form an electrode terminal or transmission line on the surface opposite to the 14 substrate surface on the surface of III #s Arashiyou Kikan. Then, the bonding area specified in 141 of the I9T standard and the pre-electrode terminal or the transmission line are electrically connected by a conductive metal part that extends over the dielectric substrate, and furthermore, the bottom surface of the dielectric substrate is A semiconductor device that is imitated by the formation of either a circuit element or a semiconductor element.
JP57065134A 1982-04-16 1982-04-16 Semiconductor device Pending JPS58182251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57065134A JPS58182251A (en) 1982-04-16 1982-04-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57065134A JPS58182251A (en) 1982-04-16 1982-04-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58182251A true JPS58182251A (en) 1983-10-25

Family

ID=13278097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57065134A Pending JPS58182251A (en) 1982-04-16 1982-04-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58182251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188961A (en) * 1987-01-30 1988-08-04 Nec Corp Package for semiconductor integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495597A (en) * 1972-05-05 1974-01-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495597A (en) * 1972-05-05 1974-01-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188961A (en) * 1987-01-30 1988-08-04 Nec Corp Package for semiconductor integrated circuit

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