JPS58182190A - Dynamic type mos memory device - Google Patents

Abstract

PURPOSE:To realize a high-speed memory, by connecting a precharging circuit which precharges a couple of common data lines up to a power supply voltage to those common data lines through which signals from a selected memory cell and a dummy cell are transmitted after being amplified. CONSTITUTION:Read signals from selected data lines are supplied to a couple of common data lines I/O and -I/O through column switcher C-SW1 and C-SW2. Further, those common data lines are provided with the precharging circuit so that those lines are held at the same potential precharging level before data reading or writing operation is performed. The precharging level is equalized to a power supply voltage level to allow a main amplifier MA to operate with high sensitivity, obtaining the high-speed memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Jin's invention includes a dynamic tIj1. MOEL (Metal Insulated Semiconductor) memory device.

In the dynamo ivy type MO8 memory, the selected memory cell and the Dan cell are combined with a pair of data signals. The potential of the pair of data determined by the memory cell, the dummy cell, and K is aligned with this pair of data and output by the nine sense amplifiers. A pair of common data signals are sent to a pair of common data by using a column switch. It is multiplied by a gI signal main amplifier given to a pair of common data blocks. Is the output to the data output terminal of MO8 memory via the inappropriate output circuit r to No. 11, which is energized by the main amplifier? It will be done.

h, c in dynamic MO8 memory.

Such a series of operations is initiated by a control signal. A pair of data and common data lines are placed in a precharge state a before starting a series of operations such as this.

At the 7th t of data charge and common data #0 precharge,
M for precharging is connected to these data line and common data line.
O8FET is coupled.

7 If the recharging MO11 FIliT is driven by a timing signal such that it carries a voltage of
Precharge level: *Qualitatively, MO87m for precharge from timing signal level! Noshi! [wL] It is only possible to rise when you are busy.

However, if the precharge level of the common data IIIK is low, the bias voltage of the main amplifier will be lowered accordingly. One reason is that the bias voltage of the main amplifier A and the amplifier Mo11ET in it is lowered, and it operates only at a relatively low thst.

If the sense f of the main amplifier is low, it is necessary to set the amplified signal of the sense amplifier to a sufficiently large level before the main amplifier starts operating. As a result, the operating speed of the memory must be reduced.

For the purpose of this invention, a dynamic 1
We are committed to providing 11M0B memory*mt.

According to the invention, the precharge level or voltage V to the common data line. . level! It is made expensive.

Hereinafter, this invention will be explained in detail along with examples.

[Configuration and operation of dynamic memory system] *X1 of dynamic memory system! - 1i according to Fig. 1
iir*. First, show the dynaic memory system in a block diagram surrounded by bankrupt 'i? the law of nature,
In this system, there is a D-RAM (hereinafter referred to as D-RAM).
it (hereinafter referred to as CPU) and D-R
-Iit is connected from the interface circuit with AM.

Next, the human output between the dynamic memory system and the CPU will be explained. 1 piece, address signal 0~Ak
This is a signal to trace the address r of the D-RAM. REF
Gt'tNTHD-RAM memory information r is refreshed every time a refresh instruction is issued. The enable signal for wIC is the data start and convolution command signal in the D-RAMK. This is a memory start signal that causes M8 to start the memory operation of the D-RAM. D1～
D.

is human output data in the CPU, D-RAM, and kmp data path. R] If FRJCQ contains memory information of D-RAM 7Receipt: Lex signal.

The dynamic memory system kD-RAM and the above interface tg1wJK are separated into I51! I will clarify.

First, D-11M is column [mll, row KB@array in 几n
It is made up of a k-bit aggregation circuit (hereinafter referred to as nk, where 2" = 1024 bits). Accordingly, the D-RAM (nxm
) has a capacity of word x B bits.

Next, the interface path will be explained. The row address receiver sends ToQ to the RAR, and the address signals M0 to M1r of the address signals MEM sent from the OPU receive 18th and D-.
The address signal is converted into an address signal with a timing suitable for the operation of 11M. 0ARrI Column At 1' XL/ Sea/
(and mvAo to mvL+ of the above addresses mvAo~m
A column address receiver that receives 1~Ajk and converts it into an address signal with a timing that matches the operation of the D-RAM. Akka receiving fg L, D-
It is converted to address No. 18, which has a timing that is suitable for RAM operation.

69. with DORuf coder. D− according to the address signals Mj+z to Mk supplied from the address receiver ADH.
Select signals (hereinafter referred to as C8s to osm) for selecting a RAM chip.

-j)2 is sent to m==2.

RAR-OT, Rum8 control Ruri, D-R
h@CD@Sends the chip trace selection signal and row address capture signal i at the right timing.

In the case of MDM, the above address signals M0 to M1 and M1+1 to
This is an address multiplexer that multiplexes the data in time series and sends it to the D-RAM.

Ra Gif D - RAM +2) Me% IJ
ff4 @ f 97 v This is a refresh synchronization generation circuit that determines the timing r for refresh.

RA Or! D-RAM memory information t Refreshing address M No. Ro to Rt l
r? This is the refresher address counter.

This is a data bus driver whose data output between the DBDμOPU and D-RAM is switched by the wxgI signal.

○-OT [Above RAO, Mu DM, R Mu 8-OT.

DBD, D-RAMI'f#J- is the control 1gl path that sends out the signal.

Next, the formation of the cell address signal in the dynamic memory system will be explained.

Address signal A sent from 0PU (IA not shown)
o ~ m krr dyna (within the memory system, address signals M0 ~ mj and address signals MA,) + s ~ m are divided into 9.

One address signal is used as an address signal for the memory matrix in each chip of D-RAM.

The other address signals Mj-1 to Ak are used as chip selection signals for determining whether or not to transfer the chips of each device C in the D-RAM.

Address signals MU, 〜MUjfC, and each I of 4CD-RAM
According to the memory matrix in the C chip, the address number ~A1 is the row I of the IC chip array.
R[Ill # is applied, and M1+1 to Mj are applied to the column selection of the IC chip array.

Circuit operation in dynamic memory systems has been studied for a long time.
N1! I will clarify.

ajime KR 8'M, that is, RA Nissatsu ~ RM 8m, RA 81, and RAsb 8 are low address strobe notes.
Address strobe signal.

First, an address signal is output from apa.

Address signals M・～At and M1+1～MU are R respectively.
DMK is applied via AR, 0AR1j.

Next, when the RASb signal reaches a subdued level, RoubiRef No. 48 M0 to M1 are sent out from the MDM.

These row address signals M G to M L (l, D RAM
Added wholesale to 1 child of address. At this time, column address signals Mui+i to Muj are not sent out because MuDM is configured in advance to have too many teeth.

Next, when KRA81)91 becomes the opposite level to the above, column address signals M1+1 to Mj are sent out from MDM in response to this, and similarly applied to the KD-RAMO address electrons. At this time, row address signals M0 to M1 are sent out from MDM.
The signals are applied to the address terminals of the D-RAM in a columnar manner depending on the level of the ahabz signal from 1+1 to 1 to 1.

In addition, MU DM and R MU OK refresh signal R08
GA seal〃Dsantenina entrance meeting, Su7retsushiwork7dressIN
No. R・~R/[Mu DM sends out pregnancy is no longer possible.

The chip selection signal OaH~051z (-j to m=2) is changed to the chip selection system OaH~051z (-j to m=2) and the chip in the D-RAM is changed to Rmus- who receives Rmu 8al1.

Rum8s~RA1 whose timing was m5-a due to TK
Converted to iim@I number. Rm81~Rmf1ml!
, is used as a chip selection signal and a code for storing row addresses. R-8I signal frame, D-RAM&(1st line IC chip 01~A, β common rc supply n).To a colleague, to RAgmgI number, jlim line white engineering 0
It is supplied to Chippue 01li - Engineering 0rnsK#c.

Next, address setting operation in the chip in each column of D-RAM klli1. I will clarify.

1, row address No. 0 to 1 i) L D -R
A δ is applied to the address terminal of the entire 0 chip of the MO.

For example, one signal among the RA8+-Rm8m signals is selected according to RA8a and the chip selection signal Ml+t-Ak. The signal is brought to a certain level.

The row address signal is sent to the IO chips 0-1 of the BgM in the first row of the D-R MK by the R8 signal. -Mu1 is imported. here.

When the Rh8- signal is applied to the above IO before the row address number M--M1 is applied to the IO before the R-B14M, the row address number M--M119 is also applied @KkA, This is because there is a possibility that a signal other than the row address signal kj& may be included.

Column address signals M1+t to Mj are also applied to the address terminals of all chips of the D-RAM.

After that, Rh8. From @ issue to j! I watched Om81! When the number is set to a certain level, nk and Bi in the first row are changed accordingly.
The above column address signals Mut1 to Muj are input to the IO-chip of @i. Here, the column address signal Ai
10-~Muj is ohm The above l0K (company) is better than the signal
The added precincts are the same as Kameyama mentioned above.

In addition, the function of the CAM signal is such that which one of the row address signals M, - M1, M1, I, and column address signals M10, -J, is supplied to the IO-chip address frame, and it is determined whether it is b or t. It's about doing.

By the above operation, D-RAMIZ) nk of the first bamboo,
The address of the 4IR memory cell in the Ba1l IC chip is set.

RA8. ~RA8@
The selection cannot be heard because the level of the 4-go is set to be the opposite of the level of RA B@.

We briefly explain the data write operation and continuous output operation for the memory address set in the above manner.

Each IO-chip is pre-designed such that one day's convolution and emptying operations in each are determined by the high or low level of the write enable code WIC.

The convolution operation is performed by applying data DIS to DXB from the OPU to the above set address when the Wl value is at a predetermined level, for example, at a low level.

In the previous work, data D(
It is set by K that is output on B or B bit of II-D.

[Function of control signal]

The abbreviation is @1, meaning tk, and the inversion symbol (bar,
When the signal is 'Q' (Low Lsval) for those with bar ) placed above the abbreviation, the meaning of the seventh abbreviation is executed, and m without the bar symbol.
This means that it is executed at the time of meeting n'1' (High Level).

Command signal from OPU to 0-OT, ie 1llRqa
Send each number 11 and t. The me frame of these sent control signals is as follows.

C 8 Notes: Row address signal MU 0 to MU thru a Column address signal MU 1 + BU to MU j D-RAM
A signal is used to classify whether the data is sent to each chip in the chip, and a signal is used to capture the column address signal 11 of the chip.

This signal is used to combine the aB- to 08m signals with the R8a signal and supply them to the 0-chip array in the D-RAM.

The WE flaw signal is a signal for ORing data from memory cells in the D-RAM IC chip and determining the convolution t of data in the memory cells.

The refresher operation starts at Rca[, and the address signal M is output at MDM. ~Mu1. When the sending session of M1+, to Mj is stopped, the refresh address signal R from KRAO is
・~Ruru for sending Rtk.

``Row address signal from 8b1t1 frame DM.

9J switching timing for converting to the multi-code decoder 18 and the RAIII thread signal, that is, one of the RA 85 to RAam codes. When selected, one of the row address signals M0 to M1 is output from the MDM, and the row address fl! -1't Mu0 to Mu1 and column address signals Mu1+- to Muj switching timing tRA&,
The signal is delayed from the signal.

Next, the relationship between the W1 signal and the data path driver (DBD) will be explained.

D-RAM and DB are connected to the Wl signal sent from 0-OT.
DK joins the group. When the W1 decoding is at a high level, the cutout mode is activated, D-11MID data is output, and the D
18 is sent to OVa via BDt-. At this time, the W1 signal is inputted from DBD to D-RAMiC so that the manual data is not included. When the WIC signal level is at the write mode, input data is applied from the data input terminal KOPH of the D-RAM via the DBDk, and data is written to the set address. Konoto 1
The data output of the 1D-RAM is controlled by the Wl signal so that it is output from the DBD.

[Refresh: L operation]

In the memory cell M of the D-RAM, information is stored in a capacitor such as a capacitor in MOg in the form of an electric charge. This charge decreases over time due to the electric bell. Although there is a problem here, there is a charge leak D@button, for example, information '1' (Htgh L@vel
) If the charge level corresponding to K becomes 0 smaller than the reference level for determining information 1 and 1' and 'O' (Low LsVel) 2, it will be mistakenly determined as 10'. Therefore, it is necessary to refresh the charge V before the charge K decreases below the above-mentioned reference level while the information 11t is being stored. This refresh operation must be performed at least IIg1 within the guaranteed memory cell information storage time.

The refresh operation will be briefly explained with reference to FIG.

Refresh is sent to the refresh synchronization generating circuit R8G to the KOPU every chest period of L*request number 1zyRIQk (refresh time)/(number of refresh cycles). (In addition, the number of word lines connected to the column cheater is the number of word lines connected to the column cheater and *iib.) By receiving the above-mentioned RIQ7, the CPU''C sends out the refresh instruction signal R]17GR'MTi (. %Kltllllll
At this time, the OPU outputs the write enable signal W.
It is configured to transmit X and memory activation signal M81. RIIFGR, NTi in control cell tract 〇-〇te
Address multiplex DM by receiving 1P
and a refresh control signal R0s for applying K to a refresher address counter (hereinafter referred to as RAO).
Output k.

By receiving the MnM R0e bond, a refresh-only address signal R.about.R1'i (D-RAMK) is sent instead of the address signal M.about.Mj for random access.

Refreshing methods for D-RAMK are roughly divided into two. One method is to perform refresh 5-2 on each row of the chip array. This method has three PI points, as it consumes less power for refreshing, but it has the disadvantage of taking a long time to refresh.

Another 1H1D-RM M metalwork 0 tip array k
This is a method of refreshing to lWJ#. Although not shown in Fig. 1 is a configuration for using this method to store real bamboo, for example, the address signal from the address register I is
The MkV decoder DCRrfr is applied to the RA8 control circuit MRA8-OT to output the cutting edge signal RA8. ~RA8m'j is set to a certain level, thereby refreshing all the data in the D-RAM at once.

The advantage of this is that it requires less time to refresh, but the disadvantage is that it requires a lot of energy to be depleted.

Next Refresh operation in matrix array in IO of KD-RAM II - will be explained.

The refresh address signal R.~R) is applied from the RAM DM to the address child of the D-RAM, and the
9 at the level of No. 1, 27 of the IO matrix array
+1 row address or a sequential route. This and the right, 0
8g! The issue is at the same level as above. The information of the selected memory cell connected to address 9 is sent to 11' and 10' by a sense amplifier (not shown) K.
The level of running is amplified to be widened. This amplified signal is then carefully written into the memory cell again. That is,
A refresh is performed.

Note that σD −RA is applied to the wlc signal during refresher operation.
M and DBDK are not sent. Therefore, the human output of data from the DBD is not included.

[Function of ahtp system signals and Cm8 system signals] Figure 2 shows the block of one concentrator circuit (hereinafter referred to as IC) in D-RAM, and Figure 5 CC A more detailed version of I-0 is shown below.

From the timing pulse generation block TGB in the factory O,
RAa system signal (hereinafter referred to as RA8-1).

) and 0mB system value number (hereinafter referred to as 0m8-φ) are output.

(1) RAS-φ φ, E is added with the address bats 7mm signal 691 to which the address buffer (hereinafter referred to as DB) Kl:tl is added, and the row address signal MU0 is filled in the DBK latch field.
Level ao corresponding to ~mu1, τ7゜...lL
i, 5Lik row decoder (hereinafter referred to as R-DOR)
and a signal for determining whether to send it to a column decoder (hereinafter referred to as 0-DOR).

-X is the word-control HI number, and this is R-DCRK
A memory array (hereinafter referred to as M-ARY) is applied.

) is the signal for determining whether to send the selected signal jM-FIY to select the row address 1r.

The signal φPAa is the sense amplifier IJIjl value number, and the sense amplifier Kb is added to this signal to drive the sense amplifier.

(2 JOA8-φ φ m crr address buffer control 4 IqA No. 69, this σ m DBK is applied and latched in m DB, level '1 corresponding to column address signal Ai++ ~ m j
+I + ai+1 ,...aj* aj2
This is a signal for determining whether to send to R-DOR and 0-DOR.

ψ! The column switch 0-8W4C is applied to the column switch 0-8W4C, and is a signal that selects the column switch tis connected to the column data I and Km of Y-M RY depending on the selected one signal.

φop and φma are connected to data output buffer 7 and output amplifier @signal Too, which are respectively data output buffer (hereinafter referred to as DOB) and output amplifier (hereinafter referred to as
It is called Mmu. ) is a signal that causes the read data from M-RY to be sent to the data (Dout) jf1 child.

φRW is the data manual buffer control I signal To9, and this is the data manual buffer (hereinafter referred to as D) Kf
=0 is added, and a signal is output from the manual data (Dtn) terminal to the write data il-M-R1.

p with data output buffer IIIJI11 signal to φRw.
, DOBK is applied to this, and is a signal that prevents output to the successive data output ("out") during the convolution operation.

From the timing pulse generation 14 tate G1 in Figure 2,
Il! φ, φda as will be explained later in
Control signals such as ma are output.

(Configuration and operation of D-RAM) D-RA Mc1 configuration 11 - Explanation will be made according to Fig. 2.

The block surrounded by the broken part is one collection of D-RAM I! It is configured as 11 circuits (hereinafter referred to as xo).

In the above work O, the block TGB surrounded by two-dot chain -
Frame tying pulse generation block, D-RAMq
) Generates a signal for each circuit's operation k 111J 11.

Next, the operation 11 of each (b) path of the D-RAM will be explained according to the typing diagram of FIG.

Row address signal M~M1 is address buffer DB
When KI/R is included in 1 and latched, the numbers MU0 to MU1 are transferred to row address 1, and RA811 becomes low level. Here, RA8 (No. 11 t row address value No. ~
The reason why the row address 1 as a row address in the memory array is longer than M1 is because the row address 1 is actually the lowest in the process 0 [4 in 1].

When the signal φ1 delayed from the KRA 100th signal is applied to the DBK, the latched ft, , a address signals 4
Levels a...a...-'a1.1IL1 corresponding to # are sent to row decoder R-DOR and column decoder 0-DOR. The above level' (1111・〜a1゜aIK
Accordingly, among the output signals of the plurality of lines (21+1 lines), only the selected one is set to high level to R-DOR,
Performs an operation to set the unselected ones to low level.

Then, in accordance with this selection operation, the signal φ! rises to the /1 level. When R-DOaK is applied, select level and non-select level signals are sent from R-DOR to M-m R1 111
Served. Is this the row address in M-MURYK?
! , R-DOR, one of the 21+1 Rinko Tagata becomes high level, so that the row address of 01 in 7JM-RY is selected and set, corresponding to the seventh row.

111 and a' of the cell that is fikIIm in the low address play of one of the far-off KM-MURYKs
The information of o' is supplied to a sense amplifier (hereinafter referred to as 8m) and multiplied by 1iAK. This 8
The increase operation of the timer starts when φF is applied.

After that, column address signals M1+1 to M, 1dEAD
BK4! It's loaded and latte. Then, the C/B signal or the column address signal (M1+a to Mj) is brought to a low level with a delay. The purpose of changing the column address deviation from 0 to 19 is to embed the column address signal v1j1 in the memory array as a column address in the memory array.

9th flight φ, delayed from KOA&signal. When applied to the cam DB, the level ai corresponding to the column address note above
+1 + 'i+1 + """& J r a J
Water is sent from ADB to 0-DOR. Set C-DO
Rσ Upper R performs the same operation as the above OR. and top 1
The selection signal formed by eo-DOR is a delayed signal -! The signal is sent to the column switch (hereinafter referred to as 0-8W) in response to the voltage applied to 0-Don. In this way, one of the 2J-1 output signals of 0-DOR in the column address in M-RY becomes high level, so one 0-8W is selected, and its H is coo, 5w4 (for example). It is set depending on the column address layer that is connected, that is, when the data is selected.

In this way, one address within M-Mom R1 is set.

'OCK Read and convolution operations for the address set as above will be explained.

In the continuous output mode, the W1 signal is set to high level. The Kf & needle is set so that this WIC polarization signal ζ0m1m goes to a high level before going to a low level. K like this
If the 11 signal t is set to high level before one address of the M-R10 is set by the Om No. 811, the successive output operation orsmtt.

This makes it possible to shorten the start time r of threading.

Furthermore, when the 0m8 yarn signal 11n& is output, the output amplifier wh becomes active in response to the C signal 9, and the information at the address specified above is amplified. A signal φ is applied to this amplified data. , through the data output buffer (hereinafter referred to as 4DOB) r activated by the data output buffer (D
out) jllll+#! Served.

In this way, successive outputs are performed. When the 0m84N signal reaches a high level, the bladder ejecting operation a is completed.

Next, in the convolution mode, the 1J signal is set to low level. This low level WIm information and low level 0mS signal cause the signal ≠! Iw or 11 Ireperu.

Remarks: The data input buffer DIB (hereinafter referred to as DIB) is activated by the high level of φj1w.
Human data CD1n) Convolution data from 4 children above 1e
The address Ki determined by M-MU RIDa is output. In other words, a convolution operation is performed.

At this time, the signal φnw of the above-mentioned φR10 inverted value and the signal φ90 are changed. This allows ll
The continuous output of data from the DOB during read operations is a problem.

In the circuit of one embodiment shown in FIG.
O8F III T (M@tal oXta68*
m1con-auotor Flel(l ff1f
foot Translst, or ) 5 representative N channel GF I T (Inau14t@(
IGat@? 1elcL ff1ffect Tran
slstor) K.

1-bit memory cell (M-OWL) tlff, ffN
Storage capacitor 08 and address selection M (11νEI
It consists of TQM and is maintained by it II.

The information of %01 corresponds to the state in which the capacitors O and Kll are loaded and the state in which they are not loaded, respectively.

A large number of them are arranged in a matrix in M-01L. O for address selection of M-OWL arranged in the same row
The gates of the above-mentioned 08νITQ wings of 9M-OEL, which are connected in common to the drains u1 and data #DLε of MOgFITQM and arranged in the same column, are commonly connected to the words -WL, , etc.

The memory array pattern RYI is determined by the number of memory cells.
and M-MURY, or 411jil[are.

Although not added to %, in a dynamic fliMOB memory device with a memory capacity of isx bits, there are 128 sets of data from DL to DL+*a (not shown) and D to DL+ms (not shown). It consists of
Word flrXs WLt-6-WLI-sa and W
*X is given for 128 pieces from LI-1 to WLI-84.

There is no control, but R-D ORs t'X,
Reward M(1) 7-The vehicle is made to output a common selection signal r to the card #. For example, the four words fjjjl
R-
Intermediate 4-bit address signals ILl to lLi are applied to DOR.
A standard decoder circuit is provided which is composed of MO8PICTQmaro to Q4 that receive the signal. The output of one unit decoder circuit is supplied with a row switch R-8W, which is configured by MOBFHTQ14 to QayK, through MOBFKTQ1o to GL+sr. R8W114Cj
Through the row switch (a-sWll) l- controlled by the selection q1 made in tr3 based on the address signal &O, all of the lower two bits and the most significant one bit in r, R-DOR, Signal φ!
Or supply leaks. Based on this, one of the word numbers WLI-1 to WLI-v is selected by tying the I number φX.

In addition, regarding the other M-MURY, my colleague also did ToO5R.
By alternatively selecting 8W11 TR'8''ll, 1/128th word-selection is performed.

The above words iMWL+-t ~'WLl-14 and WL
I-.

~”Ll-114 has %Kaise 49-4564 respectively.
Latch circuit group I+AOH1, LmuOH- as described in No. 9 Publication or %Kaisho 51-14722 Publication @
Or is provided. These latch circuits wI group r are composed of units [g circuits a, each having the same configuration.
The (Z) one H, MO8FITQIm~ is configured by LI4K.

R-DOR, (R-DORI Ktsubmo colleague) hair ll
A11111M O8F Shima TQs ~ GLl are used respectively. This unit Ig1w1 operates as a ratioless type one gate 1gl sweetfish.

Then, the voltage v0° is immediately applied to the gate of the output signal of the unit path.
ITQsa ~Q meeting y 'I's gate will be informed.

MO8FITQM is used to read information from M-01L.
This is done by connecting OAK to the common column data DL by holding kOMK, and then sensing what kind of change occurs depending on the potential of data I/#DL or the amount of charge accumulated in oB. It will be done. Data gland D
The floating 8too4c of L is photoelectrically generated and the friend potential kl
-If the voltage is vo0, the information stored in C8 is 1
1' (beam V...) If it happens at the potential (V), the address time, that is, when M087ITQM is suddenly turned on, the data DLIZ) potential (Vl), lμ is so,
. It becomes υ potential. Information or 'o' for this nVc (
oV) If there are 6 r*, ("DL)" 0 #
a(○O"vOO-CB (VW-vth))/CO.

However, VthH is applied to the gate voltage of HMO8PKTQM.
MOS IF IT Q, is the threshold direct voltage.

Here, the difference between the potential of the data line DL determined by the logic 1t'l' of the memory cell and the potential of the data line DL determined by the memory cell's logic 1t'l', that is, the detected signal sound ΔvtIrX Δv,= (vDL) call #-(VDL)% #=(vI
F-vth)”alo.

It becomes 10. If vw=voo, the signal sound Δv8 is IvB
"(voo-Vth)" alo.

becomes.

In the memory matrix of a highly integrated device, the memory cells are made small and many memory cells are connected with a common data IMK, so that as<'oh, that is, the capacity ratio'g
/'or [becomes a very small basket.

Therefore, Δv8rX becomes a signal with a very small value.

In order to detect a reference signal with such a low value of 0, a dummy cell D-OWL is used as a 0ilk base. D-01LI) Capacitance of capacitor CI is 0. It is made under the same manufacturing conditions and the same design constants as M-OWL, except that the temperature is set to γ. MO8FlT Q before address on CD
Photoelectricity is applied to the electric potential by na&C (vo.K to the other one)
fixed). Therefore, 1 from address #KD-OIL
Two column data @! Signal change weight Δ given by DI4C
Similar to that of the memory cell (JV, ), vR is softened by the following equation.

However, the gate voltage of MO1IF]1TQp tube to VDW,
vth' rXM 08 F I T QDI threshold 11% pressure.

a v R=(v r:, v v th' ) °
o da / (If 30vDW=v0°, ΔvB
Gathered in a formal ceremony.

IvB"(voo"Vth')・○da/'0 As mentioned above, since it is set to about half of K Oas aOa, the value of ΔvRaΔV6 is equal to the subordinate.

Therefore, the information of % 1 # and % 0 # can be determined based on whether the potential graying applied to the data #MDL of the memory cell is smaller or larger than that of the dummy cell (IvB).

Layout of each circuit ゛Difference t in potential changes occurring at 8 and 10 addresses
% Tying signal (sense amplifier fIIJ@signal) ≠
2. It is a large sense amplifier (the operation will be described later), and a pair of complementary data l1lDL.
The person's output node is connected to I and DL. Data DL1. The number σ of memory cells coupled to D is made equal to increase the detection n1jIIL1r by making the complementary data 1mDL+ and DL- equal the floating vt'a-. D.L., ,D.I.J.

σ for each, cross one digit as shown - cell D -
OWL is combined with M.

Phase data la vs. DLI, DL, O If one KWi-combined memory cell is selected, a pair of die words # is inserted so that the die cell is always coupled to the other data.
DWLt −+ r One of DWLt-m or R-DOR
- or selected by the output of R-DORs.

The operation of the seven sense anbu is a pair of variables combined with this sense an 18 mm.
O8P I T Qsi ”Qss k*L,,, their stop*m production I@F, 1 [increase the few signals most dynamically. This positive return 1IIIlffiαMI8Fl?Q
s* or tying signal (sense amplifier control signal) φPA
It starts at the same time that conduction starts due to K. Seiso jlI
By the start of the operation, the data potential (Vi) of the data potential (Vi) determined by the memory cell or frame dummy cell in advance during addressing becomes extremely low and decreases by 7'L. The other one (VL) makes it descend quickly. This widens the difference between vH and VL. In this way, VL drops to the threshold line voltage v7h of the differential Wi seal M08FIT, and the return operation is completed. vIlrzvo in the correct W# layer operation evacuation #. 1i11D, 'lx, to a larger potential than VTh.
In the end, it reaches αttsoOv.

The information stored in the memory cell that was virtually destroyed during addressing is added to the potential of vH or VL served by the sense operation VC of the sense amplifier (
4 convolved).

1111m'l'' level, but because the data forest potential vH is V. If you add more than a certain level to o11'c, it will pop out several times and ask whether it is rewritten or written (b). While it is being returned, the malfunction that will be cleared up as an error will be lost.The active restore circuit was provided to prevent this malfunction.This has no effect on vXJyc. 114zu vH only has the function of boosting the i selective KV0° potential.03!ll and 0!11a are MI8 variable f valley elements whose static capacitance changes depending on the applied voltage. Basically, it can be explained that a capacitor can be formed at a higher voltage as α threshold voltage VThrjli*, and only a capacitor can be formed at a lower voltage.

The active restore operation is as follows. In the following, for convenience, it is assumed that data @IDL is set to high level at the time of address according to memory cell information '1' K, and data DL is set to the reference level by data construction memory. . The timing chart of the timing signals of each aircraft, which should be referred to in the following discussion, is shown in FIG.

Data Iwao DL1DL, and possible tS heavy element OB,, OB@
σ, data precharge note 5 when φi is high! Being insulted.

Hisa K, sense amplifier IIA-signal φ! When the sense amplifier 8 is put into operation state by the system, it is determined whether the data DL is precharged or MO! iPMTQvmk
A discharge field is generated through the discharge field. Since data mDLt is at a high level, MO8FITQII is turned on! be made into The method, 6J variable capacitance element OB,
The precharge of can also be discharged.

This variable capacitance element OB@u no longer operates as a substantial KSt element.

After the sense amplifier a phase increases, when the timing deviation 4 (active restore 1IIlIII value number) φq0te is set to high level, the gate potential of M apm'rQss increases by a large amount by mmc8Ev0°19 accordingly. I am made to do so. At this time, the gate potential of MIJIFITQta has 11# at the 9th level 1- since the iIT Henya heavy element OB does not substantially operate as a bootstrap capacitance. MIiiFllTQtsOke)'ML rank or electric-wLEf, depending on being paid higher than,
Data IIIDIJ, frame, this MXB71XTEQll
An electric voltage v0° is applied through the terminal. Ding nawachi day
-DL, to the potential of vo. When K is recovered, it becomes .

[Precharge circuit]

To the common data terminals 10 and 10[, column switches 0-8W- and 0-JiWll valves are supplied with a start-up data signal from the selected data layer, or a write data signal is supplied from the data manual buffer DXB. Ru. Even if such a data signal is present after the end of a read or write operation, the common data 1/'O
If the data signals % and 10K are held, when a start-up operation or writing operation is started, these common data 10 and 10K are held.
It takes a long time until the data Jgi signal is set to a level different from that of the previous data signal.

Therefore, the common date 4iii engineering 10 and X10ffCr
X, both precharge circuits are assembled. By the operation of the pair of common data buttons L and TRICHARGE, they are set to the precharge level of the lowest potential when the data start-up operation and the convolution operation are started. If such precharging is performed, when a comparison operation or a frame write operation is started, a pair of common data 1liI/c ratio soft time t will be stored. It becomes possible to give a level sr corresponding to the data signal.

This+Jl! JIIiP! The operating potential of the main amplifier 7'M, which will be explained later, is considered to be the IIE load in the common data exchange, although it is not limited to the frame and back of the frame.

In order to enable the main amplifier to operate with high sensitivity to the precharge level in the common data, 5 is set to a level that is distributed over the voltage level of the %i-path.

In order to raise the common data precharge level t to the current voltage K, the precharge circuit r * is driven by a signal that also causes the WL source voltage xv to rise. This kind of 4M is formed by a feeling of excessiveness in Pootstrap.

However, the photocharge in the bootstrap volume is reduced by one undesirable leakage device.

Due to the decrease in charge in the bootstrap capacitor IK, the signal level to be supplied to the precharge circuit is reduced. Therefore, if the precharge operation continues for a relatively long time, the precharge level in the common data shrine will be reduced.

In the circuit shown in FIG. 5, in order to prevent the precharge level from decreasing as described above,
and l10K, two precharge circuits PC1 and PO are coupled.

all precharge @1ifsPOtt! , as shown in the figure, the precharge MO8νl is controlled by the timing signal φ5. Qs+ +Q*s and balance MO87ITQI@ are composed of precharge IjaAMOPm of p1 and 2, and precharge MOa is controlled by tie-inter 4M φi with 0m8 system signal.
FITQ*i l Q*a khi balance MO8νN
TQ, Rinse is being bribed by s.

By common data 10 and 10 frames, two precharge wWlpo, and POIK, I! 3m diagram and drop 3
Following the 15KRm8 thread signal shown on BH3, Cm8
It is necessary to maintain a good precharge level not only in the normal start-up write operation mode where system signals are supplied, but also before entering the memory or other operation modes.

For example, in the refresher operation mode, the row address I
The RMB signal is happy 11FI so that I'' can change slightly *g!
JK is changed as shown. In this case, 018
No. 4, a substantially high level (11%). In this refresh j-operation mode, the frame, common data block 10
and is maintained at the precharge level of 10 frames. C B
If the I/I level transition of the signal is made relatively long, the reduction in the amount of charge in the bootstrap capacitance as described above will cause the timing signal level to decrease. Since then, the precharge circuit OF has become unable to provide a voltage level of the common data 10 and 10K1.

However, each time the precharge circuit OP, Ku, and RA8 signals are brought to a high level, a timing signal SOF which is brought to a sufficiently high level is supplied.

As a result, a good precharge level is maintained by the common data Ii1 and x7o frames and the precharge IJ path OF=.

Since the common data 1 and 10 are maintained at a good precharge level in this way, it is possible to operate the main amplifier MAIH at a relatively fast speed when the memory or read operation mode is entered later. So that I can do it.

In page operation mode, σ and row address r are fixed Iil! The 0m8 signal is changed as shown in FIG. In this page operation mode, the precharge circuit OF, frame, and OA8g1 are set to high level IIK operation state 161K''Ik.

[Tie ξnder signal generation 1al#] Ninth 0 tie of the above precharge operation (Fugu No. 91-5,
φ products are as follows: 6FI1.1 ILT diagram 1 ξ
Each is formed in the E circuit.

In the implementation 91 circuit of Figure 6, the timing signal φR1 is applied to the gate MO8PlτQtem, and the timing signal -AH is applied to the gate MO1ilF1τ.
Q14 is connected in series with the carp to which the voltage v0° is supplied and the ground potential. MO8FITQsoi to which the signal φB is applied to the gate and the 1gl path (Q
tos, all4) output signal or MOaFlTate- applied to the gate is the upper
and 1# earth potential - are connected in series.

Series connection jdo#FITQ1@s and Ql. On the other hand, the power supply voltage V is applied to the gate of the output signal outputted from the common connection point of 6. . or applied MO8FIlfTGL+oyk
Through this, it is supplied to the gate of MO81FITGLtos, and on the other hand, it is supplied to the gate of MO8PiTQ whose source is grounded. MO8FM! A timing signal φR1 is supplied to the drain of the TQls frame 7.

MO87I where one timing signal φmR can be applied to the frame gate between the source of MOBFB/TQsea and the ground potential.
TQ+・9 is provided. MO8PI connected in series [
A tie is set in the output signal output from the common aha of iTeQl@a and Qt@s as Note-5. To this tuning signal φπ, a key voltage v0° or M is applied to the drain.
The gate of O81FllTQtt. is also supplied. Also the above MO8Fl! The source of Q■・ and the MO
8FITQ1 insect is connected and b. m08! FITQ■
・The gate.

M Oa Rong 111 for source Seki Ku bootstrap
10B easy is provided.

Il! Route b of the implementation of Figure 7 (1, MO8PITQtss
~Q+*o and the bootstrap capacitance OB4 provide a circuit configuration similar to that shown in Figure 6 above. Then, as a 0m8 thread signal, φm0. φmu0 is used.

In the circuit of FIG. 7, in order to prevent a drop in the level of the timing signal φ product during the refresh operation, the MO81FITQlz and M Engineering 8F
A diode-type MO8 transistor 11 is provided between the FiTQtsr'Z' source and the output of the main input signal -5.

And MOJIFI TeQtms and Qtta4D coexistence li
! A bootstrap capacitor OBI is provided between the common point and the point to which the input signal φmH$ is applied. From this IC, when the Pout strap 811kOBmu and the timing signal φmu II are set to low level, and the timing signal φmu0 is set to high level, M08F
Precharged through MTGLtlk. Therefore, M
A bootstrap voltage is provided by setting the OflFITQ/Ha gate and drain frame, the tying signal φ, 1 to the I/I level.

This bootstrap voltage is supplied to the MOgFITQiu output. Since then, the level of the output signal φPo is prevented from dropping.

In other words, the timing setting φ is set to 0 or low in response to whether the frame 0 or 8 is set to high level in the feed mode.

At this time, the output signal φδσ, the bootstrap capacitance OB
, the 'IEII voltage v0゜engine 9 is also brought to a large level b. When the low level period of the timing signal φm0 is long, the photoelectric charge of the bootstrap capacitor OB, MO
8FICTQ,,, source leak IIA, MO8PK
It is caused by leakage current such as drain leakage current of TQ+■. Since then, the level of the output signal φi is lowered. However, in the circuit configuration g shown in FIG. 17, when the RA84 signal causes the tying signal φM II to be set to a low level, the putot strap @tOBi is removed. When the diode-connected gate and drain KH of MO8PIItTQ and the tying signal φi are set to I-E level, the voltage is raised above v0° by the bootstrap capacitance 0BsK. Therefore, the output 1 of FIG.

■In other words, the output signal φi, the -ing signal φAi
KiW1 period and -u1 to a good level.

Next, the operation t%a of the 6mth 1g circuit will be explained. In addition, @B
Note that the waveform added to the go-path is shown in the iris diagram.
However, in order to facilitate the scrapping, the same disgusting signal #LNI4
is also shown in Mu 6-.

In the operation mode in which the RAII system polarization signal is signaled, in response to the RA8 polarization signal C being set to the low level, internal timing signals φB and φMUI11 are set to a low level. It will be done. Therefore, MO81FInTGL+oa, Qse*QI@
- is on-state IIK. MO8F] [1TQ-0° is turned on and Mo81! ']1TQl
- or off-state 11. 19MO8PICTQ+@s
is IIKed on and MO8PIlltTQl is
lli)h 2i The situation is brutal. MO8FmlTQ
Io? Since an electric voltage v0° is applied to the gate of H17, the source and drain of H17 are maintained in the ON state 11 which is below the electric voltage. Therefore, MO8FICT
1 which is output to the common edge point of GLsei and qII-! In the issue, MO81Fj1iTQi@? MO13 through 1cm
F'1llTGL+os game) K@ will be thinned. Therefore, MO8PMITQ-0- is also turned on.

When the RA8 signal is set to low level in this way,
The output signal φPG°, Mo1FITQ...8a @? V as shown in
It is set to a low level like the *m potential of the C#t circuit.

Similarly, the output signal φPG' a, M O8FMTQt
A similar low level is caused by the 1$ on state 111.

Next, when RAii is returned to the high level due to the end of the operation, the internal timing signal φ PI is first set to the low level as shown in FIG.
Next, after a predetermined delay time, the timing signal -II is brought to a low level as shown in FIG. 8O.

MOgPlτQ@sa s Q, *s and Ql, due to the tie-building signal φM being set to low level.

It turns into a pile of dust. , - Inner note φ 3 When the timing signal φ is set to low level, the timing signal φ
As shown in FIGS. 5 and 8, the program (1) is set to a low level of 11-. MOflFIT according to this nK
Qtes is installed in the case in the on state. Therefore, M.O.
MO87ITQla or MO871TEQ-■ and QI
At the common connection point with I4, the source and drain junctions connected thereto, depending on the capacity of the gate capacitance of yospztas*-, 1tLJs to the low level 1-. Mo1FI
TQt. .

Or off-state! MO8F”
T'Li@l, Ql- and 0 are maintained at a high level O with a similar capacitance to the common II point. Shut up, M
OB1, Tql and GLt are set to 1-, which is an on state.

Timing No. 411 φmmHtff After the timing signal φmmR is set to low level, it is set to low level after a predetermined polishing time.

MO8FJCT on one side to timing signal φmm
Q+@sk valve output 11AOzL/C durability n, b.

Therefore, the timing signal φm! Ilka I・Ilevel LI
As a result of the C field, the output g φi reaches a high level, such as the voltage O, as shown in FIG.

Immediately after the timing signal .phi.R is applied, the MO1ilF18Q--frame is maintained in the on state and the output 1111i0atl is maintained at a low level. Therefore, when the tying signal φm III is set to 11, the bootstrap receptacle OB.

It is precharged via the frame, Mo1FITQ+@・.

Timing signal - hxa H% Mo1FI on the other hand
Supplied to the gate of TQt@-. timing signal φ1
When ■ is set to 11, MOaFI is
TQtes or on-state l! be made into MOflFITQt
MOaFlT by being es or on IIK
Since the gate of QI@- is charged up to a high level fL, it is turned on.

And Kot) M Oa FIT, Qt@@ is on state a!
When this happens, the nine turtle loads that have been accumulated in advance at the gates of MO8PMTQ■s and Q clouds are pulled out. the result,
1i after the timing signal φmme goes to high level
MOaFITQtes for a predetermined time determined by the on-resistance of 0871TECL@o.

Qls is turned on.

M engineering a F l T Q st @rt , its gate is coupled to the output -OI, and the timing signal φ M R
1...KgEh will be turned on if it is trapped by an enemy.

Therefore, the timing signal φπ' outputted from the output car OAK
a, after a predetermined time has elapsed since the timing signal φAll or /1 is input, the M operation 5yicteQl is activated as described above.
When t is turned off, it changes to the /'-level.

Output line Qg<timing signal φpQu to be output, Pootstrap capacitor @OB precharged as described above
As the voltage level k of the output kos is increased due to the bootstrap effect of
As shown, the power supply voltage will rise steadily from the level of vao.

Output &10t potential μ, Molν1TGLts. or the high level of the output IIIO&
Since it is set to A, Mo1FITQr+ can be increased by 8 at level 1 of voltage v0° regardless of the pupil voltage.

Note that when the potential of output #O1 is increased, VO! 1F
9. The source electrode of ITQ+@s now acts as a drain electrode. The drain electrode *frame comes to act as a source electrode. In this case, M051FITQle Hatani,
Since a negative bias voltage is essentially applied to the gate electrode of the IE electrode which acts as the source electrode, the IE electrode is turned off. Therefore, the charging charge in the bootstrap capacitor OB, MO8FIteQIesk
It cannot be discharged through.

By performing the same operation as the circuit shown in FIG. 6 in the circuit shown in FIG. 7, the *-voltage v0.degree. In addition, 8
g7 The precharge path pc shown in Figure 4B is supplied to the circuit shown in Fig.
, , P.O.

In, MO8FITQezh GLss, GLss
and Qss, timing No. 11 φPG° and φBL:
By raising the D/% resistance sufficiently above the voltage v0° level as described above, the on-resistance mt is sufficiently low even when the common data I10 and Ilo are brought to the voltage v0° level. -Always on wllp
K to hold it. Since then, the precharge level t-1#[pressure vo] of the common data 10 and 10 has been set. You will be able to raise it at level 1.

Incidentally, when the precharge level of the common data 1 and 10 is increased as described in 1 above, the drain voltage of MO8PICTQts etc. forming the column switch is increased accordingly.

Therefore, MOjiFl? Although Qvs etc. are suddenly turned on, it is possible to increase the drain-source current caused by Kf, so output No. 1 of the sense amplifier S is used as common data 1 and 10. There is also the advantage of being able to convey the knowledge to the 10K students. Therefore, it is possible to make it A4 with this nine.

[Main amplifier]

As shown in Fig. 511, the main amplifier MA, gate, and drain are cross-connected to each other.
CTQes, Qel and their Mo1FIIT
Qtee * Qtoz, a timing signal φma provided between the common source and the ground potential
The power switch MOaFm"Qi@l is controlled by the power switch MOaFm"Qi@l.

The connection between the pair of input nodes of the main amplifier M and the common data 1 and Ilo is a cut MO8F IC controlled by a tie signal φRgKL, respectively.
T Q @ @ , Q @ y @ setup t'Lte'-Qh.

[Main amplifier operation]

A pair of O input nodes of the main amplifier M are precharged to $.

The timing signal φ! is a 0m8ss signal. When K/% is increased as shown in Figure 4B, the column switch circuits 0-11. and 0-1W, MO517mTQ like easy 0BIIIAT
Or on-state wAK is done. Therefore, the sense amplifier B
The data signal amplified by the sense amplifier is supplied to the common data 1 and 10.

The data signals given to the common data 1 and 10K are applied to a pair of input nodes of the main amplifier M through the cut MOIIFITq and Qlft valves.

Timing signal φ! After a delay after the high level δ is reached, a pair of human powered nodes KiIA of the main amplifier M are given a huge level difference.
The timing signal φml appears at a high level as shown in Figure 4B. Its function is to control the operation of the main amplifier MA. Among the pair of human-powered nodes in the main amplifier MAK, the amplification operation of the input node stile, which has a relatively low potential 11C5 according to the potential of the common data 1 and 10 or 10, starts. By doing so, he is lowered into the history of the (b) road's am turtle position. The other human power node σ is placed in a horizontal position, and the amplification MOgpm'r is connected to the drain.
The high potential is set to 1 to 1 by substantially turning off all the transistors.

Among the common data lines 10 and xlo, the common data III, which has been made to a relatively low potential by the output of the sense amplifier, is charged with a charge. Q vs Mata 1akes
The k valve is turned on and discharged to bring it to a low level. That is, common data volumes x10 and l10K:
given cold level ii.

It will be amplified by the main amplifier iris.

In order to amplify the level of the data signal in such common data #, there is a
It is effective in dissolving lIyIIA.

Main amplifier MA, amplification MO8PITQ, Hatake, q...
Each gate or common! ! Installed output MO8FII
Including TQ assault... and Qt@-. Output MO8FI
The drain output signals of TQ+o and Qts- are supplied to an output buffer circuit DOBK. Output buffer circuit D
Timing signal φBq, irises 4B for OBj@ production
As shown in the figure, the timing signal -ma for controlling the main amplifier operation is set to high level and then set to high level after a predetermined time. An output signal DOUT as shown in FIG. 4B is outputted from the output buffer latch 1aDOB in accordance with the /S level of the timing signal -0F. Incidentally, when the timing signal φOF is set to a low level at the output buffer of the output buffer Kojiji DOB, it is brought into a floating state.

In the main amplifier M shown in FIG. If not, a pair of manual nodes of the main amplifier M, each cut MO13FliteQs
common data 10 and 10 through s and Qsy k
The pre-charge is terrible.

The cuts MO8FITQ@- and Q are controlled by a timing signal φBg4C as shown in g4B.

In order to raise the tying signal -i to the level of the precharge level of the main amplifier A pair of human power nodes t, the common data l10h and the voltage v0° of the common data l10h and the voltage v0°, the VO is preliminarily applied. 10vth (However, Vo. [wL
- Voltage, V, , 1M087Ite's Nutness Hold Voltage) is set to a high level. Taikinguigigoφi
At such a high level, the timing signal φm for the main amplifier operating state is
It is maintained by Kaya who is made to level 3.

Therefore, cuts MO8FIITQ and Q9. Column switch circuit O-S by frame, timing signal-YVC
W, and M08FllT such as MOaFITQ de S in a-swlvc will have a relatively low on-resistance even after being turned on. As a result, a level difference corresponding to the data signals applied to the frame and common data I10 and I10K is applied to a pair of human-powered nodes in the main amplifier M with a comparative I% performance level t.

In Thailand, g1 No. It is lowered at the level Kll of turtle-tortoise pressure v0°.Therefore, MO8FICTGLss and QI
FA gradually begins to have ALA on twist.

By setting the timing signal φRg applied to the gates of the cut MO87ITQe and Qev to a relatively low level, the pair of manual nodes of the main amplifier MA are connected to the common data 1 and 10, and the input amplifier B. or be neglected. That is, the threshold coupling between the pair of human powered nodes of the main amplifier M and the common cheater is weakened. Even if there is a paranormal capacitance of the large-sized tortoise that is commonly kept as a common data source, the capacitance (not shown) coupled to a pair of human power nodes of the main amplifier M is substantially reduced. be done. As a result, the main amplifier M and its negative functions are destroyed, and the driver has to commute to work four times. Main amplifier MA or a16 speed operation rh allows data to be input from memory 1l-Jj4
It is movable to spread around the stray lil.

The timing signal φRg frame, as shown in FIG. 4B,
When the timing deviation φ is changed from a high level to a low level, the low level of the ground potential is changed.

That is, cut MO1i1FICTQ1. and Q.7
For example, the timing signal φ,. Based on the precharge (b) WIP OI is suddenly turned off when the operation is started again. Since then, the precharging of the common data I10 and Ilo can be started even though the main amplifier M is in operation.

Timing signal φFgi! , depending on whether the main amplifier operation control timing signal φma is low level [1],
is set to 1 level (of the level of the fishing voltage v0°).

Timing signal φIga, II! IE after a predetermined time
(It is made to change to a level 1% higher for four elements than l voltage v0°.

In addition, in the write operation mode, the write enable No. 1B vm goes to a low level as shown in FIG. 4B. In this case, a data signal to be convolved into the common data $1111, 10, and Ilo is supplied from the 7-time data input.

This one-shot mode with apricot sauce? Then, the main amplifier MA
In order to prevent the voltage from affecting the common data I/O and the potential of the circuit 10, the timing 1! No. φ, gr
[, IE4 BaK broken MT indicator water storage, synchronized with the timing signal -ma, is set to the low level of the ground potential.

In a circuit of approximately 5iW, the precharge voltage applied to the pair of input nodes of the main amplifier M is the amplification Mo8.
It acts as a bias voltage at the start of operation for 1/XTQ a and Qee. Increase @MO81rRTQCs and Q
When the precharge voltage is significantly reduced, the device can operate with high conductance. This is 4Cg
5, the main amplifier MA'iji [1! #AJil''
r: @Subject can also be used. Therefore, sensing of the main amplifier M can be started at a point in time when the output signal from the sense amplifier 8 is small, so that it is possible to be busy making -S sea bream.

In addition, in the circuit shown in the IE5 diagram, the sensitivity of the frame and sense amplifier is the same, so data@DL, DL'@precharged,
MO8FITQy*, l; Ll υ for M
O8PIT is an electric voltage V. . The switch is controlled by the timing signal φK set to the high level above.

[Word Liao Boost Circuit] The selection level of word edge W1-1 L/k L W 1-64 is voltage V. . If the voltage is raised only to the level K, even if the potential of the data is raised to the level of 1 by the active restore circuit as described above, the memory capacity in the memory cell is 08KH,
Only the plow voltage minus the positive voltage r of the switch MOBIMTQM from the word-〇 selection level is supplied. Therefore, only a relatively small amount of information charge can be written into the memory cell. In this way, if the information charge is small, ml
It becomes necessary to repeat the refresh operation nine times within a relatively short period of time in order to regenerate the information lost due to the leakage current fiK.

In one line of Figure 5, convolution 1 is added to the memory cell and ^
In order to reduce the amount of information 11E to be loaded sufficiently, the selection level of the word line is raised to more than the *St pressure v0°.

To determine the word edge selection level, IE-voltage v0
Word line control signal φ at a level higher than ゜! Or it is done in the form Iit.

@9111) Krr, signal generation all path φX-GIMII
A bootstrap path B1 is shown in which the f/# signal IO change rate output from the control signal φ2 is substantially unrestricted and raised above the high level kpm voltage v0° level of the control signal φ2. ing.

Bootstrap function wIBmTKsP and flight number is generated (
b) Roadφ! - When the signal φX output from G1m1m is set to low level, 1% processing 8FITQa, 1 and Q
llm is on-state JIK. At this time, the bootstrap capacitance OB@ is the diode-connected MO8νlT
The precharge status is clearly entered through the Qmta and M engineering S series TQmlk. Since the output of the primary inverter circuit vl is set to high level, M O8P I T
One of the gates of QIa and the bootstrap capacitor @OB, O11&a, MO8FJl;TQ*Iik, is held at a low level K11l.

In response to the timing signal φR from the awe raw path φ1-Gllfl being set to high level as shown in FIG. The word line side control is set to the high level of the voltage v0° level! 1g No.1φ
I is output.

Even if the word edge side @deviation signal φX is set to a high level, the output of the inverter circuit V and its delay time are set to a high level. Therefore, the boot ninja trap capacity OB, [,
Charged via Mo8FITQssa and Qll.

At the output of the inverter circuit I'VI, after the above delay time,
is set to the low level of the ground potential. By the low level output of the inverter path IV-, the MO81X
1 and Qats stile off type 1114c explodes. Pootstrap valley 110B- and 01lyKll-voltage v0 through its WI squared, MolνlTQ*t・and GINI k
゜Or a gift shop will be opened.

MOalFMTGLmis or Pootstrap capacity OB
, is turned on by the voltage increased by the Pootstrap capacitance OB-, so that the voltage ratio increased by the Pootstrap capacitance OB- is connected to the word signal 1 through MO8FltQ□,k.
K is added to.

That is, the word control signal φX at the t-voltage level outputted from the signal generation circuit 7-GINI is caused to have the WLll voltage by the 7'-tostrap circuit B-TE as shown in the accumulation diagram. The level increases by p4.

In response to the word line side m signal φXσ and the timing signal φ1■, which is an Rm8 system signal, being set to high level, the fourth mK is driven to a low level as shown. MOII which is controlled by the timing signal φm in the critical bootstrap 1gJ path BBT shown in FIG.
FITQmts Provided between the gate of iEM08FITQ*ta and the II ground potential point. MOLilFI
TQ, I, frame and timing deviation signal φB are suddenly turned off by setting them to high level. Since then, Pootstrap's weight CB- or pointless Km electric shock can be prevented.

Poot strap l [l! At 1MB8T, the bootstrap storage OB-frame is made to have a relatively large capacity to accommodate relatively low IL storage capacity. On the other hand,
Poot strap capacity 011yHMO8FlteQsk
Since it is only necessary to encourage them, the amount stored is relatively small. As shown in the front of the bootstrap capacitor 0B-U with a relatively large Vt, photovoltaic signals are applied independently to the operation of the signal generating circuit φX-GINm. Therefore, Pootstrap times l113B8T stile,
Signal generation - path ≠ I - Relatively small ^ negative #It for GIAMIAK is just below the bottom.

Word-system-signal φ! is supplied to word # through MOgFITQas or Qll and 9 or q1, etc., which are switched by the output of R-DOR-.

At the sP% 1st s111, the output of R-DORI is 1.
To 11! It is one piece of MO81Fm cut into n*MoaymτQts or Qss etc. for one person. MO8711 by R-DORIK! When the gate of Qte is supplied with an iIA selection level that is close to the voltage v0°, the gate voltage of this hi OB F I T Qam and the channel range and K Therefore, the voltage of the O voltage is applied to the frame and the cO difference between the frames and the O voltage. Therefore, the word line side m signal φ! Or high level Kf
%MO8P]CTQ, , If), the gate potential is further raised above the level of the word f1m control signal φX due to the bootstrapping effect of the above-mentioned capacitance. Since I#i, MO8FITQ*s is sufficiently maintained in the ON state 11 even if the word output signal φX is raised above the wL insertion pressure v0° level. Cut MO8F
ITQaoU and MO87ITQas are automatically turned off by raising their gate potentials. R
- Cut M where the low level signal of DOR is not supplied
O8FET1), word 1 system - signal -! Regardless of the level, it will be on-state 11JK. Therefore, in an on-state situation, suddenly an*"t"%/'hMO8FI? , for example, from Qvs to GLst, word line side control No. 4111φX
Regardless of your level, you can run an 11km off course.

Similarly, Gae/l1M01i11FITQ mouth or Ql
? M08 now supports word IIIK
? IT is successfully turned on.

In order to speed up the creation of frames and memory cells in the 1st row of the assembled diagram, each word ``Ll-@4 and W
LI-1-WIJI-44 and Di-Word style D
WL, -self, DWL・-B (DWLl-1+D
MOJiF]1TQsst and qO are synchronously turned off when the word 1 m signal φX rises between WL@-1 (not shown) and W ground potential.
is provided. Each MOJ above [l? QII or Q
The word tsm signal φ is applied to each on-resistance cylinder of as.
It is set to be sufficiently large for the 11-level output impedance of the timing generation path forming xk, and the parallel composite resistance cages thereof are set to be sufficiently small.

The common word @IIC via R-11WIlj is also falsely provided with MOIFITQaa to Qas of the same machine.

C are 0M0Iν1TGLss L/%LA41 etc.,
Word layer system by seven parallel composite beast cages - the rising of the high level of signal fx is selected from x') o word layer rL4
The operation is performed to suppress the p-level mK up to I. (-4D
M button R-DOROaIR-The word ml1lIII4Ii number φI that was automatically combined with the end of the work is R41
It will be iit.

After setting the hot water@vc tying margin for the aF operation M completion timing, the word control signal φ is sent from the signal generation circuit φX-G11m.
! Even if you don't make it output, you will start to despise it. It becomes 1 so that it can be operated with the **%-path Fal + Unwrinkle.

Note that before the R-DORIDORID output level is set to a good level [16 control signal φr211j output t″L], the potential of the selected word layer is undesirably increased, and the OWI event occurs. , the aroma information in the memory cell is destroyed.In order to prevent such undesirable one-way operation, the R-DORII is applied to the control signal φ! as described above.
E) Selection - Must be made to be output after completion of production #
It must be i.

[Pootstrap circuit for column switch] f-11g
DL @ etc. is precharged to the level of the electric pressure V0゜, and the common data 10 and 10 of the same machine are precharged to the level of the electric pressure V0゜. In such a case, in order to transmit the data signal from the data to the common data forest at high speed, and conversely, in order to transfer the data signal i from the data to the data 711 at high speed, ychi a21 step 0-811K>F
MOIllllMTtl like fhMO8FITQys
, it is preferable that the signal be driven by a signal that is raised above the power supply voltage v0° level.

In Figure 115, the power supply voltage vao level for supplying to the column switch circuit 0-812 is set to the igIW & which has accumulated water! A 111@signal φX is formed in which p is also raised.

Control m @ issue φ! In the same plane as the route shown in Figure 9,
It is output from the ll1LID- path.劃-signal φ! In order to form
In synchronization with the rising of the voltage, the output circuit for outputting the signal 91 which rises to a high level of the voltage v0° is connected to the Pout strap shown in the box summary 9-. Road B8
A total of 100 million Pootstrap circuits are provided. The first signal! Level Poot Strap for
MOalMTql- shown in 1i21st road KH1 No. 9-
Instead, break the same figure? #7i There is a MO#FITQuy that looks like surface water has been accumulated with hair.

Data selection-path flA, frame, data path selection MO
JIFII! TQyi, Qts 4! 1 de-1 control for O gate and ground potential amount! In response to the rising r of No.-y < 7 state @Kink M O51F M T Qvt
, Qys Hibiki: m is provided. These MO13
FIliTQ? ? .

Q? I, etc. perform the same operation as LQs* without MOIFITQ. Common word 1 via 0-8Wlj
A similar MolνIT is also provided for the overselection signal 1.

The CIv invention is not limited to the above-mentioned implementation, but the true essence @1
A single frame can be freely transformed.

[Brief explanation of drawings]

Figure 1 shows the flow diagram of the dynamic salt memory system.
Figure 2 is a block diagram of a dynamic memory device. l
! Figure 3, Figure 3Bl14, Figure 4A, and Figure Hatake 4B are the operating waveform diagrams;
Figure 8 shows its operating waveform diagram, Figure 19 shows a specific circuit diagram of the Oshi-Puttstrup follicle, Figure 10, and l! FIG. 11 is an #L-shaped diagram showing the first mode of operation. Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 Fig. 11 cz<s>---f'---- 2ゎ、-

Claims (1)

[Claims] 1. A sense amplifier that receives and amplifies signals from a pair of data blocks to which signals from selected memory cells and data cells are respectively transmitted;
) A pair of common data signals transmitted via a path, a precharge circuit that precharges this common data at a voltage level of 1, a main amplifier that receives the signal of this common data, and a main amplifier that receives the common data signal. Dynaic 11M
O8 memory device. 2. Common data and main amplifier amplification M0811TO
1. The MOB memory fixing device according to the claims set forth in claim 1 states that a cutting MOBIX tip is provided in the connection with the gate. 3. The precharge circuit is formed by the Rm 8 thread signal and the Om 8 thread signal, and the M which is driven by the boot 7 trap area pressure.
O8PKT Busy Electric Voltage! Item 1 or 2 of the scope of the 脣uxuanjokyo, which is characterized by being precharged with
Dynamic MO8 memory i! Place. 4. The precharge level to data 1 must be up to the illumination voltage level. %I'F
Scope of claims 1. Dynamic type M08 memory IIT described in the second or third frame.