JPS581818B2 - logarithmic converter - Google Patents

Description

[Detailed description of the invention] This invention relates to a logarithmic converter.

In the logarithmic converter, using an NPN type transistor,
It is well known to have a structure in which an input voltage is applied to the base and the collector current is output.

That is, as shown in FIG. 1, a transistor 2, which uses the PN junction between the base and emitter as a diode, is connected to the base of an NPN type logarithmic conversion transistor 1.
An input voltage is applied to the input terminal 3 connected to the emitter, and the collector current of the transistor 1 is detected by the detection circuit 4. The output current detected by the detection circuit 4 is applied to the human input terminal 3. It is designed to be a logarithmic value of the input voltage given.

Note that the transistor 2 is for temperature compensation of the transistor 1, and the change in the temperature coefficient of the transistor 1 is canceled out by the transistor 2.

Reference numeral 5 indicates a constant current source, and reference numeral 6 indicates an emitter bias resistor, which is normally a resistor with a low resistance value, but may not be used depending on the case.

By the way, according to such a configuration, the maximum value of the output current, that is, the collector current of the transistor 1, does not exceed the current amplification factor times the constant current from the constant current source 5, and in order to further increase this value, it is necessary to , a resistor 6 with a low resistance value is connected to the emitter of the transistor 1, a bias current is caused to flow from the bias current source 7, and the emitter bias potential of the transistor 1 is increased to obtain a logarithmic output current that is sufficiently smaller than that of the constant current source 5. The aim is to obtain up to

However, even if the resistance value of the resistor 6 is made considerably low, the output current flows through the resistor 6 and a parasitic voltage is generated there, so that linear logarithmic conversion cannot be expected in a region where the output current is large.

The object of this invention is to enable linear logarithmic transformation over a large range.

In this invention, for the above purpose, a current proportional to the current flowing through the collector of the transistor for logarithmic conversion is drawn out from the emitter of the transistor, so that the output current does not equivalently flow through the resistor. It is something.

FIG. 2 shows an embodiment of the present invention, in which 11 is an NPN type transistor for logarithmic conversion, and 12 is a PN type transistor for temperature compensation.
13 is an input terminal, 14 is a constant current source, and 15 is a low resistance bias resistor connected to the emitter of transistor 11. The above configuration is the first one.
There is no major difference from the configuration shown in the figure.

16 is a transistor that uses the PN junction connected to the collector of transistor 11 as a diode; 17 is an NPN transistor connected in parallel to resistor 15; 18
is a transistor that uses a PN junction as a diode,
The bases of the transistor 17 are connected to each other.

A transistor 19 is connected in series to the transistor 18, and a transistor 20 is also connected to a current detection circuit 21.

The bases of each transistor 16.1920 are connected to each other, and each emitter is connected to the power supply terminal 22.

Therefore, the current flowing through transistor 16 (which is also the collector current of transistor 11).

), a current equal to or proportional to transistors 19, 2
It will flow to 0.

Further, since the bases of the transistors 17 and 18 are connected together, a current equal to or proportional to the current flowing through the transistor 18 flows through the transistor 17.

In the above configuration, the current flowing through the collector of the transistor 11 with respect to the input voltage applied to the input terminal 13 corresponds to the logarithm value of the input voltage, which is the same as in the configuration shown in FIG.

Here, the current flowing through the transistor 11 tries to flow through the resistor 15, but of the current, the same current (or the current proportional to the current flowing through the collector of the transistor 11)
The current flows to transistor 18 and hence to transistor 17.

In other words, the collector current of the transistor 11 (or a current proportional to this) is extracted from the current flowing through the resistor 15, and the remaining current flows through the resistor 15.

As a result, the output current (collector current of the transistor 11) equivalently does not flow through the resistor 15.

Therefore, linear logarithmic conversion is possible even in a region where the output current is large.

Since the same current (or proportional current) as the current flowing through the transistor 16 flows through the transistor 20, it goes without saying that the current detected value by the detection circuit 21 becomes a logarithmic value corresponding to the input voltage.

As detailed above, according to the present invention, it is not necessary to make the bias resistor sufficiently small and to flow a large current through it to obtain the bias voltage. Even when obtained, linear logarithmic transformation can be performed over a large range, and logarithmic sweep from 0.sup. is easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 11...Transistor for logarithmic conversion, 13...
...Input terminal, 15...Bias resistance, 1
6.17...Transistor using PN junction as a diode, 18.19...Transistor, 21...Current detection circuit.

Claims (1)

[Claims] 1 a logarithmic conversion transistor through which a collector current corresponding to the logarithmic value of an input voltage applied to the base flows; a first transistor connected to an emitter bias circuit of the logarithmic conversion transistor; a second transistor whose bases are connected to the base of the transistor for logarithmic conversion and whose collectors are connected to the base of the second transistor; comprising third, fourth and fifth transistors that flow collector currents corresponding to the collector currents of the transistors;
The third transistor is connected in series to the logarithmic conversion transistor, the fourth transistor is connected to the second transistor in series, and the detected value is connected in series to the fifth transistor so that the detected value is the logarithmic value of the input voltage. A logarithmic converter formed by connecting a detection circuit.