JPS58181198A - Resistance simulator - Google Patents
Resistance simulatorInfo
- Publication number
- JPS58181198A JPS58181198A JP6350582A JP6350582A JPS58181198A JP S58181198 A JPS58181198 A JP S58181198A JP 6350582 A JP6350582 A JP 6350582A JP 6350582 A JP6350582 A JP 6350582A JP S58181198 A JPS58181198 A JP S58181198A
- Authority
- JP
- Japan
- Prior art keywords
- detection circuit
- variable resistance
- resistance element
- current
- closed loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Alarm Systems (AREA)
- Emergency Alarm Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、測温抵抗体を用いた温度警報装置の試験に使
用して好適ならしめた抵抗模擬装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resistance simulator suitable for use in testing temperature alarm devices using resistance temperature detectors.
従来、この種の装置として第1図に示すものがあった。Conventionally, there has been a device of this type as shown in FIG.
図において、(1)は第1電極と第2電極間の電流通路
の抵抗率が第3の制御電極によって変化される電圧制御
形可変抵抗素子、(2)は可変抵抗素子(1)の端子間
電圧を検出する電圧検出回路、(8)は可変抵抗素子(
1)に流れる電流を検出する電流検出回路、(4)は上
記可変抵抗素子(1)の抵抗値を設定するデータ入力(
6)によって出力が制御されるアナログデジタルコンバ
ータ(以下いコンバータト称す) % (6)は上記可
変抵抗素子(1)の第3電極への供給電圧を制御するこ
とによシ該可変抵抗素子(1)の抵抗値を調整する演算
増巾器s (7) 、 (8)は抵抗模擬装置の出力端
子、R□〜R3は抵抗で、該可変抵抗素子(1)と電圧
検出回路(2)及び演算増巾器(6)とて第1の閉ルー
プが形成され、該可変抵抗素子(1)と電流検出回路(
8)及び演算増巾回路(6)とで第2の閉ループが形成
されてお)、上記演算増巾器(6)は電圧検出回路(2
)と電流検出回路(8)及びAβコンバータ(4)の各
々の出力を演算増巾した出力でもって可変抵抗素子(1
)の第3電極を制御するようになされている。In the figure, (1) is a voltage-controlled variable resistance element in which the resistivity of the current path between the first electrode and the second electrode is changed by the third control electrode, and (2) is the terminal of the variable resistance element (1). The voltage detection circuit (8) is a variable resistance element (
1) is a current detection circuit that detects the current flowing through the circuit; (4) is a data input (4) that sets the resistance value of the variable resistance element (1);
% (6) is an analog-to-digital converter (hereinafter referred to as converter) whose output is controlled by the variable resistance element (1) by controlling the voltage supplied to the third electrode of the variable resistance element (1). The operational amplifier s (7) and (8) are the output terminals of the resistance simulator, R□ to R3 are resistors, and the variable resistance element (1) and the voltage detection circuit (2) are used to adjust the resistance value of the variable resistance element (1). and an operational amplifier (6) to form a first closed loop, which connects the variable resistance element (1) and the current detection circuit (
8) and the operational amplifier circuit (6) form a second closed loop), and the operational amplifier (6) is connected to the voltage detection circuit (2).
), the current detection circuit (8), and the Aβ converter (4).
) to control the third electrode.
上記第1図構成において、今、端子(6) 、 (γ)
間の電圧をEH(v)s端子(6)に流入する電流を工
R(A)とすると、電圧検出回路(2)の出力電圧はx
v−gR(vl電流検出回路(8)の出力電圧は−に工
・工RCV)で表わされ(ただしKvおよびに工は比例
常数である)、A/’Dコンバータ(4)の出力電圧−
Eつは抵抗R3、電圧検出回路(2)の出力は抵抗R□
、電流検出回路(8)の出力は抵抗R2を介してそれぞ
れ演算増巾器(6)に入力され、ここでこれら電圧検出
回路(2)、抵抗R□、演算増巾器(6)、可変抵抗菓
子(1)で形成する第1の閉ループ、電流検出回路(8
)、抵抗R2、演算増巾器(6)可変抵抗菓子(1)で
形成する第2の閉ループが同時に作用するので、図示点
Xでは次の条件で平衡する。In the configuration shown in Figure 1 above, now terminals (6), (γ)
If the voltage between EH (v) and the current flowing into the s terminal (6) are R (A), then the output voltage of the voltage detection circuit (2) is x
It is expressed as v-gR (the output voltage of the vl current detection circuit (8) is - RCV) (however, Kv and RCV are proportional constants), and the output voltage of the A/'D converter (4) is −
E is the resistor R3, and the output of the voltage detection circuit (2) is the resistor R□
, the outputs of the current detection circuit (8) are input to the operational amplifier (6) via the resistor R2, and here the voltage detection circuit (2), the resistor R, the operational amplifier (6), and the variable The first closed loop formed by the resistance confectionery (1), the current detection circuit (8
), the resistor R2, the operational amplifier (6), and the second closed loop formed by the variable resistance confectionery (1) act simultaneously, so that at point X shown in the figure, equilibrium is achieved under the following conditions.
Rユ R3R2
従って、端子(6) I (γ)間の抵抗値は次式で表
わされることになシ、
図示される抵抗模擬装置は電流工、が一定の条件のもと
に、ψコンバータ(4)の出力電圧−EDで端子(6)
、 (γ)間の抵抗値、すなわち可変抵抗素子(1)
の抵抗値が設定できることになる。Therefore, the resistance value between terminals (6) and I (γ) can be expressed by the following formula. 4) Output voltage - ED at terminal (6)
, (γ), that is, the variable resistance element (1)
This means that the resistance value can be set.
しかるに、従来の抵抗模擬装置は以上のように構成され
ているので、可変抵抗素子(1)に流れる電流lRが一
定の条件のもとに使用しなければならなく、その適用範
囲が限定されるという欠点があった。However, since the conventional resistance simulator is configured as described above, it must be used under the condition that the current lR flowing through the variable resistance element (1) is constant, and its range of application is limited. There was a drawback.
そこで本%明は上記のような従来のものの欠点を除去す
るためになされたもので、可変抵抗素子に流れる電流値
に拘りなく抵抗値の設定が出来る抵抗模擬装置を提供す
ることを目的として、係る目的を達成するために、第1
の閉ループ又は第2の閉ループのいずれかの検出回路と
演算増巾器との間に開閉素子を設け、その開閉デユーテ
ィサイクルの制御によって上記演算増巾器へのフィード
バック量を調整し可変抵抗素子の抵抗値を設定すること
を特徴とするものである。Therefore, the present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and the purpose is to provide a resistance simulator that can set the resistance value regardless of the current value flowing through the variable resistance element. In order to achieve this purpose, the first
A switching element is provided between the detection circuit of either the closed loop or the second closed loop and the operational amplifier, and the amount of feedback to the operational amplifier is adjusted by controlling the switching duty cycle of the variable resistance element. This feature is characterized by setting the resistance value of .
以下、本発明の一実施例を第1図と同一部分は同一符号
を附して示す第2図について説明する。Hereinafter, an embodiment of the present invention will be described with reference to FIG. 2, in which the same parts as in FIG. 1 are denoted by the same reference numerals.
第2図において、(9)は第2の閉ループを形成する電
流検出回路(8)と演算増巾器(6)との間に設けられ
て演算増巾器(6)へのフィードバック量を変化させる
開閉素子で、制御入力α0)によってその開閉デユーテ
ィサイクルが変化するようになっている。その他は従来
と同様である。なお、第1図のA/1)コンバータ(4
)は含まれない。In FIG. 2, (9) is provided between the current detection circuit (8) and the operational amplifier (6) forming a second closed loop, and changes the amount of feedback to the operational amplifier (6). The opening/closing duty cycle of the opening/closing element is changed by the control input α0). Others are the same as before. In addition, the A/1) converter (4
) are not included.
係る構成において、第2の閉ループを形成する電流検出
回路(8)から開閉素子(9)を介して演算増巾器(6
)に入力される電流1工は、
5−
上式によって示されることになシ、電圧検出装置(2)
、抵抗R□、演算増巾器(5)、可変抵抗菓子(1)で
構成する第1の閉ループと電流検出装置(8)、開閉素
子(9)、演算増巾器(5)、可変抵抗菓子(1)で構
成する5g2の閉ループとの間には、点Xにおいて次の
条件で平衡する。In such a configuration, the operational amplifier (6) is connected from the current detection circuit (8) forming the second closed loop via the switching element (9).
) is input to the voltage detection device (2), which is not indicated by the above formula.
, resistor R□, operational amplifier (5), variable resistance confectionery (1), current detection device (8), switching element (9), operational amplifier (5), variable resistance There is an equilibrium at point X with the closed loop of 5g2 consisting of confectionery (1) under the following conditions.
RIR,T
従って、端子(6) 、 (γ)間の抵抗値は次式で表
わされる。RIR,T Therefore, the resistance value between terminals (6) and (γ) is expressed by the following formula.
工RR2・Kv T
すなわち、端子(6) 、 (7)間の抵抗値が開閉素
子(9)のになシ、制御入力α0)によって開閉素子(
9)の開閉デユーティサイクルを制御することにより可
変抵抗 6−
素子(1)の抵抗値を設定することができ、可変抵抗素
子(1)に流入する電流値の影響を受けないことになる
。In other words, if the resistance value between terminals (6) and (7) is different from the switching element (9), the switching element (
By controlling the opening/closing duty cycle of the variable resistor 6- element (1), the resistance value of the variable resistor 6-element (1) can be set and is not affected by the current value flowing into the variable resistor element (1).
なお、上記実施例では開閉素子(9)を第2の閉ループ
内に設けて電流検出回路(8)から演算増巾器(6)へ
の入力電流を制御したが、第1の閉ループ内に設けて電
圧検出回路(2)から演算増巾器(6)への入力電流を
制御しても同様の効果が得られるのは勿論である。In the above embodiment, the switching element (9) is provided in the second closed loop to control the input current from the current detection circuit (8) to the operational amplifier (6), but the switching element (9) is provided in the first closed loop. Of course, the same effect can be obtained by controlling the input current from the voltage detection circuit (2) to the operational amplifier (6).
以上のように、本発明によれば、可変抵抗素子の抵抗値
を第1又は第2の閉ループのいずれか一方に設けた開閉
素子のデユーティサイクルで設定するように構成したの
で、外部条件の影響を受けずかつ高精度に抵抗値の設定
ができる抵抗膜擬装置が得られる効果がある。As described above, according to the present invention, the resistance value of the variable resistance element is set by the duty cycle of the switching element provided in either the first or second closed loop. This has the effect of providing a resistive film pseudo device in which the resistance value can be set with high precision without being affected.
第1図は従来の抵抗膜擬装置を示す回路図、第2図は本
発明の一実施例による抵抗膜擬装置を示す回路図である
。
(1)・・可変抵抗素子 (2)・・電圧検出回路(8
)@@電流検出回路 (5)e・演算増巾器(9)・
・開閉素子
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 葛 野 信 −FIG. 1 is a circuit diagram showing a conventional resistive film pseudo device, and FIG. 2 is a circuit diagram showing a resistive film pseudo device according to an embodiment of the present invention. (1)...Variable resistance element (2)...Voltage detection circuit (8
)@@Current detection circuit (5) e・Arithmetic amplifier (9)・
・Switching element In the figures, the same reference numerals indicate the same or equivalent parts. Agent Shin Kuzuno −
Claims (1)
電極によって変化される可変抵抗素子、この可変抵抗素
子の第1電極に一端が接続されて可変抵抗素子に印加さ
れる電圧に応じた出力電圧を送出する電圧検出回路、上
記可変抵抗素子の第2電極に一端が接続されて可変抵抗
素子に流入する電流に応じた出力電圧を送出する電流検
出回路、上記可変抵抗素子及び上記電圧検出回路と第1
の閉ループを形成し、かつ上記可変抵抗素子及び上記電
流検出回路と第2の閉ループを形成して該電圧検出回路
と該電流検出回路との出力差を演算増巾し上記可変抵抗
素子の第3電極を制御する演算増巾器を備えると共に、
上記第1の閉ループ又は第2の閉ループのいずれかの検
出回路と演算増巾器との間に設けた開閉素子を備え、こ
の開閉素子の開閉デユーティサイクルを制御することに
よって上記可変抵抗素子の抵抗値を設定することを特徴
とする抵抗模擬装置。A variable resistance element in which the resistivity of the current path between the first electrode and the second electric wire is changed by a third control electrode, one end of which is connected to the first electrode of the variable resistance element to apply a current to the variable resistance element. a voltage detection circuit that sends out an output voltage corresponding to the voltage; a current detection circuit that has one end connected to a second electrode of the variable resistance element and sends out an output voltage that corresponds to the current flowing into the variable resistance element; and the variable resistance element. and the voltage detection circuit and the first
and forms a second closed loop with the variable resistance element and the current detection circuit to computationally amplify the output difference between the voltage detection circuit and the current detection circuit. In addition to being equipped with an operational amplifier that controls the electrodes,
A switching element is provided between the detection circuit of either the first closed loop or the second closed loop and the operational amplifier, and the variable resistance element is controlled by controlling the switching duty cycle of the switching element. A resistance simulator characterized by setting a resistance value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6350582A JPS58181198A (en) | 1982-04-14 | 1982-04-14 | Resistance simulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6350582A JPS58181198A (en) | 1982-04-14 | 1982-04-14 | Resistance simulator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58181198A true JPS58181198A (en) | 1983-10-22 |
Family
ID=13231150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6350582A Pending JPS58181198A (en) | 1982-04-14 | 1982-04-14 | Resistance simulator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58181198A (en) |
-
1982
- 1982-04-14 JP JP6350582A patent/JPS58181198A/en active Pending
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