JPS6014212Y2 - inductance measuring device - Google Patents
inductance measuring deviceInfo
- Publication number
- JPS6014212Y2 JPS6014212Y2 JP7267078U JP7267078U JPS6014212Y2 JP S6014212 Y2 JPS6014212 Y2 JP S6014212Y2 JP 7267078 U JP7267078 U JP 7267078U JP 7267078 U JP7267078 U JP 7267078U JP S6014212 Y2 JPS6014212 Y2 JP S6014212Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- circuit
- amplifier circuit
- input terminal
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【考案の詳細な説明】
本考案は抵抗及びコイルの並列回路のコイルのインダク
タンスを測定し得るインダクタンス測定装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inductance measuring device capable of measuring the inductance of a coil in a parallel circuit of a resistor and a coil.
電子機器のＰＣ板ユニット上の実装部品あるいはターミ
ナル等に接続された部品で第１図に示すように抵抗Ｒと
コイルＬの並列回路構成の場合、従来の測定器では前記
コイルのインダクタンスを測定することはできなかった
。When a component mounted on a PC board unit of an electronic device or a component connected to a terminal etc. has a parallel circuit configuration of a resistor R and a coil L as shown in Figure 1, conventional measuring instruments measure the inductance of the coil. I couldn't do that.
本考案は抵抗及びコイルが並列接続された状態でコイル
のインダクタンスを測定し得るインダクタンス測定装置
を提供するものである。The present invention provides an inductance measuring device that can measure the inductance of a coil in a state where a resistor and a coil are connected in parallel.
以下図面を参照して本考案に係るインダクタンス測定装
置の一実施例を説明する。An embodiment of the inductance measuring device according to the present invention will be described below with reference to the drawings.
極性反転自在の直流電源１１の一端は基準電位点に接続
され、他端は抵抗値Ｒ１の第１の抵抗１２及び抵抗値Ｒ
２の第２の抵抗１３の並列回路を介して第１の直流差動
増幅回路１４の第１の入力端（ここでは反転入力端）に
接続される。One end of the polarity reversible DC power supply 11 is connected to a reference potential point, and the other end is connected to a first resistor 12 with a resistance value R1 and a resistance value R1.
The second resistor 13 is connected to a first input terminal (here, an inverting input terminal) of a first DC differential amplifier circuit 14 via a parallel circuit of two second resistors 13.
前記第１の増幅回路１４の第２の入力端（ここでは非反
転入力端）は基準電圧回路１６に接続される。A second input terminal (here, a non-inverting input terminal) of the first amplifier circuit 14 is connected to a reference voltage circuit 16 .
また第１の増幅回路１４の出力端及び前記第１の入力端
相互間に抵抗値Ｒ２の第３の抵抗１７が接続される。Further, a third resistor 17 having a resistance value R2 is connected between the output terminal of the first amplifier circuit 14 and the first input terminal.
前記第１の増幅回路１４の出力端は測定端子の一方１８
に接続され、測定端子の他方１９は第２の直流差動増幅
回路２０の第１の入力端（ここでは反転入力端）に接続
される。The output terminal of the first amplifier circuit 14 is connected to one of the measurement terminals 18.
The other measurement terminal 19 is connected to the first input terminal (here, the inverting input terminal) of the second DC differential amplifier circuit 20 .
前記第２の増幅回路２０の第２の入力端（ここでは非反
転入力端）は抵抗値Ｒ１の第４の抵抗２１を介して前記
第１の増幅回路１４の出力端に接続されると共に抵抗値
Ｒ２の第５の抵抗２２を介して基準電位点に接続される
。A second input terminal (here, a non-inverting input terminal) of the second amplifier circuit 20 is connected to the output terminal of the first amplifier circuit 14 via a fourth resistor 21 having a resistance value R1, and a resistor. It is connected to the reference potential point via a fifth resistor 22 of value R2.
前記第２の増幅回路２０の出力端及び前記第１の入力端
相互間に抵抗値Ｒ２の第６の抵抗２３が接続される。A sixth resistor 23 having a resistance value R2 is connected between the output terminal of the second amplifier circuit 20 and the first input terminal.
前記第２の増幅回路２０の出力端はゲート回路２４の制
御端に接続される。The output terminal of the second amplifier circuit 20 is connected to the control terminal of the gate circuit 24.
ゲート回路２４の入力端にはクロックパルス発生回路２
５、出力端にはパルス出力端子２６を介してパルスカウ
ンタ（図示せず）が接続される。A clock pulse generation circuit 2 is connected to the input terminal of the gate circuit 24.
5. A pulse counter (not shown) is connected to the output terminal via a pulse output terminal 26.
次に動作を説明する。Next, the operation will be explained.
直流電源１１により第１の抵抗１２及び第２の抵抗１３
の並列回路の入力端にｅｌなる直流電圧を印加したとき
第１の増幅回路１４の出力電圧ｅ′Ｉは次式のとおりで
ある。The first resistor 12 and the second resistor 13 are connected by the DC power supply 11.
When a DC voltage el is applied to the input terminal of the parallel circuit of , the output voltage e'I of the first amplifier circuit 14 is as follows.
但しＲ１・・・第１の抵抗１２の抵抗値
Ｒ２・・・第２の抵抗１３の抵抗値
Ｒ１が被測定コイルに並列接続されている抵抗Ｒ８と等
しく設定すれば（１）式は次式となる。However, if R1...the resistance value of the first resistor 12 R2...the resistance value R1 of the second resistor 13 is set equal to the resistor R8 connected in parallel to the coil under test, equation (1) becomes the following equation. becomes.
また第２の増幅回路２０に前紗′１なる直流電圧が印加
されると同増幅回路２０の出力電圧は次式のとおりであ
る。Further, when a direct current voltage of front voltage '1 is applied to the second amplifier circuit 20, the output voltage of the second amplifier circuit 20 is as shown in the following equation.
但しＲ１・・・第４の抵抗２１の抵抗値 Ｒ２・・・第５の抵抗２２の抵抗値 丁・・・Ｌｘ／Ｒｘ Ｒ１＝Ｒ，と設定すれば（３）式は次式となる。However, R1...the resistance value of the fourth resistor 21 R2...Resistance value of the fifth resistor 22 Ding...Lx/Rx If R1=R, then equation (3) becomes the following equation.
（２）式及び（４）式により ２ ｅｏ”１．、 ＠ｅｓ ” ｔ ・・・（５） となり、第２の増幅回路２０の出力ｅ。By equations (2) and (4), 2 eo”1., @es”t ...(5) Therefore, the output e of the second amplifier circuit 20 is.
は完全に時間に対し比例する。is completely proportional to time.
前記第２の増幅回路２０の出力電圧ｅ。Output voltage e of the second amplifier circuit 20.
が第３図（Ｃ）のように（ｔｄ）時間で所定の電圧（−
１，ＩＶ）に達したときゲート回路２４が開き、パルス
発生回路２５の出力は出力端子２６に導出される。As shown in Fig. 3(C), the predetermined voltage (-
1, IV), the gate circuit 24 opens and the output of the pulse generating circuit 25 is led out to the output terminal 26.
前記第２の増幅回路２０の出力電圧が（ｔｄ）時間で所
定の電圧（−１，ＩＶ）に達したことが検出されると自
動的に直流電源１１の極性が反転され前記第２の増幅回
路２０のｅ。When it is detected that the output voltage of the second amplification circuit 20 has reached a predetermined voltage (-1, IV) in time (td), the polarity of the DC power supply 11 is automatically reversed and the second amplification circuit 20 is activated. e of circuit 20.
は正極方向に推移しくｔｓ）時間で−０，１ｖに達した
ときゲート回路２４は閉じ、クロックパルス発生回路２
５の出力パルスが出力端子２６に導出されなくなる。changes in the positive polarity direction, and when it reaches -0.1v at time ts), the gate circuit 24 closes, and the clock pulse generation circuit 2
5 output pulses are no longer delivered to the output terminal 26.
出力端子２６に導出されたパルスは前記カウンタによっ
て計数される。The pulses delivered to the output terminal 26 are counted by the counter.
従って前記ゲート回路２４の開いている間パルスが計数
される。Therefore, pulses are counted while the gate circuit 24 is open.
前記個及ｔｓはインダクタンスの大小に比例しているの
で前記パルスの計数は被測定コイルＬ、のインダクタン
スに比例するので、計測の各レンジにおいて被測定イン
ダクタンスとパルス計数の絶対値が等しくなるように前
記直流入力電圧ｅｉ、第６の抵抗２３、クロックパルス
周波数を切換えを行なえばコイルのインダクタンスを求
めることができる。Since the number and ts are proportional to the magnitude of the inductance, the number of pulses is proportional to the inductance of the coil L to be measured, so the absolute value of the inductance to be measured and the pulse count are equal in each measurement range. By switching the DC input voltage ei, the sixth resistor 23, and the clock pulse frequency, the inductance of the coil can be determined.
第３図に回路各部分動作タイミングを示す。FIG. 3 shows the operation timing of each part of the circuit.
同図Ａは入力直流電圧ｅ、を示し、同図Ｂは第２の増幅
回路２０の入力直流電圧を示し、同図Ｃは第２の増幅回
路２０の出力電圧を示し、同図りはクロックパルス発生
回路２５の出力、同図Ｅはゲート回路２４の開放時間を
示し、同図Ｆはパルス計数を示すものである。Figure A shows the input DC voltage e, Figure B shows the input DC voltage of the second amplifier circuit 20, Figure C shows the output voltage of the second amplifier circuit 20, and Figure C shows the clock pulse. The output of the generating circuit 25, E in the same figure shows the open time of the gate circuit 24, and F in the same figure shows the pulse count.
以上のように本考案によるインダクタンス測定装置は抵
抗に並列に接続されたコイルのインダクタンスを測定す
ることができるので、ＰＣ板に実装された状態でコイル
のインダクタンス測定が簡単にできる。As described above, since the inductance measuring device according to the present invention can measure the inductance of a coil connected in parallel to a resistor, the inductance of the coil can be easily measured while being mounted on a PC board.
第１図は本考案に係るインダクタンス測定装置の被測定
回路、第２図は本考案に係るインダクタンス測定装置の
一実施例を示す回路構成図、第３図は同上動作タイミン
グを示す線図である。
１１・・・・・・極性反転自在直流電源、１２・・・・
・・第１の抵抗、１３・・・・・・第２の抵抗、１４・
・・・・・第１の直流差動増幅回路、１６・・・・・・
基準電圧回路、１７・・・・・・第３の抵抗、１８，１
９・・・・・・測定端子ζ２０・・・・・・第２の直流
差動増幅回路、２１・・・・・・第４の抵抗、２２・・
・・・・第５の抵抗、２３・・間第６の抵抗、２４・・
・・・・ゲート回路、２５・・曲クロックパルス発生回
路、
２６・・・・・・パルス出力端子。FIG. 1 is a circuit to be measured of an inductance measuring device according to the present invention, FIG. 2 is a circuit configuration diagram showing an embodiment of the inductance measuring device according to the present invention, and FIG. 3 is a diagram showing the operation timing of the same. . 11...Polarity reversible DC power supply, 12...
...First resistor, 13...Second resistor, 14.
...First DC differential amplifier circuit, 16...
Reference voltage circuit, 17...Third resistor, 18,1
9...Measurement terminal ζ20...Second DC differential amplifier circuit, 21...Fourth resistor, 22...
...5th resistor, 23...6th resistor, 24...
...Gate circuit, 25...Music clock pulse generation circuit, 26...Pulse output terminal.
Claims (1)
抵抗値Ｒ１の第１の抵抗及び抵抗値Ｒ２の第２の抵抗の
並列回路と、この並列回路の他端に第１の入力端が接続
され第２の入力端が基準電圧回路に接続される第１の直
流差動増幅回路と、この第１の増幅回路の出力端及び前
記第１の入力端相互間に接続される抵抗値Ｒ２の第３の
抵抗と、前記第１の増幅回路の出力端に接続される測定
端子の一方と、この測定端子の他方に第１の入力端が接
続され第２の入力端が抵抗値Ｒ１の第４の抵抗を介して
前記第１の増幅回路の出力端に接続されると共に抵抗値
Ｒ２の第５の抵抗を介して基準電位点に接続される第２
の直流差動増幅回路と、この第２の増幅回路の出力端及
び前記第１の入力端相互間に接続される抵抗値Ｒ２の第
６の抵抗と、前記第２の増幅回路の出力側に制御端が接
続されるゲート回路と、このゲート回路の入力端に接続
されるクロックパルス発生回路と、前記ゲート回路の出
力端に接続されるパルス出力端子とを具備し、前記測定
端子に抵抗及びコイルの並列回路を接続して前記コイル
のインダクタンスを求めるようにしたことを特徴とする
インダクタンス測定装置。A parallel circuit including a polarity reversible DC power supply, a first resistor having a resistance value R1 and a second resistor having a resistance value R2, one end of which is connected to the power supply, and a first input terminal connected to the other end of the parallel circuit. a first DC differential amplifier circuit connected to the reference voltage circuit and having a second input terminal connected to the reference voltage circuit; and a resistance value R2 connected between the output terminal of the first amplifier circuit and the first input terminal. a third resistor, one of the measurement terminals connected to the output terminal of the first amplifier circuit, a first input terminal connected to the other of the measurement terminals, and a second input terminal connected to the resistance value R1. A second resistor connected to the output terminal of the first amplifier circuit via a fourth resistor and connected to the reference potential point via a fifth resistor having a resistance value R2.
a DC differential amplifier circuit, a sixth resistor with a resistance value R2 connected between the output terminal of the second amplifier circuit and the first input terminal, and a sixth resistor connected between the output terminal of the second amplifier circuit and the first input terminal; It comprises a gate circuit to which a control end is connected, a clock pulse generation circuit connected to an input end of the gate circuit, and a pulse output terminal connected to an output end of the gate circuit, and a resistor and a resistor are connected to the measurement terminal. An inductance measuring device characterized in that the inductance of the coil is determined by connecting a parallel circuit of coils.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7267078U JPS6014212Y2 (en) | 1978-05-29 | 1978-05-29 | inductance measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7267078U JPS6014212Y2 (en) | 1978-05-29 | 1978-05-29 | inductance measuring device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54174374U JPS54174374U (en) | 1979-12-08 |
| JPS6014212Y2 true JPS6014212Y2 (en) | 1985-05-07 |
Family
ID=28984566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7267078U Expired JPS6014212Y2 (en) | 1978-05-29 | 1978-05-29 | inductance measuring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6014212Y2 (en) |
-
1978
- 1978-05-29 JP JP7267078U patent/JPS6014212Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54174374U (en) | 1979-12-08 |
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