JPS58179949A - Tape speed discriminating circuit of magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To dicriminate quickly the state of a magnetic recording and reproducing device when the recording mode is switched, by detecting that a driving means of a recording tape has a rise at a level close to a prescribed speed of revolution by a speed control means and then discriminating or holding the recording speed of the tape. CONSTITUTION:In the reproduction mode, a control pulse 7 of a magnetic tape is reproduced by a control head 1. The pulse 7 is then fed to a control period measuring circuit 4 after amplification 2 and waveform shaping 3. The measured period is fed to a mode deciding circuit 5. The signals obtained from a pulse detector 17 as well as a pulse generating means 15 attached to a capstan 16 are supplied to a speed control circuit 20 via the amplifier 18. The output of the circuit 20 is supplied to a capastan motor dirving circuit 19 to receive the control of speed. The circuit 20 delivers a signal 13 when the capstan signal is set at a level close to a sfrequency of a prescribed mode in order to actuate the circuit 4. In such a way, the state can be quckly discriminated for a magnetic recorder/reproducer when the recording mode is switched after the speed of a reproduced tape rises up the speed of a detected tape.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for automatically determining a tape recording speed when reproducing a magnetic tape recorded at a plurality of speeds in a magnetic recording/reproducing apparatus.

In a magnetic recording/reproducing device, by switching the tape speed of the same magnetic tape during recording, there are 4 second, play (hereinafter abbreviated as SP), long, play (hereinafter abbreviated as LP) and super long.

Recording may be performed at a plurality of tape speeds, such as in play (hereinafter abbreviated as SLP). Therefore, it is necessary to set the tape speed during playback to the same speed as during recording. In other words, SP-recorded tapes are SP replayed, LP-recorded tapes are LP-played, and 18LP-recorded tapes are SLPLP-played.
It is necessary to appropriately switch the tape speed during playback to match the tape speed in the recording state. Therefore, during playback, it is necessary to first determine the tape speed at the time of recording and then set the playback tape speed appropriately.

In this case, the speed must be set quickly and without malfunction.

FIG. 1 shows a conventional example of an SP, LP, and SLP detection circuit.

Further, the main waveforms of the same figure are shown in FIG.

In FIG. 1, 1 is a control, 2 is an amplifier, 3 is a waveform shaping circuit, 4 is a control pulse period measurement circuit, 5 is a mode discrimination circuit that determines whether it is SP, LP, or SLP from the 40 period measurement value. This is a time constant circuit that operates for a certain period of time when the 6-digit mode is switched.

At the time of reproduction, the control pulse 7 on the magnetic tape (not shown) is set to the control pulse, and the magnetic tape is reproduced by pressing the control pulse 7 on the top of the magnetic tape (not shown).

This control pulse 7 passes through an amplifier 2 and a waveform shaping circuit 5 and becomes a thin pulse signal 8.

This signal 8 is input to the control pulse period measuring circuit 4 at the next stage. The period measuring circuit 4 measures the period of the control pulse, and sends the information to the mode determining circuit 5 for each measurement, and the mode is determined to be one of 5PXLPXSLP. For example, when playing an SP recording tape, SP signal 9 is %H#, and when LP signal 10 is %L#, S
The LP signal 11 is set to be SLl.

Assume that the playback tape has now changed from the SLP mode to the SP mode. The control pulse (hereinafter abbreviated as CTLP) period played back from the tape is recorded at the SP speed and 90 TLP is played back at the SLP mode speed.
For example, the cycle changes three times. Therefore, the information of the period measurement circuit 4 changes, and the mode display output of the discrimination circuit 5 changes accordingly. In other words, the SP signal 9 is
T(#K, S L P signal 11 ka 'H' color becomes 'L' and SP is displayed.

Since the CTLP cycle also changes when the SLP part is played back during SP playback or when the KLP part is played back during SLP playback, each mode is discriminated by the mode discrimination circuit 5 based on the CTLP cycle.

Assume that the discrimination output has now changed from SLP to SP. On the other hand, the speed control system works to change the tape speed from SLP to SPK, but since sudden speed changes cannot be made, the playback C
The TLP cycle gradually changes to a normal cycle. At the time of this change, the output of the period measuring circuit 4 is transferred to the mode discriminating circuit 5.
, it may be determined that the mode is other than SP depending on the CTLP cycle.

For example, if the LP mode is determined, the speed control system 4
Works as LP mode. However, since the tape is reproducing the SP recorded portion, it is determined that the tape is not SP, and the speed control system operates in SP mode.

Tsumu v1 Even though it is initially determined to be SP from SLP, it may be mistakenly determined to be LP mode midway through. If this malfunction occurs, the tape speed will not change smoothly.
Not only does it take a long time to settle down to the SP speed, but there are other inconveniences such as the playback screen being distorted. Therefore, when the mode is switched, the mode is prevented from changing for a certain period of time. In other words, when switching modes, the bird outputs the signal 12 and drives the time constant circuit 6 consisting of a counter or monomulti, and its output signal 15 controls the CTLP period measuring circuit 4 for a certain period (T). It is stopped to prevent mode changes from occurring. As a result, the mode can be smoothly switched without causing any malfunction even when the tape feeding speed changes in accordance with the mode change. However, in the method of using this time constant circuit 6 to prevent mode detection for a certain period of time, even if the tape feeding speed responds quickly and reaches a predetermined speed,
Since mode detection is stopped, it cannot be determined even if playback of a recorded portion in a mode other than SP recording starts at that time, resulting in a disadvantage that speed switching is delayed. in particular,
If there is an unerased portion of the SP recorded for a minute period or an overlap of CTLP in the transition from SLP to LP, there is a drawback that such a malfunction occurs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a tape speed determination circuit for a magnetic recording/reproducing apparatus that eliminates the drawbacks of the prior art described above and operates stably and quickly even when switching recording modes.

The main focus of the present invention is that when the speed control circuit for the capstan drive motor is outside the variable control range corresponding to the tape recording mode that has already been determined, the discrimination mode is maintained, and after the speed control circuit is within the variable control range, the automatic discrimination circuit is operated. It's in the point where you let it happen.

An embodiment of the present invention will be described below with reference to FIG. Third
In the figure, parts having functions similar to those in FIG. 1 are numbered the same. In the figure, 16 is a capstan;
18 is an amplifier, 19 is a motor drive circuit, 20 is a speed control circuit, 21 is a waveform shaping circuit, 22 is a counter, 24 is a latch circuit, and 25 is a 5P1 obtained from the mode discrimination circuit 5.
A decoder circuit processes information of the latch circuit using LP and SLP signals, and 26 is an output circuit that outputs a signal from the decoder circuit 25.

Next, the operation will be explained.

Pulse generating means 15 attached to capstan 16
A pulse detector 17 obtains a signal having an integral multiple of the rotational speed of the capstan 16, and this signal passes through an amplifier 18 and becomes a capstan signal 28. The capstan signal 28 is
It is a frequency and voltage converter.

The output is input to the speed control circuit 20, and the output thereof is input to the capstan motor drive circuit 19 at the next stage.

These constitute a normal speed control loop and control the motor so that the frequency of the capstan signal 28 becomes a predetermined frequency. This allows the capstan 16 to be kept at a constant rotational speed, allowing stable tape running.

5 Regardless of the PXLP and SLP status K, the control pulse signal 7 to be reproduced is one of the TV transmission and reception methods N.
In the case of TSC, it is 50Hz. (The NTSC mode will be explained below.) On the other hand, the tape speeds are SP, LP, and SLP and have an integer ratio relationship.

For example, set the SLPLP recording speed to 1/3 of the SP state.
, if the tape speed for LP recording is half that of the SP state, it is necessary to send the tape at the respective tape speeds for reproduction special transmissions. For this reason, the rotation speed of the capstan 16 is also 1 at the time of SP at the time of SLP.
/3, and 1/2 during LP. Therefore, the capstan signal 28 has a frequency ratio of 6:3:2 at 82 o'clock, LP time, and SLP time. This capstan speed is
The speed control circuit 20 controls the speed to a predetermined mode speed.

An example of speed control will be explained with reference to FIG.

The capstan signal 28 is input to the waveform shaping circuit 21 and sent to the Callan table 22 and the latch circuit 24. The counter 22 contains the black that passed through the AND gate 25.

After the counter 22 is reset by the signal 29, the counter 22 starts counting. After one cycle of the signal 28, the counting information of the callan 4122 is transferred to the latch circuit 24 by the signal 31, and is held until the next signal 31 is input. As soon as the signal 61 is output, the reset signal 29
is output, and the callan 422 restarts after being reset. By repeating this operation, the capstan signal 2
8 one cycle period is counted by a clock, and the information is held in the latch circuit every cycle.

The information transferred and held in the child circuit 24 is input to the decoder circuit 25, processed, and input to the motor drive circuit 19 through the output circuit 26. As shown in FIG. 4A, when the capstan signal 28 input to the speed control circuit 20 matches the predetermined mode frequency (coincides with the predetermined tape speed), it is within the control variable range. The output signal 32 of the speed control circuit 20 has a potential in the middle of the output amplitude. Now, if the speed of the motor is slowed down due to the addition of a load, etc., the frequency of the capstan signal 28 will drop (state B in FIG. 4). At this time, the black signal 50 input to the counter 22 increases during the signal 29O period. Therefore, the count information of the counter 22 increases. After this counting information is transferred and held in the slave circuit 24, the output signal 32 increases according to the amount of information, increasing the motor rotation. When the capstan rotational speed is faster than a predetermined value, the opposite is true, the count information of the counter 22 becomes small, the control output signal 62 of the speed control circuit 20 decreases, and the motor rotational speed is reduced. As shown in Figure 5, in a normal speed control circuit, the output control variable range is within a small range with respect to a predetermined control frequency (fo). If the potential is slow, the output is fixed at the highest potential.

In other words, the capstan signal 28 is (fo±Δf)(7)
Within the range, the output signal 32 varies according to the frequency of the signal 28, but outside the range (h±Δf) the output voltage is fixed. This is to increase control sensitivity and perform stable speed control. Note that this k is 5PXLP, SL
Each P is different.

In the present invention, we use this feature of the speed control circuit to
The tape speed determination circuit is designed to operate only when the speed is within the range of ±Δf).

In other words, if the capstan signal from the speed control circuit 20 is around the frequency of the predetermined mode [that is, (h sat △f
)%H# if it is within the range, and 1Ll if it deviates from around the predetermined frequency.

The signal 13 is taken out and the operation of the CTLP period measuring circuit is turned on and off accordingly.

An embodiment of the method of generating the signal 13 will be explained with reference to FIG. Components in FIG. 6 that have the same functions as those in FIGS. 1 and 3 are given the same numbers.

In the figure, 40 is an AND gate, 59.41 is an inverter 4, 42 is a decoder circuit that processes the signal from the latch 24, and 45.44 is a switch that controls the control output signal 32 according to the information from the latch 24. In the circuit, 45 is a power supply set to the lowest potential of the output signal 32, and 46 is a power supply set to the highest potential of the signal 52. 6 in Figure 7
The main waveforms of the figure are shown.

When the signal 2 is input to the waveform shaping circuit 21, the latch signal 5
1 and a reset signal is output, and the callan 4122 starts counting. When Qn goes from SLl to %HIK after inputting d, black, and cursor 422, the output of AND gate 23 becomes 1Ll, stopping counting and maintaining that state. In addition,
Count value of counter 22 at Q+-Qn-+ 1, Q1~
The count value of Qn-2 changes as shown in FIG.

In this example, within the variable control range of the speed control system (h±△f
) is set in the D part, and in other ranges, the control output signal 52Vi maximum level 1/! or lowest potential 1
It is fixed at /1.

Whether or not it is within this variable control range is determined based on the information of Qyl-z, Qn-+, and Qn of the counter 22. That is, when the latch signal 31 is output from the waveform shaping circuit 21, the count information of the counter 22 at that time is transferred to the latch circuit 24 and held. The held information is input to the decoder circuit 25, but Qn-2 of the child circuit 24
, Qn-+, and Qn, it is determined whether the speed is within the variable control range, faster or slower.

If within the variable control range, signal 49 becomes 'H'% signal 50
is 'H'N signal 51 times SLl, so signal 1S is 'H'
'S signal 48 becomes tH'. At this time, switch 43 is a
Since the switch 44 is connected to the d contact, the signal 32 is the same as the output of the decoder circuit. Outside the variable control range, the signal 15 becomes SLl. If the motor is rotating fast at that time, the signal 48 is 1Hl, so
The switch 45 is connected to the contact point d, but the switch 43
is connected to contact b, so the output signal 32 is fixed at the lowest potential and acts to slow down the rotation of the motor. Also, if the motor rotation is too slow, the signal 51 is 'H'% signal 4
8 becomes SL1, the switch 44 is connected to the contact point C, and the output signal 32 is fixed at the highest potential.

That is, depending on the output timing of the latch signal 31 after the counter 22 starts, the output signal 52 changes as shown in FIG. 7, and the motor rotational speed is controlled to a predetermined frequency.

Note that if the child signal 31 is output at the timing shown in FIG. 17C, the control output signal 32 outputs a potential in the middle of the output amplitude. The signal 13 is %H' in the range shown in the seventh diagram, which is within the variable control range, and is SL1 in other areas.

Suppose now that a tape recorded with SLP is being played back at SLP speed (the predetermined capstan signal frequency of SLP is assumed to be fost, p). At this time, since it is within the control variable range, the signal 13 obtained from the speed control circuit 20 is 1H#, and the automatic speed discrimination circuit is operating. Suppose now that the mode recorded on the tape has changed from SLP to SP. Since the tape feed speed remains at SLP, the CTLP frequency played back is 10Hz instead of the original 50Hz.
becomes. When this CTLP with a long period is input to the CTLP period measuring circuit 4, the information is input to the mode determining circuit 5 and it is determined that the mode is SP mode.

The mode discrimination output is input to the speed control circuit 20, and the S
Changes from LP to SP mode. At this time, the predetermined frequency of SP is fosp, which is three times the frequency of foSLP, so
If it is outside the variable control range, the signal 13 will be %LI. When the signal 15 reaches %L1, the CTLP cycle measuring circuit 4 is turned off and the output of the mode determining circuit 5 is fixed at SP.

On the other hand, in the speed control circuit 20, the capstan signal 28 is f6
sp and increases the motor rotation speed.

When the motor rotation speed increases and rises to within the control variable range of speed control, that is, the capstan signal 28 becomes f.
When the frequency is around o8P, the signal 15 becomes 1Hl, the CTLP period measurement circuit 4 is turned on, and the automatic speed detection circuit is activated.

Operations such as from SLP to LP and from SP to SLP are performed in the same manner.

As described above, it is possible to use the output of the speed control circuit, so that even if the recording speed has changed slightly or there are unerased areas, the speed control circuit can keep the tape at a speed that responds. In the past, if the mode was changed once the speed was determined, the screen would be distorted for a certain period of time, but this does not occur with the method of the present invention.

Although the above explanation has been made using a digital speed control circuit, since an analog speed control circuit also has a variable control range, the automatic discrimination circuit can be configured in a similar manner.

According to the present invention, the first speed detection circuit operates as soon as the playback tape speed rises to the already detected tape speed mode, so even when the tape recording mode changes frequently, the state can be well and quickly determined, and the recording tape speed can be quickly detected. Can determine speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a tape speed determination circuit of a magnetic recording/reproducing apparatus in the prior art, FIG. 2 is a waveform diagram of a main part explaining the operation of FIG. 1, and FIG. 3 is a diagram showing an embodiment of the present invention. The circuit diagram, FIG. 4 is a waveform diagram of the main part of FIG. 6, and FIG. 5 is an operational diagram showing the variable control range of the speed control circuit shown in FIG.
The figure is an embodiment diagram of the main part of FIG. 5, and FIG. 7 is a waveform diagram thereof. DESCRIPTION OF SYMBOLS 1... Control head, 4... Control pulse frequency Xll measurement circuit, 5...
...Mode discrimination circuit, 6...Time constant circuit, 16...Capstan, 20...Speed control circuit, 25...Decoder circuit. O 1 Concave O 2 Fig. O 3 Fig. 4YJ O 5 Fig. 4 YJ O 5 Fig. 4 Dimensions '7 Fig. D Possible mouth #within range

Claims (1)

[Claims] 1. A magnetic recording and reproducing device that reproduces data at a reproduction tape speed corresponding to the tape speed during recording, which includes a control recorded on a magnetic tape, a detector for detecting pulses, a drive means for running the recording tape, and a drive means for running the recording tape. The speed control means controls the rotation speed of the drive means to a predetermined rotation speed, and the speed control means detects that the drive means has risen to around the predetermined rotation speed, and when this detection signal is output, the tape 1. A tape speed determination circuit for a magnetic recording/reproducing device, characterized in that the circuit is configured to determine or hold the recording speed of a magnetic recording/reproducing device.