JPS58179915A - Magnetic recording medium - Google Patents

Magnetic recording medium

Info

Publication number
JPS58179915A
JPS58179915A JP5315783A JP5315783A JPS58179915A JP S58179915 A JPS58179915 A JP S58179915A JP 5315783 A JP5315783 A JP 5315783A JP 5315783 A JP5315783 A JP 5315783A JP S58179915 A JPS58179915 A JP S58179915A
Authority
JP
Japan
Prior art keywords
signal
data
staircase wave
staircase
wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5315783A
Other languages
Japanese (ja)
Inventor
Takaharu Maruoka
丸岡 高晴
Seiji Toyohara
豊原 生次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KINKI KEISOKKI KK
Original Assignee
KINKI KEISOKKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KINKI KEISOKKI KK filed Critical KINKI KEISOKKI KK
Priority to JP5315783A priority Critical patent/JPS58179915A/en
Publication of JPS58179915A publication Critical patent/JPS58179915A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10046Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10194Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using predistortion during writing

Abstract

PURPOSE:To increase greatly the recording density of a data recorder/reproducer, by using a staircase wave generating circuit to convert a digital data into a staircase wave having a modulated period and then to record it to a recording medium. CONSTITUTION:The staircase waves of different periods in accordance with 1 or 0 of the signal at a terminal Q which is obtained by latching a data signal (a) by a latching circuit 11. In other words, the half period T of the staircase wave is short and long when the data (a) is set at 0 and 1 respectively. Then the staircase wave is recorded on a magnetic tape 3 by a tape recorder 7. In the reproduction mode, an output signal (c) is supplied to a buffer 14 of a comparator 5. At the same time, the top or bottom point of the signal (c) is held by the values of a diode and a capacitor. Then the amplitude center potential of the signal emerges at a capacitor C4 through a resistance. An operational amplifier 15 compares the signal with its amplitude center to extract a square wave (d) which has a short period to a signal 0 and a long period to a signal 1 respectively. Thus, the recording density is greatly increased.

Description

【発明の詳細な説明】 この発明は、ディジタルデータを特殊な形式で記憶した
磁気記録媒体に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording medium that stores digital data in a special format.

周知の如く、磁気テープへのディジタルデータの記録方
式としては、位相変調方式が主として採用されており、
その記録密度は32ピツ)/ll1m。
As is well known, the phase modulation method is mainly used to record digital data on magnetic tape.
Its recording density is 32 pits)/ll1m.

又は64ピツ)/nu++が現状である。or 64 pits)/nu++ is the current situation.

この発明の主たる目的はかかる記録密度を大幅に増大せ
んとするものである。
The main object of this invention is to significantly increase such recording density.

即ち、この発明は入力さhるディジタルデータaを階段
波発生回路1によって第3図(a)に示す如くの周期変
調された階段波に変換した信号を記録した記録媒体を提
供せんとするものである。
That is, the present invention aims to provide a recording medium in which a signal obtained by converting input digital data a into a periodically modulated staircase wave as shown in FIG. 3(a) by a staircase wave generating circuit 1 is recorded. It is.

かかる階段波に変調して記録されたデータ信号を読み出
して得られた信号は第3図(b)の如く周期変波された
正弦波に近い波形であり、その振幅中心と比較して第3
図(c)の方形波を得るための振幅中心を求めるのが容
易になるよう振幅変動が非常に少ない階段波を決定され
ねばならない。
The signal obtained by reading out the data signal modulated into such a staircase wave has a waveform close to a periodically varied sine wave as shown in FIG.
A staircase wave with very small amplitude fluctuations must be determined so that it is easy to find the amplitude center to obtain the square wave shown in Figure (c).

従って第3図(a)で示す階段波は、正弦波を近似する
形が理想的であり、又位相の遅れも考慮して周期を変え
る時点を進ませておくことが望ましい。階段波を記録し
ても(b)の正弦波の如く滑らかになるのは例えばテー
プレコーダ等の記録装置の連断周波数に近い所で動作さ
せているからである。
Therefore, the staircase wave shown in FIG. 3(a) ideally has a shape that approximates a sine wave, and it is also desirable to advance the point in time at which the period is changed, taking into account the phase delay. Even if a staircase wave is recorded, it becomes smooth like the sine wave in (b) because it is operated at a frequency close to the continuous frequency of a recording device such as a tape recorder.

次に第1図に示す如く、本発明装置の一例を具体的に述
べると、1は前述した如くの階段波を得るための階段波
発生回路、2は増幅器、3は磁気テープ、4は同じく増
幅器、5は読み出された信号を振幅中心で比較する比較
回路、6は周期判読及び復号回路で、7はテープレコー
ダを示している。又、aは記録すべきデータ信号、bは
第3図(a)で示す階段波、Cは第3図(b)で示す再
生波、dは同じく第3図(c)で示す方形波、eは読み
出されたデータを示すものである。
Next, as shown in FIG. 1, to specifically describe an example of the apparatus of the present invention, 1 is a staircase wave generation circuit for obtaining the staircase wave as described above, 2 is an amplifier, 3 is a magnetic tape, and 4 is the same. 5 is a comparison circuit that compares the read signals at the center of their amplitude; 6 is a period reading and decoding circuit; and 7 is a tape recorder. Further, a is a data signal to be recorded, b is a staircase wave shown in FIG. 3(a), C is a reproduced wave shown in FIG. 3(b), and d is a square wave similarly shown in FIG. 3(c). e indicates read data.

階段波発生回路1はクロックパルスepの入力端子CI
及びリセット端子R及び出力端子TI、T2・・・・・
・T6(シフト方向はT1からT6の方向)を備えたシ
フトレジスタ8と、切り換え入力端子01,02,03
及びデータ入力端子UO。
The staircase wave generation circuit 1 has an input terminal CI for the clock pulse ep.
and reset terminal R and output terminal TI, T2...
・Shift register 8 equipped with T6 (shift direction is from T1 to T6) and switching input terminals 01, 02, 03
and data input terminal UO.

Ul、C2・・・・・・C7及び出力端子OUTを具備
したデータセレクタ9と、このデータセレクタ9の出力
端子OUTからの入力端子IN及び出力端子Vl、V2
.V3を有するカウンタ10と、端子Wの値を端子Xに
印加される信号の立上がりでラッチするデータ・ラッチ
回路11と、カウンタ10の出力端子Vl、V2に接続
された否定入力のAND回路と、カウンタ10の出力端
子V2゜■3に接続されtこ排他オア回路EORIと、
カウンタ10の出力端子Vl、V3に接続された排他オ
ア回路FOR2と、各排他オア回路EORI。
A data selector 9 equipped with Ul, C2...C7 and an output terminal OUT, an input terminal IN from the output terminal OUT of this data selector 9, and output terminals Vl, V2.
.. A counter 10 having a voltage V3, a data latch circuit 11 that latches the value of a terminal W at the rising edge of a signal applied to a terminal X, and an AND circuit with a negative input connected to the output terminals Vl and V2 of the counter 10 an exclusive OR circuit EORI connected to the output terminal V2゜3 of the counter 10;
An exclusive OR circuit FOR2 connected to output terminals Vl and V3 of the counter 10, and each exclusive OR circuit EORI.

FOR2の各出力をダイオードDI、D2・・・・・・
D4の順方向電位差でクランプするクランプ回路12と
更に抵抗R4及びR5の比が1:2に選んで構成された
ディジタルアナログ変換器13とから構成されている。
Each output of FOR2 is connected to a diode DI, D2...
It is comprised of a clamp circuit 12 that clamps by the forward potential difference of D4, and a digital-to-analog converter 13 configured by selecting resistors R4 and R5 at a ratio of 1:2.

データセレクタ9は入力端子01がOであるときはカウ
ンタ10の端子Vl、V2の値にしたがってデータ入力
端子UO〜U3のいずれかと出力端子OUTとが接続さ
れ、入力端子01が1であると外は、同様にカウンタ1
0の端子Vl、V2の値にしたがってデータ入力端子U
4〜U7のいずれかと出力端子OUTとが接続される。
In the data selector 9, when the input terminal 01 is O, one of the data input terminals UO to U3 is connected to the output terminal OUT according to the values of the terminals Vl and V2 of the counter 10, and when the input terminal 01 is 1, the output terminal OUT is connected. Similarly, counter 1
Data input terminal U according to the values of terminals Vl and V2 of 0
Any one of 4 to U7 is connected to the output terminal OUT.

振幅中心で比較する比較器5はバッファー増幅器14及
びダイオードD5.D6.D7.D8、抵抗R7,R8
,R9、コンデンサC2,C3,C4及び演算増幅器1
5から構成され信号Cを入力し信号dを、出力する。
Comparator 5, which compares at the center of amplitude, includes a buffer amplifier 14 and a diode D5. D6. D7. D8, resistance R7, R8
, R9, capacitors C2, C3, C4 and operational amplifier 1
5, which inputs signal C and outputs signal d.

かかる階段波発生回路等の動作説明を第2図の波形図を
参考に述べる。
The operation of such a staircase wave generating circuit will be described with reference to the waveform diagram in FIG. 2.

先ず最初カウンタ10の出力端子Vl、V2.V3の信
号が(1,0,0)であるとする。データラッチ11の
出力端子Qの信号がOであるときは、データセレクタ9
の出力端子OUTにはデータ入力端子U1からの信号が
出力される。又、このデータ入力端子U1はシフトレジ
スタ8の出力端子T3と結ばれているので、クロックパ
ルスCPが端子c4に3回入力したとき、データセレク
タ9の出力端子OUTから信号が出力され、抵抗R1及
びコンデンサC】から成る遅延回路を通してシフトレジ
スタ8のリセット端子Rに人力される。この時シフトレ
ジスタ8はリセットされて全ての出力はなくなる。この
ようにクロックパルスCPより幅の狭い信号をデータセ
レクタ9の出力端子OUTから取り出せる。データセレ
クタ9の出力端子OUTの信号がなくなる時点でカウン
タ10の出力端子Vl、V2.V3の信号は(0,1,
0)へと変化していく。
First, the output terminals Vl, V2 . Assume that the signal of V3 is (1, 0, 0). When the signal at the output terminal Q of the data latch 11 is O, the data selector 9
A signal from the data input terminal U1 is outputted to the output terminal OUT of the data input terminal U1. Also, since this data input terminal U1 is connected to the output terminal T3 of the shift register 8, when the clock pulse CP is input to the terminal c4 three times, a signal is output from the output terminal OUT of the data selector 9, and the resistor R1 and a capacitor C] to the reset terminal R of the shift register 8. At this time, the shift register 8 is reset and all outputs disappear. In this way, a signal narrower in width than the clock pulse CP can be extracted from the output terminal OUT of the data selector 9. When the signal at the output terminal OUT of the data selector 9 disappears, the output terminals Vl, V2 . The signal of V3 is (0, 1,
0).

こうなると、データセレクタ9の出力端子OUTはデー
タ入力端子U2と接続されることになり、以下同様にシ
フトレジスタ8とデータセレクタ9との間の結線により
決定される時間毎にデータセレクタ9の出力端子OUT
からカウンタ10を進める信号が取り出される。
In this case, the output terminal OUT of the data selector 9 will be connected to the data input terminal U2, and the output terminal of the data selector 9 will be connected to the data input terminal U2 at intervals of time determined by the connection between the shift register 8 and the data selector 9. Terminal OUT
A signal is taken from which advances the counter 10.

階段波発生回路1におけるカウンタ10の出力端子Vl
、V2で階段波の4つの段を表わすことになり、従って
その入力端子INから信号が入るごとに、この回路1の
出力信号すのレベルが階段状に変化していく。ここでV
l、V2.V3の各信号がV1=1.V2=1.V3=
x(x=0又は1)の場合と、V1=0.V2=O,V
3=xの場合とでは、出力信号すの値は等しく、この場
合だけ同じ段のところに留まることになる。即ち、カウ
ンタ10の入力端子INから信号が8回入力されると、
ディジタルアナログ変換器13の出力端子即ち信号すの
出力端から一周期分の階段波が得られる。
Output terminal Vl of counter 10 in staircase wave generation circuit 1
, V2 represent four steps of a staircase wave, and therefore, each time a signal is input from the input terminal IN, the level of the output signal S of this circuit 1 changes in a stepwise manner. Here V
l, V2. Each signal of V3 is V1=1. V2=1. V3=
x (x=0 or 1) and V1=0. V2=O,V
In the case of 3=x, the value of the output signal S is the same, and only in this case it stays at the same stage. That is, when a signal is input eight times from the input terminal IN of the counter 10,
A staircase wave for one cycle is obtained from the output terminal of the digital-to-analog converter 13, that is, the output terminal of the signal.

上記階段波は第3図(、)に示すように、振幅が基準値
から最大値に向って順次増加し、最大値から基準値に向
って減少する波形を有す、る。
As shown in FIG. 3, the staircase wave has a waveform in which the amplitude sequentially increases from the reference value to the maximum value and decreases from the maximum value to the reference value.

シフトレジスタ8はタイマーの役割をなし、階段波の各
段の時間の基準となり、データセレクタ9はその各段に
よってデータ入力端子UO,Ul・・・・・・U7とシ
フトレジスタ8の出力端子TI、T2・・・・・・T6
の間を結線するものである。
The shift register 8 plays the role of a timer and serves as a time reference for each stage of the staircase wave, and the data selector 9 uses the data input terminals UO, Ul...U7 and the output terminal TI of the shift register 8 according to each stage. , T2...T6
It connects between.

従って、Cρ端子に加えられる信号によりデータ入力端
子UO,01・・・・・・U3又はU4・・・・・・U
7の組み合わせが切り換えられるので、データaをラッ
チ回路11でラッチした端子Qの信号力弓であるかOで
あるかによって別の周期の階段波を選択でとる。即ち、
この実施例ではデータaが0であるときは階段波の半周
期Tは短かく、a が1のときはTは長くなる。この階
段波は増幅器2を介してテープレコーダ7により磁気テ
ープ3に記録される。
Therefore, depending on the signal applied to the Cρ terminal, the data input terminals UO, 01...U3 or U4...U
Since the combinations of 7 can be switched, a staircase wave with a different period can be selected depending on whether the signal power of the terminal Q or O, which is latched by the latch circuit 11, is the signal power of the data a. That is,
In this embodiment, when data a is 0, the half period T of the staircase wave is short, and when a is 1, T is long. This staircase wave is recorded on the magnetic tape 3 by the tape recorder 7 via the amplifier 2.

次に磁気テープ3の再生時において、増幅器4を介して
読み出された信号Cは比較器8におけるパンファー増幅
器14に入力して増幅されると共に、ダイオードD5及
びコンデンサC2で信号の山の頂点が保持され、ダイオ
ードD6とコンデンサC8で信号の谷の頂点が保持され
る。
Next, when reproducing the magnetic tape 3, the signal C read out via the amplifier 4 is input to the amplifier amplifier 14 in the comparator 8 and amplified, and the peak of the signal is reached by the diode D5 and capacitor C2. The peak of the signal valley is held by diode D6 and capacitor C8.

そこで抵抗R8及びR9を通してコンデンサC4には信
号の振幅中心の電位があられれ、演算増幅器15におい
て信号と、その振幅中心が比較され第3図(c)に示す
如く信号0に対しては周期が短かく、信号1に対しては
周期の長い方形波dが取り出される。
Therefore, the potential at the center of the amplitude of the signal is applied to the capacitor C4 through the resistors R8 and R9, and the operational amplifier 15 compares the signal and the center of its amplitude. For signal 1, a short square wave d with a long period is extracted.

尚ダイオードD?、D8は演算増幅器15の出力が飽和
しないように挿入されたものである。
Also diode D? , D8 are inserted to prevent the output of the operational amplifier 15 from being saturated.

〈実施例〉 第1図で示すクロックパルス発生器cpから1/6MH
zの信号を入力してテープレコーダ7にテープ速度48
cm/秒を用いたところ、階段波の半周期で1ビツトの
データを記録することによって、データ「0」に対して
は半周期が66μ秒、データ「1」に対しては半周期が
90μ秒になった。従って記録密度が粗な場合でも 以上の如く、本発明の記録媒体によれば従来の3倍以上
の記録密度が得られることになる。
<Example> 1/6MH from the clock pulse generator cp shown in Fig. 1
Input the z signal to the tape recorder 7 to set the tape speed to 48.
When cm/second is used, by recording one bit of data in a half period of the staircase wave, the half period is 66 μs for data “0” and 90 μs for data “1”. It's now seconds. Therefore, even when the recording density is low, as described above, the recording medium of the present invention can provide a recording density three times or more higher than that of the conventional recording medium.

また本発明によれば千O」か「1」かの判別は再生波の
ゼロクロス点(基準線と交さする点)間の長さで判別で
きるので、テープレコーダのワウ7ラツク等の影響を受
けることがなく良好なデイノタルデータの記録、再生か
行なえる。
Furthermore, according to the present invention, it is possible to determine whether the wave is ``1,000'' or ``1'' by the length between the zero-crossing points (points that intersect with the reference line) of the reproduced wave, thereby eliminating the influence of the tape recorder's wah, 7, etc. Good data recording and playback can be performed without any interference.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一例を示すブロックダイヤグラム、第
2図はその要部の信号波形図、第3図(a)(b)(e
)は第1図主要部の出力信号波形である。 1・・・階段波発生回路、2,4・・・増幅器、3・・
・磁気テープ、5・・・振幅中心で比較する比較器、6
・・・周期判読及び復号回路、7・・・テープレコーダ
。 特許出願人  近畿計測器株式会社 代理人 弁理士青白 葆外2名 第2図 第3図 (a) (b) (C)
Fig. 1 is a block diagram showing an example of the present invention, Fig. 2 is a signal waveform diagram of the main part thereof, and Fig. 3 (a), (b) (e
) is the output signal waveform of the main part in FIG. 1... Staircase wave generation circuit, 2, 4... Amplifier, 3...
・Magnetic tape, 5... Comparator that compares at the center of amplitude, 6
... Periodic reading and decoding circuit, 7... Tape recorder. Patent Applicant: Kinki Keikokuki Co., Ltd. Agent: Patent Attorneys: Seihaku and Sogai (2 persons) Figure 2 Figure 3 (a) (b) (C)

Claims (1)

【特許請求の範囲】[Claims] (1)2値レベルの信号の各信号レベルに対応した異な
る周期をもち、かつ各周期内で、振幅が基準値から最大
値に向って順次階段状に増加し、最大値から基準値に向
って減少する少なくとも1/2周期を有する階段波を入
力信号として記録したことを特徴とする記録媒体。
(1) A binary level signal has a different period corresponding to each signal level, and within each period, the amplitude increases stepwise from the reference value to the maximum value, and from the maximum value to the reference value. 1. A recording medium, characterized in that a staircase wave having at least 1/2 cycle that decreases as an input signal is recorded.
JP5315783A 1983-03-28 1983-03-28 Magnetic recording medium Pending JPS58179915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5315783A JPS58179915A (en) 1983-03-28 1983-03-28 Magnetic recording medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5315783A JPS58179915A (en) 1983-03-28 1983-03-28 Magnetic recording medium

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP15397278A Division JPS5577018A (en) 1978-12-01 1978-12-01 Magnetic recording device

Publications (1)

Publication Number Publication Date
JPS58179915A true JPS58179915A (en) 1983-10-21

Family

ID=12935007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5315783A Pending JPS58179915A (en) 1983-03-28 1983-03-28 Magnetic recording medium

Country Status (1)

Country Link
JP (1) JPS58179915A (en)

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