JPS58179025A - Inverting circuit - Google Patents

Abstract

PURPOSE:To control the threshold value from outside, by varying the supply voltage of the inverting part of an input signal by the control voltage and furthermore shifting the output level of said inverting part up to the level of the power supply voltage. CONSTITUTION:A P channel enhancement type FETQ1 and Q6 decide the voltage at a point A by means of an FET which varies the threshold value of circuit and the currents flowing to the FETQ1 and Q6 themselves. The P channel FETQ2 and Q5 have the threshold value respectively. If the potential of the power supply VDD side which is higher than the threshold value of circuit is applied to an input VIN, the FETQ2 is turned on. However the potential of a point B does not reach that of a power supply VSS and then floats up. This floating potential is compensated by FETQ3 and Q4, and a level near VSS is delivered to the output VOUT.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is particularly directed to an enhancement-type field effect transistor total driver, and is directed to a full driver of enhancement type field effect transistors. The present invention relates to an inverting circuit whose load is a field-effect transistor.

An enhancement type field effect transistor (hereinafter referred to as field effect transistor 't-FET) is used as a driver,
Conventional inverting tg with depre, syn type FET k load
The I connection is drawn in Figure 1.0, that is. 1 is an enhancement type FET, the input signal vIN is applied to its gate 81, and this drain is an enhancement type FET. 'through v
DDl [output voltage V as it is fitted into the shaft. UT is given 9. The circuit-1 voltage vTC of this circuit can generally be expressed by the following equation: Ov,,=v? I-,,Il/βlI
TTO here Th V7m is Enhancement Men F1FE
T+ #am1111 pressure S v? D is tee 7L' w
V m 7 type F E Tl single value output, β1 is the enhancement member} WFWTI channel conductance β1 and depression, shi.

is the ratio of the channel conductance β of the channel ffi F jE T *.

β1=β, /β. In addition, the channel conductance β is well-known in transistor integrated circuit devices (
Hereafter referred to as IC (O).

When constructing a circuit t using a number of inverting devices, it is possible to construct a circuit t, or to construct an analog-to-digital converter t″?S. Conventionally, this type of V
Tc′frTo be different from other inverting circuits, β1 and β! The hito, which is β8, was shaken by 1 and it was ``TCC gold brother''.

FIG. 2 shows an input/output custom-made example t of the conventional example in FIG. 1 when β1 is varied in this way. The characteristics in Figure 2 are VDD=-
17V *Vals=Ov*V,,=-2,3￥
b and V, D=-4-6,9V, and the following case.

As is clear from this, when βBk is made smaller, the βt of the enhancement type FET becomes unstable.

Since β of Shindanff1FETl is equally important, the output potential changes from V□ side to vDD@, and conversely, vDf,
The weir transition area that moves from the side to the vas side becomes wide.

Furthermore, even if the enhancement type FET is turned on, if the β-breathing is reduced to a level equal to the β weight, the V0 level will not appear in the output potential, but will shift from the V2 level to the vDD level. Therefore, the margin against noise becomes small, making it impossible to use it for logic circuits. On the other hand, even if β8 is increased, the changes in v and c are not so large, and therefore the reward for increasing the size of the transistor in order to increase βl is very small.

Moreover, the biggest drawback of this method of turning β1 into tears is that
Since the 凰 is created at the stage when the IC is manufactured, once it is completed in -, it is no longer possible to adjust the ``tc'' completely. In this way, converting β i & v to eK resulted in numerous drawbacks, and design had to be done within the constraints of these drawbacks.

The present invention solves the above drawbacks and allows the circuit w4 value to be freely controlled by an external control voltage. 4Ii, and the output level can swing up to around vIs level.

Below is a detailed explanation of an embodiment using the present invention in Figure 9 #K
152 will be revealed.

The inverting circuit in Figure 3 has five field effect transistors and one load FET, and is a nine inverting circuit. Here h Qt
・Qt ・Ql and Q4 are P-channel enhancement type FETs, Q, and. , P-channel degradation, can be achieved using a single-type FET.

FET Qt and Qs 7-”l'jm @V
fart.

The drains of 8 FETQ, , Ql and FkTQ, are connected to one leaky end of NI#, VD, respectively. Gate and drain of FETQ, gate of FkT-Ql, source of FETQ, and FETQ.

The sources of FETQ4 are connected together and the gates of FETQ4.

Drain of FETQ, and gate of FETQ.

The sources are connected to each other by KW, and the drain of KFETQs and the source of FETQ are connected by tJt-mK.

This is used as an output terminal, and the gate of FETQ is used as an input terminal.The gate of FETQ is used as a control terminal.

Next, the operation of FIG. 3 will be explained. Voltages at points A and B and output voltage V with respect to input voltage v4. t of UT1 inversion circuit
The iI four-value voltage is shown in FIG.

Since pg'rQ1 eQa is a current flowing through s Qt e Qs in the FIT used to slightly change the circuit threshold voltage, the voltage vTC1 at point A can be changed by vcONT. 1+%F FJT Qs -Q
Although the source potential of sFiQ is different, it has the same structure as the conventional example, and if the source potential of Q is used as a reference, the circuit -gILvTct1 is the same. sand! In other words, in Figure 3, the source of Q is V to vTCIm.
V.

-Vtc, ), then the circuit value voltage is V? If you add C, it will be 21W IDIj3J EV. Ha v? C
＝'? C.

+ V? c.

In the example of Fig. 3 with such a potential distribution, if a potential of vl)D@ is applied to the input V□, exceeding the circuit value v, c, then Q is turned on, but B At the point, the potential is not vo, but it is floating by vTcl. To compensate for this, FETQA and Q4 are used.FETQ,
and Q have the same current value flowing through the common gate QllQ#. Therefore, if more stain current flows in Qs due to Qm being turned on, the current in Ql will also increase @For this reason, %Q
By m and Q4, the amount floating by vTC from vss at point B is 1'l[.

If the potential on the v18 side is added, a potential obtained by subtracting the threshold voltage V□ of FETQ from vDD appears at the output.

As described above, according to the third inverting circuit, the circuit value v,, ty14 can be adjusted by the voltage of VCONT, and the output high level is near the V level, and the output low level is from vDDS to v? l It becomes the drawn level. Here, the way of coming out is 0
-It is a concern that the level does not drop at vDDt, but if the output of this embodiment is connected to a general P-channel logic circuit, it is not a serious problem since the general P-channel logic circuit operates based on v8m. It's not a disadvantage @Also. FETQ was an enhancement type here, but it was a dibre.

There is no particular problem even if a line-type FET is used, and VTCtvlmTo is VTCtvlmTo because V is negative in a dipleg type.

level to vDD level.

In this way, according to the present invention, the voltage t-
By changing the circuit threshold voltage, you can freely change the circuit threshold voltage, and you can actually create an inversion circuit that can swing the output high level to around 1kV□! Figure 5 shows another embodiment of the present invention. This is a 2-bit analog-to-digital converter, where Q,' to Q@' + Q
%' to Q,' corresponds to Ql to Q in Figure 3, and the circuit l! I am using Q, //taQma” to change 1fIL・However, Q
Q, ' and Q, ' or Ql to use "y't"
The magnitudes of ' and Qt' may be varied.

In addition, in the third prisoner, Figure 5, FETQt -Qs'Q
t' can be resistance 0

[Brief explanation of the drawing]

Figure 1 shows a conventional embodiment, Figure 2 shows the input/output characteristics of Figure 1, and Figure 3L)! g is a diagram showing one embodiment of the present invention, FIG. 4 is a diagram showing the voltage at each point in the third embodiment, and wJ5 is a circuit diagram showing another embodiment of the present invention. be. l...Enhancement type transistor, 2.
・・・・・・Depreciation type transistor, 3.4・
...Inversion circuit according to the present invention having different circuit threshold voltages, Q...FET. 5S District 1 Figure 2 Figure 3 Figure 1 Figure 4 Figure 5

Claims (1)

[Claims] A signal inverting section that inverts the phase of an input signal, a power supply section that supplies voltage to the signal inverting section according to the applied control voltage, and shifting the output level of the signal inverting section to near the power supply voltage. An inverting circuit characterized by comprising means for.