JPS58178632A - Switching circuit - Google Patents

Abstract

PURPOSE:To reduce the loss of an electric power at the normal time, by breaking a driving current when a load is short-circuited at the 2nd FET of which drain source is connected between the gate sources of FETs used for driving the load. CONSTITUTION:If driving command signal voltage is a low level (0V) when a load 1 is normal, the 1st FET 17 is disconnected and the 2nd FET 19 is connected (since the drain voltage is 0V, the drain current does not flow), so that the load 1 is not driven. When the signal voltage is at high level, the 1st FET 17 is connected and the 2nd FET is disconnected, driving the load 1. When the load 1 is shorted, the same status as the normal time is kept when the signal voltage is at low level. At the high level, the 1st FET 17 is connected, but the gate voltage of the 2nd FET 19 is higher than that of the normal status, so that the FET 19 is connected, the 1st FET 17 is disconnected and load current is interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection circuit for a field effect transistor that controls on and off the current flowing through a load. FIG. A MOS field effect transistor (hereinafter simply referred to as rFETJ) that constitutes a switching means that turns on and off the flowing drive current.
5 is a short-circuit detection resistor with a small resistance value that converts the short-circuit current flowing when the load 1 is short-circuited into a voltage signal;
Comparison 7 compares the voltage signal from the short detection resistor 5 with a predetermined voltage level, and outputs a reset signal when the voltage signal exceeds the predetermined voltage level! ! 9 and a drive signal for the load 1 supplied from the input terminal VIN to control the application of an on signal to the gate terminal of the FET 3;
A control section is shown which includes a drive circuit 11 to which the reset signal is output, particularly a drive circuit 11 that stops application of the on signal. Note that the Voo terminal is a power source for driving load 1 (not shown).
is the terminal to which it is connected.

As a function, when a drive signal for load 1 is supplied to the drive circuit 11 from the VIN terminal, the drive circuit 11
An ON signal of a voltage level sufficient to make the FET 3 conductive is applied to the gate of T3. When FET3 becomes conductive, negative voltage from the vDD terminal? A drive current flows through i11 and the load 1 starts driving. Since the drive current also flows through the short detection resistor 5, the short detection resistor 5 applies a voltage signal to the comparator 19 in accordance with the drive current. Comparator 9' compares the voltage signal with a reference voltage (E) for detecting a short circuit in load 1, but since load 1 never exceeds the reference voltage (E), the reset signal is No output. Therefore, the drive circuit 11 continues to supply the ON signal.

On the other hand, when the load 1 is short-circuited, an excessive current flows through the short-circuit detection resistor 5 from the VOO terminal through the FET 3, so the short-circuit detection resistor 5 outputs a voltage signal corresponding to the excessive current. applied to comparator 9. Since the voltage signal is at a higher level than the reference voltage (E), the comparator 9 supplies a reset signal to the drive circuit. Therefore, the drive circuit 11 stops supplying the ON signal to the gate terminal of the FET 3, thereby rendering the FET 3 non-conductive.

According to this configuration, F constituting the switching means
The terminal voltage of the resistor connected in series with the load via ET is compared with the M quasi-voltage, and when the terminal voltage exceeds the reference voltage due to an excessive drive current flowing when the load is short-circuited, the Since the FET is brought into a non-conductive state, the FET 3 can quickly and reliably cut off the flow of the drive current when the load is short-circuited without being thermally destroyed. On the other hand, current flows through the short-circuit detection resistor even during normal operation, resulting in power loss. Furthermore, when this resistor is integrated, it requires a large area and is difficult to manufacture using an integrated circuit process.
Since it is difficult to integrate the III1 part on the same chip as the FET due to problems in integrated circuit technology, the short detection resistor, comparator, and drive circuit must be installed and wired separately from the FET. The problem is that it is time consuming.

This invention was made in view of the above.↑In order to provide an integrated device that causes no power loss during normal operation and that reliably cuts off the flow of drive current to the load when the load is short-circuited, a first FET whose gate is connected to the parallel connection, whose drain is connected to the load, and whose source is grounded; A second FET is provided, the gate of which is connected to the gate of the FET, the gate of which is connected to the drain of the FET, and the source of which is grounded.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the invention, 13.15
is connected to the input terminal VIN of the drive command signal of load 1,
In addition, the resistor and capacitor 17 connected in parallel have their gates connected to the resistor 13 and capacitor 5, their drains connected to the load 1, and their sources grounded. A first switch constituting a switching means that sometimes interrupts the drive current flowing through the load 1.
The MO8 type FET (hereinafter simply referred to as "first FETJ") 19 has a gate connected to the drain of the first FET 17, a drain connected to the gate of the first FET 17, and a source grounded. a second FET that controls the gate voltage of the first FET l3 according to the state of the load 1;
FET (hereinafter simply referred to as the second FETJ), 21
is a current interrupting element in which the first and second FETs 17 and 19 are integrated into one chip. The resistance value Ri of the resistor 13 is such that when the load is short-circuited, the drain voltage of the second FET 19 becomes smaller than the threshold voltage y th of the first FET. Further, the capacitor 15 is connected to the first FE
It has a sufficiently large capacitance (2) compared to the gate capacitance CG+ of T17 (shown as an equivalent circuit in FIG. 2). Further, the same reference numerals as in FIG. 1 indicate the same parts.

Figure 3 is a characteristic diagram of the first FET, Figure 4 is the characteristic diagram of the second FET.
The characteristic diagrams, Figures 5 and 6, show the operating waveforms when load 1 is operating normally and when it is short-circuited, respectively.
(A> is the drive command signal voltage Vi of load 1, (B
) is the gate voltage Vo+ of the first FET I7, (C) is the drain-source voltage VDS of the first FET I7,
(D) shows the drain current of the first FETI 7, and (E) shows the input terminal Ii from the input terminal VIN.

The operation of this embodiment will be described above with reference to the drawings described above. The drive command signal voltage Vi of the load 1 is, for example, 10 volts when the load 1 is being driven, and O volts when the drive is stopped, and the drive voltage of the load 1 is 1
2 volts, and the resistance R of load 1 is 2.4 ohms.

First, a case where load 1 is normal will be described. When the drive command signal voltage V1 is 0 volts, the effective gate voltage VG+ of the first FET 17 is also 0 volts, so the first FET 17
I7 is in a non-conducting state (point B in FIG. 3). Second F
Since 12 volts of load 1 is applied to ET19, it is in a conductive state, but since the drain voltage VDS2 is O volts, no train current flows (point (a) in FIG. 4). When the drive command voltage V1 becomes 10 volts (Fig. 5 (
A), the input resistance ro due to the drive command voltage vi (as shown in the equivalent circuit diagram in FIG. 2), flows through the gate capacitor CG+, but the resistance value of the gate resistance rGl is extremely small, and the capacitor 15 is sufficiently larger than the gate capacitor CG+, so the first FE
The gate voltage VG+ of TI7 suddenly rises to 1
It reaches 0 volts (see Figure 5(B)). The gate voltage VG1 is the threshold voltage V of the first FET 17.
The first FET 17 begins to conduct at time II exceeding th (after the delay time t dl has elapsed from the rise of the drive command voltage vi), but due to the switching characteristics of the first FET 17, further time When the first F
Since ETI 7 becomes completely conductive, the drain voltage V D S H decreases from 12 volts to 0.5 volts (point (A) in Figure 3), and the drain current 1'D+
becomes a predetermined current value (4° 8 amperes) (Fig. 5 (D)
)reference).

On the other hand, when the drive command voltage V1 becomes 10 volts,
Gate voltage VG2 is 12 volts, drain voltage VD S
2 becomes 10 volts (point d in Fig. 4), the second FET becomes conductive and a drain current of 1 milliampere SE I D 2- flows, but the first FE described above
As the drain voltage vO81 of TI 7 decreases, the gate voltage VG2 also decreases from 12 volts, and when the drain voltage VDSI becomes 0.5 volts, the second F
ET becomes non-conductive (point a in FIG. 4).

Further, regarding the input current 1i, the drive command voltage v1
The current that is the sum of the current that charges the gate capacitor CG+ of the first FET 17 when the gate capacitor CG+ of the first FET 17 is turned on and the current that flows as a drain current when the second FET 19 is turned on flows in a pulsed manner. When becomes conductive, it becomes O ampere.

Therefore, when load 1 is normal, input terminal VIN
When a drive command signal for the load 1 is applied from
Threshold voltage y th of gate voltage VG2 of T,
After the delay time ° [dl and the switching time td2 of the first FET have elapsed,
Since the first FET is in a conductive state and the second FET is in a non-conductive state, a predetermined drive current flows through the load.

Next, a case where the load 1 is short-circuited will be described.

When the drive command signal voltage ■i is O volts, the first FET 17 and the second FET are activated as in the case where the load 1 is normal.
19, no drain current flows in either case. Then, when the drive command signal voltage vi rises to 10 volts, the input current 1i due to the drive command signal voltage vi increases to As a result, the gate voltage VG+ of the first FET 17 reaches 10 volts and the first FET 17 becomes conductive, and a drain current 1iulD+ of 6 amperes flows (point (D) in FIG. 3). However, since load 1 is short-circuited, 12 volts, which is the drive voltage of load 1, is always applied between the drain and source of the first FET 17 (the sixth
(See figure (C)). Further, since 12 volts is also applied to the gate voltage VG2 of the second FET 19, the second FET 19 is always in a conductive state.

On the other hand, the first F which was being charged by the front two input terminals 1i
When the gate capacitor CG+ of ETI 7 is charged up to 10 volts, the drain voltage VDS2 of the second FET 19 decreases according to the load operating line of the second FET 19 due to the resistor 13 connected to the input terminal VIN. Accordingly, the gate voltage VG of the first F-ET17
+ also decreases, and an equilibrium state is reached when the drain voltage VDS2 reaches 1 volt (point (b) in Figure 4).
Similarly, the gate voltage VG+ is also 1 volt, so (
(see FIG. 6(B)), the first FET 17 becomes non-conductive and cuts off the current flowing to the load 1 (see FIG. 6(D>
reference).

In the circuit shown in FIG. 2, the voltage generated in the drive voltage of load 1 due to noise etc. is applied to the second FET 1.
If it is desired to prevent the voltage from being applied to the gate of No. 9, a Zener diode ZD may be connected between the gate and the ground (see FIG. 8, which will be described later). In addition, if it is desired to prevent an excessive current from flowing to the gate of the second FET 19 when the load 1 is short-circuited, the resistance value is appropriately determined based on the allowable current of the second FET 19 and the Zener diode ZD. A resistor Rr having a resistor Rr is connected to the gate and the first
(See FIG. 8, which will be described later).

Next, the current interrupting element 21 connects the first and second F
ETI 7 and ETI 19 are integrated into one chip, and FIG. 7 shows an example of its cross-sectional structure, and FIG. 8 shows an equivalent circuit. In FIG. 7, 23 is the first FE
The substrates 25 and 27 which serve as the drain of T17 are the gate and source of the first FET 17, 29 and 3, respectively.
1.33 is the drain, gate, and source of the second FET 19, and 36 is aluminum (AΩ) constituting the electrode.
) Discipline. Note that the same reference numerals as in FIGS. 1 and 2 indicate the same components.

Next, the structural features of this element will be explained. The sources 27 and 33 of both the first and second FETs 17 and 19 are grounded via the terminal 101, so that the voltage applied to the substrate 23, which is the drain of the first FET (vertical MO8) 17, is Even if the voltage fluctuates, the operation of the drain 29 of the second FET (horizontal MO8) 19 is not affected, and the second FET
Zener diode Z connected to protect ET19
Similarly, there is no problem with the operation of D.

Furthermore, when the first and second FETs 7 and 19 and the Zener diode ZD are formed, there are Although raw diodes 37-1 to 37-3 are formed, they have no effect on circuit operation.In addition, a resistor is used to prevent excessive current from flowing into the gate 31 of the second FET 19 when the load 1 is short-circuited. Rr is silicon dioxide (Si 02
) It can be easily formed using polysilicon resistor on the film 39. Furthermore, first and second guard rings 41-1 and 41-2 are formed (P+
However, if the drive voltage of load 1 is low, the first and second guard rings 41-1 and 41
-2 is not necessary. Also, 43 is Ring Glass (PSG)
II. Furthermore, in FIGS. 2, 7, and 8, 101, 103, and 105 are terminals of the current interrupting element 21.

Therefore, according to the present invention, a device for cutting off the drive current flowing through the load when the load is short-circuited is connected to the parallel connection portion of the resistor and capacitor connected to the terminal for inputting the drive command signal of the load, and a first node having a gate connected to the connection, a drain connected to the load, and a source connected to the ground;
and a current control means that can be integrated by a second FET whose train is connected to the gate of the first FET, whose gate is connected to the drain of the first FET, and whose source is grounded. Therefore, there is no power loss during normal operation of the device for cutting off the driving current, and furthermore, if it is integrated, it can be made smaller.

[Brief explanation of the drawing]

Fig. 1 is a conventional example of a switch circuit, Fig. 2 is an example of a circuit implementing the present invention, Fig. 3 is an operating characteristic diagram of the 10th FET, Fig. 4 is an operating characteristic diagram of the 20th FET, and Fig. 5 is a normal load. 6 is a circuit operation waveform diagram when the load is short-circuited, FIG. 7 is an example of a cross-sectional configuration of an element when this invention is integrated, and FIG. 8 is a diagram of the circuit operation waveform when the load is short-circuited. This is an equivalent circuit of the element. (Explanation of symbols representing the main parts of the diagram) 1...Load
VIN...Input terminal 13...Resistor 15...
Capacitor 17...first FET19...second
FET 21...Current interrupting element patent applicant
Nissan Motor Co., Ltd. Figure 1 Figure 2 Figure 3 Vos+ (V) Figure 4 VDS2 (V) 5110 Figure 6

Claims (1)

[Claims] A terminal for inputting a signal for commanding driving of a load, a parallel connection portion of a resistor and a capacitor connected to the terminal, and a gate connected to the parallel connection portion, a drain connected to the load, and a source grounded. a second field effect transistor having a train connected to the gate of the first field effect transistor, a gate connected to the drain of the first field effect transistor, and a source grounded. A switch circuit characterized by: