JPS58178574A - Input protecting device - Google Patents

Abstract

PURPOSE:To obtain an input protecting device which has strong electrostatic stress by providing aluminum electrode and conductors on an oxidized film of an N type Si substrate, connecting them to the input terminal of an IC and providing a deep P type layer of low density under the connecting pad. CONSTITUTION:An N<+> type layer 4 and a P<+> type layer 3 are provided on an N type substrate 2, and a deep P type layer 7 is formed under the aluminum electrode 1 on an oxidized film 6 and at the connecting part 5. When a large negative voltage is applied to the electrode 1, a lower N type layer is inverted, the layers 3, 7 are connected, the junction capacity of the layer 7 and the substrate 2 is added, thereby exhibiting large input capacity, and increasing the electrostatic breakdown withstand voltage. The concentration of an electric field at the edge of the electrode which is caused by the inverting phenomenon under the electrode 1 is prevented by providing the layer 7, and the defect in Si due to stress at the junction time does not affect the influence of the electrostatic withstand voltage. According to this structure, an input protecting device which has high reliability can be obtained without adding special steps.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input protection device for a field effect transistor.
In particular, the present invention relates to an improved input protection device for integrated circuits and circuits constituted by transistors of MO8 structure.

With the recent progress in MO8 circuits, an understanding of the phenomenon of static electricity in MO8J structures, where the gate oxide film of MO8J is damaged due to static electricity from the human body or equipment, has become clearer, and many input protection devices have been devised as a countermeasure. It was done.

Through these improvements in the input protection device, the electrostatic M breakdown resistance has improved, and one tank has become available, which is sufficient for practical use.

However, in recent years, there has been a demand for improved weight resistance against electrostatic stress in applications such as automobile electrical equipment, and improvements to input protection devices have become increasingly important. in general,! ! 11
i1. In order to improve the withstand voltage, the input eyelid protection device itself has to be large, and therefore, especially in the case of a small integrated circuit (S8I), the size of the pellet has a large impact on I/I.
i, t- and has. It is no exaggeration to say that in this type of 8SI, the size of the pellet is determined by the area occupied by the input insulation layer, which in turn determines the cost of the product.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable and inexpensive integrated circuit element by realizing an input protection device that is small and strong against electrostatic stress.

In the present invention, the input terminal of an integrated circuit constituted by at least several MOS transistors is connected to a first aluminum 1 placed on an N-type silicon substrate with a silicon oxide film interposed therebetween. The aluminum electrode is connected to the pole by a pinhole, and the aluminum electrode is inside the substrate.

A second region electrically connected to the resistance region by the P-type diffusion layer of
In an input protection device which is connected to an aluminum electrode and an aluminum wiring on an oxide film, the input protection device has P-type impurity regions at the bottom of the first aluminum electrode and the second aluminum electrode, respectively. It's in the device. It is also preferable to have an N-type impurity region between the two low concentration tPW diffusion regions and below the aluminum interconnection connecting the first aluminum electrode and the second aluminum electrode. Moreover, the first aluminum I! It is also preferred that the other lower P-type diffusion region is electrically connected to the 11It source terminal of the circuit.

In general, electrostatic discharge resistance is related to input capacitance, and the larger the input capacitance, the lower the resistance is.However, increasing the input capacitance will reduce the circuit response speed, etc. This is not desirable because it imposes the above restriction.

According to the present invention, the input capacitance is extremely small under normal operating conditions, but it shows a large input capacitance only when electrostatic stress is applied, so the response speed of the circuit does not decrease. By adding the P-type diffusion region, the electric field concentration phenomenon caused by electrostatic stress is alleviated.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1(a) is a plan view of a standard input/tablet device according to the prior art, and FIG. 1(b) is an x-
FIG. 3 is a schematic diagram of a cross section taken along the x' line. In the figure, l is an aluminum electrode, 2 is an N-type silicon substrate, 3 is a P+ type diffusion layer, and o4 serves as an input layer resistance and a diode.
The N+ type scattering layer 5 is a contact portion between the P+ type diffusion layer 3 and the aluminum electrode 1, and 6 is a silicon oxide film. In such a conventional input protection device, the load resistance is small, especially against electrostatic stress where a negative potential is applied to the input terminal, and the first (a)
) It often breaks at point A or B shown in the figure. The reason for this is that when the PN folds formed in regions 2 and 3 in Fig. 1 are reverse biased, the aluminum electrode 1 becomes negative potential, so the N-type semiconductor chain acid at the bottom of the aluminum electrode 1 is reversed. A
This is because the electric field is concentrated at the point or point B. To deal with this phenomenon, for example, a structure as shown in FIG. 2 is an effective means for improving the withstand capability. In other words, by eliminating the N++ diffusion region 4 at the bottom of the aluminum electrode and at the same time increasing the distance between the aluminum electrode 1 and the N++ diffusion region 4, the electric field concentration at points A and B is alleviated. However, the electrostatic resistance fFi is not sufficient.

FIG. 3 shows a first embodiment of the present invention. In the figure, 7 is a P-type impurity region according to the present invention. In the structure shown in FIG. 3, if P-type impurity regions 3 and 7 are electrically connected under normal operating conditions, the input capacitance is It is the same as the input experience device shown in Fig. 1 or 2, but when a large negative voltage is applied to the aluminum electrode l, the N-type region at the bottom of the aluminum electrode l is inverted, and 3 and 7 are electrically connected. connected. As a result, a fitting capacitance is added by the P-type impurity region 7 and the substrate 2, and a large input '! 6 Lid is shown. It is thought that the reason why the electrostatic breakdown strength is improved is that a part of the applied electrostatic energy is absorbed by this capacitance. The #42% length of this structure is due to the aluminum 11L inversion phenomenon described above in that a deep PMM non-consolidated region with a low a11 degree is formed under the bonding pad. At the same time as preventing electric field concentration at the electrode end, defects in the silicon caused by stress during bonding are
This structure does not affect the electrostatic capacity 1111. Furthermore,
The P-type impurity layer at the bottom of the second electrode also reduces the electric field concentration at the electrode end, thereby improving the breakdown resistance at point B in FIG.

A second embodiment of the present invention, shown in FIG. 4, has an improved structure in the east having an N-type impurity region 8 under the aluminum electrode. This N'' type impurity layer can increase the inversion voltage at the bottom of the aluminum electrode 1. Therefore, it is particularly suitable for MO8 devices that require high breakdown voltage. The N- type impurity region, which has the same effect JJ as in the example, needs to be lower than the N+ type scattering layer impurity at in order to prevent the destruction at point A in FIG. In order to improve the breakdown voltage of the N-channel transistor, MO8 devices are equipped with a
It has a type impurity region and can be formed at the same time.

The third embodiment shown in FIG. 5 has a structure in which a P-type impurity region 7 formed under a bonding pad is connected to the lowest potential of the circuit to a source line (Vss) via a contact 9. In this structure, electrostatic energy is released as a current to the power supply line, so it has an extremely large electrostatic withstand capacity. In Figure 5, an example of connection with the Vss line is shown, but
Even when connected to the VDD line, there are effects such as -. It goes without saying that the F1 type impurity region 8 also achieves the above-mentioned effect 1 in the third embodiment.

In the embodiment according to the present invention described above, the P-type impurity region 7
This can be done at the same time as forming the P-well, and as mentioned above, when the operating voltage is high, it is possible to create a device with gs grain properties at a low cost without adding any S. can be provided.

[Brief explanation of drawings]

1 and 2 are diagrams showing an input security device according to the prior art, and FIGS. 3, 4, and 5 are diagrams showing an embodiment of the present invention. In the figure, 1...aluminum electrode, 2...
...N-type semicircular substrate, 3...P+ type diffusion region, 4...N++ diffusion region, 5...P
Contact area between mold diffusion region and aluminum electrode, 6...
・Silicon oxide film, 7... P-type impurity region, 8
. . . N-type impurity region, 9 . . . Contact for P-type impurity region, 10 . . . Aluminum electrode connected to a power source.

Claims (1)

[Claims] (1) The input terminal of an integrated circuit constituted by at least a plurality of field effect transistors is connected to the first 11 aluminum poles and conductive wires installed on the N-type 7 silicon substrate with a silicon densified film interposed therebetween. and the aluminum electrode is connected to a second aluminum electrode electrically connected to a resistance region formed by a P-type diffusion layer in the substrate by an aluminum wiring on an oxide film. An input protection device characterized by having P-type impurity regions under each of a first aluminum electrode and a second aluminum electrode. (23 (In the input protection device of Section 11, an N-type impurity is added between the two low-concentration P-type diffusion regions and under the aluminum interconnection connecting the first aluminum electrode and the second aluminum electrodes w and t). The input protection device according to claim (1), characterized in that the area is shouldered. (In the input protection device according to paragraph (1) or (2), the 2. The input protection device according to claim 1, wherein the type diffusion region is electrically connected to a power supply terminal of the circuit.