JPS58177595A - Signal transmitting circuit - Google Patents

Abstract

PURPOSE:To facilitate designing and to decrease manufacturing processes, by driving source follower and transmission gates, stage by stage, alternately in different phase, and transmitting an input signal to stages, one after another, successively. CONSTITUTION:A transistor M41 turns on synchronously with a signal phi2 to store a pulse 22 at the gate 3 of a transistor (TR) M51. When the voltage V3 (figure F) of this gate 3 reaches VH, the TRM51 turns on and operates in the same way with a TRM21 to obtain a pulse 13 at the source 4 of the TRM51 (figure G). Similarly, pulses 23, 24- of signals phi1 and phi2 appear at the sources 6, 8- of TRs M22, M52- (figures I, K-). Therefore, an input signal phiIN is transmitted successively in this circuit to obtain the pulses at the sources of the TRs M21, M51, M22, M52- successively. Then, those pulses drive, for example, horizontal lines successively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission circuit suitable for use in a shift register for driving a CCD image sensor, a liquid crystal display, a memory device, etc.

For example, a circuit as shown in FIG. 1 has conventionally been used as a shift register for sequentially driving the horizontal scanning layer of a CCD image sensor line by line.

In the figure, the input terminal (1) is M for enhancement m.
OS) is connected to the gate of transistor TI, and the source of this transistor TI is connected to the ground line (2) W! MO8 transistor T whose drain is depletion
This transistor T2 is connected to the source and gate of T2.
The drain of is connected to the power supply line (3)K.

This transistor TI, T! Transistor TI, T! The transistor T41., which is also KII-wired. TSI K is connected to this transistor T41. The connection point of T51 is connected to the transistor T1. T
Transistors Tyr and TsIK connected in the same way as 11
Connected.

The transistors Ts1 to TIIF)fi are sequentially and repeatedly connected. In addition, the upper fixes in the figures are shown in common, and the lower ones are changed sequentially.

Furthermore, if the phase is further different, the gastric upset signal φ1. The terminals (4) and (5) supplied with the φ work are the transistors Tll, Tll... and the transistor Ts, respectively.
It is connected to the gates of t, Ta2, and so on.

This circuit K> has the proverbial ivy terminals (4), (5)
K is the lock signal φ1.K as shown in FIGS. 2A and 2B. φ2
is supplied. On the other hand, the input terminal (1) K is supplied with a signal φIN as shown in FIG. 2 CK, for example.

As a result of this, an inverted voltage Vl as shown in FIG. 2 DK appears first at the connection point (2) between the transistors Ts and Tz.

KokoteVtp-p = VDD (MDDHaIHII
5 y (3) chisel pressure).

Next, Vl is sampled by the signal φl and held at the gate of the transistor 'l' 41, and a voltage v2 as shown in FIG. 2E appears.
41. At the connection point (2) of T51, an inverted voltage v3 as shown in Figure 2 FK appears. For example, the first horizontal scanning layer is driven by this voltage VsK.

Furthermore, the signal 3 is sampled by the signal φ2 and held at the gate 2 of the transistor 171, and a voltage v4 as shown in FIG. 2 GK appears. This K means that the transistor T
71. Connection point of T81 ■, transistor T420 gate ■, transistor T42. At the connection point (3) of T5Z, voltages V5. V6.
V7 appears, and the second horizontal scanning fd is driven by this voltage v7. The above-described operations are then performed sequentially.

Here, if the condition of ■(φt, 1lz)pp ≧VDD + vth is satisfied as the threshold value th of the transistors Tss, Tst, etc. that constitute the transmission gate, then the signal is transmitted through the transmission gate. transmitted.

After 5K, the input signal -1N is transmitted sequentially, and each horizontal j1! The margins are driven sequentially.

However, Jin's circuit requires six transistors in one stage from transmitting a signal to obtaining the next signal. For this reason, the circuit scale becomes large, and when a special KIC is used, the chip area becomes too large, leading to problems such as an increase in ICf):2 stroke. That is, in the circuit described above, transistor T41. T51 and T71. Each signal is inverted, so twice as many elements are required to obtain the same phase signal! It has become.

In addition, in the above circuit, when a capacitive load is connected to the output side, the waveforms of the output signals shown in Fig. 2 F and JK become dull to 5 as shown by the breakage. When used in an image sensor, for example, the degree of decomposition deteriorates, and the quality of the image deteriorates due to color mixing.

Furthermore, in the case of the circuit described above, the transistor Tt.

T51. T81... always has IEIK on,
For this reason, transistors Tl, T41. Tf1...
When the switch is turned on, a through current flows, consuming an extremely large amount of power.

Also, since each transistor is driven in the encompassing region,
%, a large amount of power is required to drive the circuit at high speed.

Also, the low level of the output signal is the transistor T41 and T
Since it is determined by the partial voltage of s+..., the low level will fluctuate due to the variation K of these elements, making it difficult to design.
IK becomes.

Since different elements are used for the enhancement type and derejection salt, for example, when integrated circuits are used, many manufacturing processes are required.

In view of the above point K, the present invention is designed to eliminate the above-mentioned conventional drawbacks with a simple configuration. ll Below, embodiments of the present invention will be described with reference to the drawings.

In the fifth III, the input terminal (1) constitutes a transformer construction gate MO8O8
Mo1 of enhancement through Transis Ml)
Connected to the gate of Tunsistor M2t. A bootstrap capacitor tcs1 is connected between the gate and source of this transistor Mll. Also, the drain of the transistor M11 is connected to the MO of the enhancement module forming the transformer construction gate and the gate 'KII of the transistor M41. Further, the source of the transistor pMs1 is connected to the gate of the M08 transistor Mtt of the enhancer W through the drain and source of the transistor M41. This transistor Mal
Condant tC for Pootstrap on the gate north threshold of
*S is connected. In addition, the drain of the transistor Mll is connected to the gate of the enhancement device Moa) which is configured as a transformer construction gate, and the source of the transistor Msl is connected to the next stage circuit through the drain and source of the transistor M71. be done.

This transistor M2 l, M4 ], Ma 1. M
71 and capacitors C31 and C610 circuits are repeatedly connected in sequence.

Furthermore, the clock terminal (4) is connected to the gate of the transistor M1 and the drains of the transistors Msx, Msx, etc., and the clock terminal (5) is connected to the gate of the transistor M1 and the drain of the transistor M21.
．． Connected to the drain of M21...

In this circuit, the clock layers (4), (5),
The input terminals (1) each receive a signal φ1. as shown in FIG. 4A, B, and C. φ2. φIN is supplied. Here, the signal φl.

The high level of signal φ2 is set to vH, the low level is set to VL, and the signal φIN is set to high level vi and low level tVL. Also, the signal φ1. The pulse of φ2 is set as shown in the figure (11
).

[12]..., [211(22]...).Also, all the threshold values of the MO8 transistors are set to vth.

As a result, first VH≦VH−vth # H+ + H
+ ' (If 11, the signal φ1N is transmitted through the transistor Mt of the pulse [:12] of the signal φ1, and a voltage Vl as shown in the fourth diagram appears at the gate of the transistor Ml10.

Next, the voltage VS (@4
In Figure B), initially Vl - Vl wx VH - VL > vth *
m e ＠ ＠ ＠ ＠ From (2), the transistor M! 1 is on and Vt = VL (
......(3) Then, when the pulse [22] of the signal φ8 comes, the voltage v1 is raised through the capacitor C31, where cB is the boot trap capacitance and cB is the stray capacitance of the gate of the transistor M21. At this time, if vt -vth≧vH...(5), then Vl xx VH...Mountain...(6) Tonari, a pulse [22
] is extracted.

Sara busy priest φ! In synchronization with this, the transistor M41 is turned on, and the pulse (22) is also accumulated at the gate (2) of the transistor Ms1. And this gate ■ voltage Vs (
When F) in Fig. 4 becomes V3 = VH (7) k, the transistor Msl is turned on, and a pulse [13] is extracted to the source ■ of the transistor Ms1 in the same manner as the transistor M21. 4 q).

Similarly, the transistors M22, Ms2...
The signal φ1. is applied to the sources ■, ■... Each pulse (23) of φ2.

[14]... are extracted (Fig. 4 I, K...
...).

Therefore, in this circuit, the long signal≠1 is transmitted sequentially, and the transistors M21, Ms3Mzz, M5z...
The 9th order pulse is taken out to the source of... With this pulse, for example, horizontal scanning lines can be sequentially driven.

Furthermore, in FIG. 4, voltages Vl, V3, V5...
The increase in voltage vA of ... is the capacitor C31, C61
This is due to the Pootstrap effect of...
, and the voltage drop v of voltage Vz, V<...
B is due to the decrease in voltages Vl, V3, etc., where CL is the capacity of the load, and voltage V2. V3...Increase in voltage V
C is determined by d'<III of signal φ2.
Voltage Vs due to turning on ss, Mix...
, Vs-... due to the distribution of charges, is 9, and the increase in voltage VD of voltage Vl is due to this voltage VC
It is due to K. Furthermore, the residual voltage V of the voltages Vg, Vs...
E is due to the fact that Vp −) −VL −+ VL.

If a capacitive load such as a CCD sensor or a liquid crystal display is used as the load, CL > C8.
TS C4・・・・・・αken, and the above vB, v(,
, vp, and vE are all approximately zero, and no problem occurs in normal use.

Also, the capacitance value cB of capacitors C31, C61...
teeth.

From the above equations (41, (5)), and the breakdown voltage of the transistor ~ If, M < 1, M7 t, which becomes the transfer gate, is B
V, it can be found from these two equations and selected in relation to C161.

In this way, the transmission of the input signal .phi.

That is, in the above circuit, the configuration of ll11 from transmitting a signal to obtaining the next signal is, for example, a transistor Mz.
There are only three elements: x, Mat, and capacitor Csl.

Therefore, the circuit scale is small, and the chip area when integrated into an IC is also reduced.

In addition, the output signal is the clock signal φ1. - is formed by extracting the desired pulses, and by shortening the pulses of the four-way signals -1 and φ2 as described above, it is possible to easily eliminate overlap in the output signals.

Furthermore, since no through current flows as in conventional circuits, power consumption is extremely low.

Furthermore, since each transistor is driven in the [11 region], high-speed rotation can be performed, and power consumption does not increase accordingly.

In addition, a task signal φ1. Since an output signal is obtained by each of the φ values, the circumference of the proverbial signal can be reduced to 1 as in the conventional case, which also reduces power consumption.

Also, the four-level output signal is matched with the four-level VL of the clock signal φ1°φ2 and the input signal -IN4F), making the design extremely easy.

Furthermore, since the circuit can be formed only with, for example, an enforcement type element, when it is integrated into an IC, the circuit can be easily and inexpensively formed.

By the way, the above-mentioned circuit (here, MOS) transistor is constructed as follows. In FIG. 5, an N source region breakdown ring and a drain region (L3) are formed on a P-type substrate (11). A 5in2 A layer at is provided, on which a gate electrode α9 is deposited.

Therefore, in such a MOS) transistor,
[A capacitor is formed in the portion α where the pole 09 and the source region α2 face each other, and has a capacitance. Further, when the gate potential becomes high, a channel fin is formed between the source region tJ21 and the drain region fin, and at this time, a conductance is also formed between the gate electrode a$ and the channel #fin.

Therefore, in the circuit described above, [conductor Cat] is used.

MO8 transistor Mat, Ms as C@1-...
A capacitance between the gate and source or channel of l. or O.. can be used. In that case, the circuit diagram is as shown in No. 6E.

KNO2) If the capacity is insufficient for the transistor alone, a capacitor may be provided at 5 as shown in Figure 7.
NO2) The capacitance between the gate and source drain of the Tunsistor MSl, M@l, etc. may be used, and in this case, the M0808 transistor l.

Mar-@- may be an enhancement type or a diversion type.

[Brief explanation of the drawing]

1 is a diagram of a conventional circuit, FIG. 2 is a waveform diagram for explaining the same, and FIG. 3 is a connection diagram of an example of the present invention.
Figure 5 is a waveform diagram for explaining the same, Figure 5 is a configuration diagram of a MOS transistor, and Figures 6 and 7 are connection diagrams of other examples of the present invention. (1) is the input terminal, (4) and (5) are the terminals Ml, M! 1゜M41, M51, M71...φ
- is M08 transistor, C31, Cl51...
is a capacitor. Same Hide Matsukuma J! 4. Drop - [Figure 1 Figure 3 Figure 2 ,, , / Figure 4 1j'' Figure 5 1 Figure 6 Figure 7

Claims (1)

[Claims] 1. An input signal is supplied to a source hopper, and a capacitance component for bootstrapping is provided between the gate and source of the source hopper, and a signal from the source holder is supplied to a transformer building. The circuit consisting of the above-mentioned / -fi 4 fighter and transmission gate is connected in sequence so that it is supplied to the next stage through the transmission gate, and
A signal transmission circuit in which the input signal is sequentially transmitted from each stage by driving the source driver and the transformer gate at different phases alternately for each stage. 2. A 5K signal transmission circuit according to claim 1, in which a capacitance component between a channel and a source and a gate of an element constituting the source carrier is used as a capacitance component for the bootstrap. 3. The above-mentioned claim S stripe 1 #C is used to define the capacitance component for the Pootstrap as the capacitance component between the channel and source of the element constituting the source follower and the capacitance component between the gate and source of the element. A signal transmission circuit consisting of an additional capacitor inserted into the circuit.