JPH0316720B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer device, and more particularly to a signal charge detection circuit for synthesizing output signals of a charge transfer device.

FIG. 1 is a diagram showing a conventional signal charge detection circuit that combines output signals of two series of charge transfer devices.
FIG. 2 is a timing chart thereof. Hereinafter, the operation of the conventional circuit will be explained using FIGS. 1 and 2.

At time _t1 , φ _R1 becomes High level, the reset transistor Tr1 is turned on, and the potential of the output diffusion layer 2 of the charge transfer device is set to VOD. At time _t2 , φ _R1 becomes a low level, and the diffusion layer 2 becomes in a floating state. At time _t3 , _φ1 becomes Low level, and the carrier accumulated under the electrode 22 is applied to a constant voltage.
It flows into the diffusion layer 2 through a channel under the output gate 21 to which VOG is added. The potential change in the diffusion layer 2 due to this inflow carrier becomes a signal voltage. This signal voltage is used to raise _φSH1 at time _t4 .
By setting the high level, the sample and time
Hold that signal pressure level at t ₅ .

The above explained the signal transmission from register A, but the signal transmission from register B is also φ _R2 , φ _SH2
This is done by adding pulses whose phase is shifted by half a week from φ _R1 and φ _SH1, respectively, and at time t ₆ the signal from register B is sampled.

In this way, the output signals of the two columns of charge transfer devices can be combined by alternately sampling and holding the respective output voltages. These separately sampled and held signal voltages are applied to the gate of transistor 9 of a source follower circuit consisting of transistors 9 and 10, and are taken out as VonT from output terminal 45 with low output impedance.

However, such conventional synthesis methods have the following drawbacks.

As shown in Figure 1, sample hold Tr5
There is a coupling capacitance between the gate of
When φ _SH1 changes from High to Low due to the presence of C ₁ , the potential VO1 at the node 44 undergoes a fluctuation by ΔV as shown in FIG. This amount of variation ΔV
is the clock amplitude of φ _SH1 , V _SH1 is the capacitance of the hold capacitor 41, and C _H is ΔV=C ₁ /C ₁ +C _H ×V _SH1 . To increase the specific value, C ₁ = 0.05 pF,
When C _H = 1pF and V _SH = 5V, ΔV = 238mV.
Since the output voltage of a CCD is approximately 1V in height, this becomes a large noise component. To lower ΔV,
It is possible to lower V _SH , increase the value of C _H , and decrease the value of _C1 , but the decrease in V _SH is caused by sampling Tr5.
Increasing the ON resistance requires an increase in sampling time, which leads to a decrease in sampling frequency. An increase in the value of C _H results in an increase in the CR time constant during sampling, which in turn leads to a decrease in the sampling frequency. Also, reducing the value of C ₁ means
This means a decrease in the Tr size of the sampling Tr5 in the W direction, which lowers the gm of the sampling Tr5, which also leads to a decrease in the sampling frequency.

As described above, in the conventional method, the noise ΔV during sampling was mixed into the output signal, reducing the S/N of the output signal. In order to reduce this noise, the maximum sampling frequency had to be lowered.

The present invention eliminates the above-mentioned drawbacks, and provides a charge transfer device in which sampling noise mixed in the output is removed without reducing the maximum drive frequency, and the S/N of the output signal is improved.

According to the present invention, in a charge transfer device including a circuit for synthesizing output signals of two series of charge transfer devices, the stable signal output period in each bit of each series before synthesis is made longer than the period other than the signal output period. The present invention includes two transfer gates that transmit the signal output during the stable signal output period, and a signal synthesis circuit that synthesizes the two transferred signals and outputs it as a single signal. A characteristic charge transfer device is obtained.

The principle of noise removal according to the present invention is that the sampling noise is
We focused on the fact that it occurs at the point where it changes to Low, that is, when it changes from the sampling period to the hold period, and by eliminating the hold period, we were able to eliminate this noise. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows an embodiment of the invention. At first glance, it looks similar to the conventional method shown in Figure 1, but VOG
The clocks applied to the transfer gates 32' and 22' immediately before the gates are φ _2L and φ _1L in Figure 1, and Tr5',
The difference is that 15' is a transfer transistor instead of a sampling transistor.

Hereinafter, this embodiment will be explained using the timing chart shown in FIG.

At time t ₁ , φ _R1 becomes High level, reset Tr ₁ is turned on, and the output diffusion layer 2 of the charge transfer device is turned on.
The potential of is set to VOD. At time t ₂ , φ _R1 is
The level becomes low, and the diffusion layer 2 becomes in a floating state. At time _t3 , _φ1L becomes Low, causing the carriers accumulated under the electrode 22' to flow into the diffusion layer 2 through a channel under the output gate 21 to which a constant voltage VOG is applied. The potential change in the diffusion layer 2 due to this inflow carrier becomes a signal voltage. What should be noted here is that the stable period of the signal output from register A is from the time carriers are injected into the diffusion layer 2 until the next period when φ _R1 becomes High, as shown in Figure 4.
_TH1 . Similarly, the stable period of the signal output from register B is TH ₂ .

Since the output periods of the two series overlap in this way, a hold period occurs by applying the pulses φ _T1 and φ _T2 shown in Figure 4 to the transfer transistors 5' and 15', respectively. It is possible to combine two series of signals without any trouble. For example, at time _t4 , φ _T1 becomes High, and φ _T2 becomes High.
It starts to change from to Low. That is, before the transfer gate 15' is disconnected, the transfer gate 5' is in a conductive state, so that the node 4
4' has low impedance, and φ _T2 is
The coupling noise that mixes in when changing from high to low has been drastically reduced, almost no mix-in, and there is no hold period, so the ΔV
There is also no mixed noise.

As described above, by using the circuit for synthesizing output signals of the present invention, it is possible to synthesize two series of output signals at high speed without introducing sampling noise, and the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional configuration for synthesizing the output signals of two series of charge transfer devices. FIG. 2 is a timing diagram illustrating the operation of the conventional configuration. FIG. 3 is a diagram showing an embodiment according to the present invention. FIG. 4 is a timing diagram illustrating the operation of the configuration of FIG. 3, which is an embodiment of the present invention. 1, 11... MOS'Tr for reset, 3, 4, 9,
10, 13, 14...Configure source followers
MOS'Tr, 5, 15...For sample hold
MOS'Tr, 5', 15'...For transfer
MOSTr, 2, 12... Diffusion layer for charge signal detection, 2
1, 31...output gate electrode, 22, 23, 32,
33, 22', 32'...CCD transfer electrode.

Claims (1)

[Claims] 1. A first charge transfer means having a first output diffusion layer at the output of the signal charge transfer path, and a second charge transfer means having a second output diffusion layer at the output of the signal charge transfer path. a first reset transistor for bringing the first output diffusion layer to a predetermined potential by a first reset pulse; and a first reset transistor for bringing the first output diffusion layer to the predetermined potential by a second reset pulse. a second reset transistor that receives the potential of the first output diffusion layer as an input signal; a first source follower circuit that receives the potential of the second output diffusion layer as an input signal; an output stage source follower circuit having an input terminal and an output terminal; and an output stage source follower circuit having an input terminal and an output terminal; A first transfer gate supplies the output in response to a transfer pulse, and supplies an output of the second source follower circuit to the input terminal of the output stage source follower circuit in response to the second transfer pulse. a second transfer gate, the first reset pulse after the first reset pulse ends;
The first transfer pulse is generated after the potential of the output diffusion layer becomes stable, and the first transfer pulse is generated after the potential of the second output diffusion layer after the second reset pulse is stabilized. 2. A charge transfer device, wherein two transfer pulses are generated, and the first transfer pulse and the second transfer pulse have a phase difference of 180°.