JPS58176932A - Manufacture of vertical type semiconductor element - Google Patents

Abstract

PURPOSE:To prevent the generation of element defects due to short-circuit or poor withstand voltage by a method wherein an anodic oxidation is performed between the process of contact hole opening for the electrode of the surface side of a substrate and the process of adhering an electrode substance on this contact hole. CONSTITUTION:When there is short or low withstand voltage between a source and a drain, a current flows from the substrate 1 to a cathode via the source region 3 as shown by the arrow mark, and an insulating anodic oxide film (SiO2) 11 constituted of the fixed thickness d is formed on the surface of the source contact hole 8. Next, Al which is the electrode substance is evaporated on the surface of a substrate, and, when an Al electrode 13 is formed thereby, the source region 3 and the Al electrode 13 are adhered closely each other resulting in ensuring good conduction, in a normal transistor. On the contrary, in a transistor of defects between the source and the drain, the both are electrically insulated by the anodic oxide film (SiO2) 11 formed between the source region 3 and the Al electrode 13, and accordingly the electrode 13 is not short-circuited by the substrate 1 and Al.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing vertical semiconductor devices such as vertical MOS transistors and vertical bipolar transistors with improved yields.

In recent years, due to the desire to simplify and integrate drive circuits and to lower the power supply voltage of the circuits, there has been a movement to apply vertical semiconductor elements, which have low on-resistance and are suitable for power switching, to switches.

The vertical semiconductor devices include vertical power MO8T transistors, vertical bipolar transistors, etc. The basic structure of these devices is shown in a simple equivalent circuit as shown in FIG. 1(a). , bipolar transistors are as shown in the same figure (b), each of which is considered to be a large number of transistors connected in parallel.

By the way, in the vertical semiconductor element having the above structure, if even one of the transistors connected in parallel has a short circuit or a breakdown voltage failure, the entire element becomes defective.

Conventionally, in the manufacturing process of the vertical semiconductor device, the M
In order to avoid defects such as those described above between the source and drain in OS transistors and between the emitter and collector in bipolar transistors, workers must perform the work carefully and strictly check each step. Ta.

This invention was made in view of the above circumstances, and its purpose is to prevent the occurrence of element failures due to the above-mentioned short circuits and breakdown voltage failures, and to improve the yield of this type of vertical semiconductor element. .

In order to achieve the above object, the present invention provides a method for manufacturing a vertical semiconductor device of this type, in which a contact hole for an electrode on the surface side of a substrate is formed between a step and a step of depositing an electrode material on the contact hole. Further, a step is provided in which the substrate is used as an anode, and the surface side of the substrate is oxidized by using the current flowing in the substrate to insulate and isolate only the current-carrying path where the short circuit has occurred.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram showing the main steps in manufacturing a vertical MOS transistor by the method of the present invention.

Figure 2 (a) shows an N-channel linear MOS transistor in which a P-well 2, an N-type source region 3, and a P-shaped isolation region 4 are formed on an N-type substrate 1, which becomes a drain region, and then a gate oxidation W is formed. !A5. The gate electrode 6 and the correlation insulating film 7 are formed in sequence, and the contact hole 8 for the source electrode is formed.
The figure shows a cross section of the device after it has been cleared, and the one on the left is a normal transistor, and the one on the right is a transistor whose source region 3 and substrate 1 are electrically connected due to a defect in P'71. be.

FIG. 2(b) is a cross-sectional view of the element f after the step of anodizing the flat side of the substrate using the substrate 1 as an anode. At this time, the value of the forming voltage V form is set to be slightly lower than the source/drain breakdown voltage.

In addition, the electrolytic solution used for anodic oxidation is preferably one that does not contain alkali ions such as Na+, etc., and the solvent is ethylene glycol, N-methylacetamide,
Tetrahydrofuryl alcohol and the like can be considered, and N84NO3, HNO3 and the like can be considered as solutes.

Furthermore, I! 1. Various documents are known regarding the details of the II conversion method, such as P, F, 5ctvidt.
and W, M 1chel, J, E I
electrochenlSoc, 103, No. 4 (
1957) pp. 230-236 or Nanjo et al., Electrochemistry
47. No. 1 (1979) pp. 48-54.

When anodic oxidation is performed in this way, as shown in the transistor on the left in Figure 2(b), if the source and train are properly insulated, no current will flow; As shown in the transistor on the right side of the figure, when the source and drain are short-circuited or when the withstand voltage is low, current flows from the substrate 1 through the source region 3 to the cathode as shown by the arrow, and the source contact hole 8
An insulating anodized layer m having a predetermined thickness d is formed on the surface of
(Si 02) 11 is formed.

Here, the relationship between the forming voltage Vform and the thickness d of the anode forming layer varies depending on the electrolytic solution, current density, etc., and is about 4/V to 10/V.

Next, as shown in FIG. 2(C), in the next step 5-, an electrode material of A DEG C. is deposited on the surface of the substrate at a thickness of about 1 to 2 μm, thereby forming an All electrode 13.

Then, in the normal transistor shown on the left side of FIG. 2(C), the source region 3 and the All electrode 13 are in close contact with each other to ensure good conduction, whereas on the right side of the figure In the transistor with a defective source-drain region shown in FIG. - Even if there is a conductive transistor between the trains, the substrate 1 and the AJ electrode 13 will not be short-circuited.

In the embodiment described above, if the surface of the normal source contact hole 8 is etched by a small thickness with F buffer H solution before the electrode material deposition process shown in FIG. 2(C), the anode The thin anodic oxide film formed on the surface of the normal source contact hole 8 is completely removed by the increasing current in the oxidation process, thereby making the conduction between the source region 3 and the Al electrode 13 even more reliable. 6- I can do it.

Next, FIG. 3 is a process diagram showing only the main steps in manufacturing a vertical bipolar transistor by the method of the present invention. FIG. 3(a) shows a vertical bipolar transistor in which a base region 21 and an emitter region 22 are formed on an N-type substrate 20, an insulating film 25 made of Si02 is provided, and a contact hole 23 for an emitter electrode is formed.
．． and a cross-sectional view of the element after the base electrode contact hole 24 is opened.

As shown at 26 in the figure, due to a defect occurring in the P-type base region, the substrate 20 and the emitter region 22
It is assumed that conduction has occurred.

FIG. 3(b) shows a cross-sectional view of the element after the substrate surface side has been anodized using the base 1120 as an anode, as in the case of the MOS transistor shown in FIG. 2. At this time, the value of the forming voltage vfOr- is
Set it slightly lower than the collector withstand voltage.

Then, the emitter region 22 is reliably insulated from the substrate 20.
While no current flows in P! ! ! For the parts 26 that are electrically connected to the substrate 20 due to a defect in the region or a low withstand voltage of the P-type head region, a current 2 flows as shown by the arrow in the figure, and this causes the surface of the corresponding emitter contact hole 23 to flow. is anodized, and an insulating anodic oxide film (Si 02) 27 is formed on its surface.

Next, in the electrode material deposition step shown in FIG. 3(C), an electrode material A6 is deposited on the substrate surface to a thickness of about 1 to 2 μm to form an emitter electrode 28 and a base electrode 29, respectively. do.

Here, in the part where the emitter and collector are properly insulated, the emitter region 22 and the emitter electrode 28 are in close contact with each other, and this provides good electrical continuity, whereas the emitter and collector are short-circuited. With respect to the portion where the resisting voltage is low or the breakdown voltage is low, the emitter electrode 28 and the emitter region 22 are reliably insulated by the anodic oxide film (St 02) 27 formed on the surface of the emitter contact.

In the above embodiment, if the surface of the emitter region 22 corresponding to the normal portion is slightly etched with a 7-day HF buffer solution before the electrode material deposition process shown in FIG. 3(C), In the anodic oxidation step, the thin anodic oxide film formed on the surface of the normal emitter contact due to leakage current can be removed, thereby further perfecting the conduction between the normal emitter region 22 and the emitter electrode 28. be able to.

As is clear from the description of each of the embodiments above, according to the present invention, by simply adding an anodizing process to the conventional manufacturing method of vertical semiconductor devices, it is possible to eliminate defective devices due to insulation defects such as short circuits and breakdown voltage defects. This has the effect of preventing this and improving yield.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are equivalent circuit diagrams showing an example of a vertical semiconductor element, FIG. 2 is a process diagram showing a method for manufacturing a vertical MO3t transistor using the method of the present invention, and FIG. 3
The figure is a process diagram showing a method for manufacturing a Vivo 9 transistor according to the method of the present invention. 8... Source contact region 9... Source region 11 at defective location... Anodic oxide film 13... Af electrode 23... Emitter contact Area 26...
...Defect location 27...Anodic oxide film 28...Emitter electrode Patent applicant 10- Figure 3 Procedural amendment 1, Indication of events Japanese Patent Application No. 57-59155 2, Title of the invention: Method 3 for making vertical semiconductor devices, relationship to the amended case Patent applicant address: 2 Takaracho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture Name
(399) Nissan Motor Co., Ltd. Representative Shun Ishihara 4, Agent 101 Address 1-15-16-7 Uchikanda, Chiyoda-ku, Tokyo
, Contents of the amendment (1) In the specification, page 3, line 6 and page 3, line 8, “
Delete "This species". (2) Page 3, line 12, page 4, lines 9 and 11, page 5, line 13, page 6, line 11. The word "board" in lines 12, 15, and 20 of page 7 and line 3 of page 8 is corrected to "board." (3) Lines 2 to 5 of page 4. The line ``Sequentially form the insulating film 7 to become the drain region'' is replaced by ``Gate oxide film 5. Gate electrode 6
After forming the P-well 2°N raw source region 3. P
A green well contact region 4 is formed, and finally an interlayer insulating film 7 is formed.''

Claims (1)

[Claims] <1) In a method for manufacturing a vertical semiconductor element having a plurality of parallel conduction paths cut off by a predetermined gate layer between a substrate surface side electrode and a substrate: For the substrate surface side electrode The vertical type contact hole is characterized in that an anodizing process is provided between the process and the process of depositing an electrode material on the contact hole, in which the substrate is used as an anode and the surface side of the substrate is oxidized. A method for manufacturing semiconductor devices. (2) The step of depositing the electrode material is a step of removing the oxide film deposited on the surface side of the substrate in the saponification step by a minuscule thickness, and then depositing the electrode material. A method for manufacturing a vertical semiconductor device according to claim 1.