JPS5817661A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To form an I<2>L, which operates at extremely high speed and power consumption thereof is low, by using an N-P-N transistor operating in the reverse direction. CONSTITUTION:An N type high impurity concentration 52 and an N type epitaxial layer 53 are shaped onto a P type silicon substrate 51, and a field oxide film 54 is further formed. A thin SiO2 film 55 is molded, and a small concentration P<-> type region 56 functioning as the internal base layer of the I<2>L is shaped into the layer 53. One part of the film 55 is removed through etching, and a Schottky metallic layer 57 and the CVDSiO2 film 58 of a low temperature are formed continuously. The layers 57, 58 are taken off, and projecting regions are molded. The ions of a P type impurity for an external base such as boron are implanted while using the films 58 as masks, the CVDSiN film 59 of a low temperature is deposited, and an ion implantation layer is activated by laser beams. The film 59 is removed through etching by EIE, metallic wiring 61 is disposed and the metal is sintered lastly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device using an NPN (NPN) transistor that operates in a reverse direction.
Int@grat@d InJ@@ti@m+ L@g
ls) The present invention relates to a semiconductor device suitable for a semiconductor integrated circuit formed by integrating darts, and a method for manufacturing the same.

As shown in Fig. 1, I"L is a so-called inverted structure type particle NPN) Rungis/1 and the above transistor 1 whose collector is the pace of this transistor are complementary lateral PNPs) U/dimetal 2 It is a logic element with a complex structure.

In this logic element, the lateral PNP transistor 2 acts as an injector for injecting charge into the inverse structure particle NPN transistor 10, and the inverse structure particle NPN transistor 1 acts as an inverter.

Therefore, it has recently attracted attention as an element that has a small logic amplitude and can operate at high speed and with low power consumption. In addition, since isolation between elements is not required, the degree of integration is high and it is suitable for application to large-scale integrated circuits.

Since S6Kr"x is a pie2 process technology, it is possible to easily coexist other ΔI-ra circuits, such as S=A circuit and ECL circuit, on the same chip.
A multi-function accumulating circuit can be realized.

A lot of research has been done on methods to operate this higher I"L at high speed, but it is important to understand that the small amount of ions accumulated in the emitter and pace region of the switching and switching transistors can be removed by the switching and switching transistors in the previous stage. For example, IEI] I
i! Journal @f 8elid -8t
at@C1rauits, Vol, 5C-14r
N'-2*Mupril 197L No. 327-336
It is done in pages.

In order to reduce the accumulation of this small amount of WOLF particles, in addition to optimizing the alt profile of the line, semiconductor layer, and emitter layer, we also minimized the area where small WOLF particles are accumulated. This is effective.

As a method for this purpose, a structure as shown in FIG. 2 can be considered.

In the same figure, 11 is a P-type silicon substrate, 12 is an N-type buried layer with high impurity concentration, 13 is a PNP (PNP) paste of transistor 2 and NPN) an emitter of transistor 1,
Mold ♂ taxial layer, 14 is silicon oxide film, 15 is N
PN) Pace of transistor 1 and PNP) P type region which becomes collector of transistor 2, 16 is NPN) Nm high impurity concentration region which becomes collector of transistor 1, 17
18 is an N+ polysilicon layer, 18 is a dielectric layer, 19 is an oxide film, 20 is a metal wiring, and 21 is a PM region which becomes the emitter of the PNP transistor 2. That is, l2Lr-)
is surrounded by a silicon oxide film 14, the Nfi high concentration impurity region 16 and the dielectric layer 18 are adjacent to each other, and the area of the P reduced region 15 is also minimized.

In such a structure, the low-resistance P-type region 15 is separated by the N-type high impurity concentration region 16, and the charge injected from the injector is sufficiently absorbed in the base layer trench directly under the collector far from the injector. However, as shown in FIG. 3, a base contact hole 22 is formed close to the N-type heavily doped region 16,
By interconnecting with I20, the above problem is solved. In this case, the N+ type terisilicon layer 11 is used for the diffusion source of the N type high concentration impurity region 16 and its interconnection, and the metal wiring 20 for base contact interconnection is intersected three-dimensionally.

According to this structure, the collector (N-type high concentration impurity region 1
6) The pace area can be made smaller compared to the area, so
IL switching time can be made faster.

However, in this case, the N+ type polysilicon layer 1ri
): Used for the diffusion source of the N-type high concentration impurity region 16 and the collector electrode number wiring, but in the case of arsenic-doped silicon, the resistance value is 100 to 2 at a thickness of 5 mm.
It's as high as 0θΩ. Therefore, the above I2L is miniaturized, that is, the collector? ILt with narrower silicon layer width
When used in a high current region, the disadvantage is that I2L does not operate due to the high resistance value of polysilicon, and the operating speed becomes slow.

Therefore, in order to make IL faster and more highly integrated,
There are certain limits to the use of silicon layers for collector layer formation. This invention has been made in view of the above circumstances, and its purpose is to provide a semiconductor device and a method for manufacturing the same, which can eliminate the conventional drawbacks by using a special metal for the director of an NPN transistor. It's about doing.

That is, the present invention deposits a metal or metal silicide layer and an insulating film layer sequentially on a conductive type semiconductor layer or semiconductor substrate, and then selectively leaves a part of the semiconductor layer or semiconductor substrate. Impurity ions of the opposite conductivity type are implanted to activate this impurity layer, and selectively leave an insulating film layer on the side surfaces of the metal or metal silicide layer and the insulation layer. A metal silicide layer is used for the collector and collector electrode wiring, and the metal wiring and collector metal or gold I1
A semiconductor device is characterized in that the tetrasilicide layer is separated only by the above-mentioned insulating film layer. According to the present invention, the logic amplitude is small compared to the conventional I''L in which the metal wiring and the collector's crocodile-shaped silicon layer are self-aligned with only an insulating film, and the resistance of the pre-electrode stack wiring is small. A high-speed, low-power consumption I''L with a small φ is easily possible.Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows the IL(r-) circuit for the blind and middle collectors. In the figure, 41 is a Δ-Tical NPN transistor with an inverse structure, 41 is a 2-tyral PNP transistor that is complementary to this transistor 41, and 411 is a Lanzostar transistor.

41 is a diode connected to the collector of the transistor 42, respectively.Next, the specific structure of the circuit and the first implementation of the manufacturing method thereof An example will be explained with reference to Figures 5 (a) to (f).

First, as shown in FIG. 5(a), a P-type silicon vine plate 51 is
An N-type high impurity concentration layer 52 and an N-type epitaxial layer 53 are formed thereon, and selectively oxidized to form a field beast film 5.
form 4. After forming a relatively thin 8102 film 55, a lightly-concentrated P-type region 56, which will become an internal space layer for the IL, is formed in the N-type epitaxial layer 53. This P-fi region 56 can be formed using Giron's high acceleration ion implantation method. Next, as shown in FIG. 5(b), after removing a part of the thin 5in2 film 55 by etching, the metal layer 57 and the CVD 8102 film 58 at a low temperature (such a low temperature that the metal does not form an alloy) are removed. Next, as shown in FIG. Engineering.

tings are removed to form protruding regions. This etching method is known as RIIC (Rea@tive IonEte).
It is more preferable to etch the film approximately vertically with a .klmg).

Next, as shown in FIG. 5(d), the low temperature cvngto
Using the 2 film 58 as a mask, a relatively high concentration of P-type impurity for the external base, for example, ion implantation is performed, and then CVD1iiN at a low temperature (a low temperature at which the metal is not alloyed) is performed.
A film 51 is deposited and the ion implanted layer is activated with a laser beam. At this time, since the reflection coefficient of metal is high, the temperature of the metal 51 part hardly rises, and only the other silicon part becomes high temperature. Then, as shown in Figure 5 (f), low-temperature CVD is applied where only the 60 part is activated.
The 81N film 59 is etched away by RIE.

In this case, the CVDIIN film 59 is selectively left only on the side surface of the protruding region consisting of the epitaxial layer 53, the metal layer 51 in the film 58, and the cyosto film 58, and then the metal wiring 61 is completed.Finally, the metal is sinked. Then the book IL
is completed.

・IL manufactured in this way has the following effects□ I feel dumbfounded.

■NPN) Since the collector of the transistor 41 is a clamp, it is different from the conventional N+ collector layer -N.
+The logic amplitude is smaller than that of polysilicon lead wiring, and a small parasitic capacitance I2L can be formed. Therefore, high speed and low power consumption can be achieved, and since the collector lead-out wiring is made of metal, the wiring resistance can be almost ignored.

■ External pace P type area 60 and collector symmetry)
There is ample space between the metal layer 67 and the main metal layer 67 when viewed from the vertical direction, so
The withstand pressure between the external pace and the collector does not drop.

■ The metal for the collector lead-out wiring can be used as a wiring material with low resistance in terms of the process, and two-layer wiring is essentially possible. In this way, by using the present invention, the IL can be improved in performance. Here, the metals in the simulation are W (tungsten) and Mug.
(silver), MuA (aluminum), MuU (gold), rt (
Platinum), etc. can be considered, and as the silicide film, silicide of a metal such as that described above can be considered.

FIGS. 6(,) to (·) show a second embodiment of the present invention. First, as shown in FIG. 6(,), an N-type high nonwire mobilization layer 12 and an N-type epitaxial layer FJ are formed on a P-type silicon substrate rl in the same manner as in the first O embodiment, and then selectively oxidized. A field oxide film 74 is formed. After forming the relatively thin slo film 11,! A thinly concentrated P-type region 76, which will become a 2L internal space layer, is formed in the Nfi engineered taxial layer 13. Next, the metal layer F1 and the low-temperature CVD 810. As shown in FIG. 6(b), the film 18t is continuously formed with a carbon dioxide layer 11 and a CVD 810. The film 78 is selectively etched and removed using a resist as a mask. In this case, sea,
Tokimetal with phosphoric acid-based etching solution (in case of A/!)
If etching is performed, the low-temperature CVD 11O film r1 becomes an overhang structure.

Next, as shown in Figure 6(,), the low temperature (VD810
Using the second film r8 as a mask, ions of relatively high concentration external paste ion are implanted. and low temperature CVT)i
After depositing lIN film 1#, the above lIN film 1# is deposited using a laser beam.
The ion implantation layer is activated to form an external paste P"ff1lI region 80. Next, as shown in FIG. 6(d), a seal is formed.
CVD5 is applied in RIB so that only the side surfaces of the protruding region made of the metal layer 17 and the CVD8102 film 18 remain.
After etching and etching the IN film 19, the metal wiring 81 is completed as shown in FIG. 6(-). Finally, sink the metal to complete this IL.

The I"L of the first embodiment has the same effect as the I"L of the first embodiment.

As described above, according to the present invention, it is possible to manufacture an IL with extremely high speed and low power consumption.In addition, in the above-mentioned 11th and second embodiments, the I2L is used, but the present invention does not necessarily apply to the I2L. The present invention is not limited to I''L type logic elements, but is also effective for field effect transistors (IQCT) and the like.

[Brief explanation of the drawing]

Figure 1 shows the conventional l2Lf-) circuit, Figure 2 shows the above I'L
FIG. 3 is a plan view showing the I2L wiring/four turns, and FIG. 4 is a diagram showing the structure. Toki collector I”L gate circuit ζ Fig. 5 (a) to (f
) is a cross-sectional view showing the manufacturing process of I2L according to the first embodiment of the present invention, and FIGS. 6(a) to (·) are cross-sectional views according to the second embodiment of the present invention. 5l-PljJ silicon substrate, 52...N-type high impurity concentration layer, 51-N-type epitaxial layer, 56...P-
ffifj area (internal pace), 57... seal, crested metal layer, s 5-cv'osto, membrane, 59-CVD81
N film, 60-P type region (external space), 61...metal wiring, 11...Pfi silicon substrate, 72...N
fi high impurity linear dynamic layer, 73...N epitaxial layer, 1g-P'''' type region (internal pace), 71...metal layer in carbonate, yg/cvDsio2a, r9-
CVD5iN film, go-p fJ region external pace),
81--Metal wiring. Figure 1 Figure 2

Claims (5)

[Claims] (1) A first conductive semiconductor layer or semiconductor substrate; a conductive layer that includes at least a part of the surface of the semiconductor layer or semiconductor substrate and has a bond between the semiconductor layer or the semiconductor substrate; a second insulating film formed so as to cover a side surface of the first insulating film;
a second insulating film formed in the peripheral region of the lower region of the protruding region in the semiconductor layer or semiconductor substrate;
It includes a conductive impurity region, the first insulating film, the second insulating film, and a metal wiring formed to handle the impurity region, and the impurity region and the conductive layer are connected to the protruding region. A semiconductor device characterized in that the semiconductor devices are spaced apart along the lateral direction. (2) The semiconductor layer is an N-type engineered Φshall layer,
A P-type region is selectively formed inside this N'm dielectric layer, the conductive layer is formed on this P-type region, and this conductive layer is used as a collector. A semiconductor device according to claim 1. (3) The semiconductor layer is NPN of the I2L gate.The impurity region is the NPN gate of the NPN transistor and the PNP gate of the I2L gate. 3. The semiconductor device according to claim 2, wherein the semiconductor device is used as an electrode wiring. (4) a step of sequentially depositing a conductive layer and a first insulating film having a flash bond with the conductor layer or semiconductor substrate and a first insulating film on the semiconductor layer or semiconductor substrate of the first conductivity type;
selectively etching the first insulating film, the conductive layer, and at least a portion of the semiconductor layer or semiconductor substrate to form a protruding region; and etching impurities of a second conductivity type from the surface of the semiconductor layer or semiconductor substrate. After implanting ions and depositing a second insulating film, activating the impurity region, selectively leaving the second insulating film on the side surface of the protruding region, and removing the conductive layer from the conductive layer. 1. A method for manufacturing a semiconductor device, comprising the steps of taking out an electrode and forming metal wiring. (5) a step of sequentially depositing, on a semiconductor layer or semiconductor substrate of a first conductivity type, a conductive layer having a bond with the semiconductor layer or semiconductor substrate, and a first insulating film; selectively etching and cindering the insulating film and the conductive layer so that the first insulating film in the armpit has an oversolder structure;
a step of leaving a part of the first insulating film and the conductive layer; and implanting impurity ions for the second conductive lid from the surfaces of the semiconductor layer and the semiconductor substrate, and depositing the second insulating film; a step of activating the region; a step of selectively leaving the second insulating film only on the side surfaces of the conductive layer and the first insulating film; and removing an electrode from the conductive layer and forming a metal □ wiring. 1. A method of manufacturing a semiconductor device, comprising a step of forming a semiconductor device.