JPS58176418U - Arbitrary gain control circuit - Google Patents
Arbitrary gain control circuitInfo
- Publication number
- JPS58176418U JPS58176418U JP7464782U JP7464782U JPS58176418U JP S58176418 U JPS58176418 U JP S58176418U JP 7464782 U JP7464782 U JP 7464782U JP 7464782 U JP7464782 U JP 7464782U JP S58176418 U JPS58176418 U JP S58176418U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- inverting input
- input terminal
- gain control
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のゲインコントロール回路を示す回路図、
第２図はこの考案の任意ゲインコントロール回路の一実
施例を示す回路図、第３図ａは従来のゲインコントロー
ル回路およびこの考案の任意ゲインコントロール回路の
可変抵抗対雑音レベルの特性を比較して示す図、第３図
すは従来のゲインコントロール回路とこの考案の任意ゲ
インコントロール回路における可変抵抗とゲインとの関
係を比較して示す特性図、第４図ａないし第４図Ｃはそ
れぞれこの考案の任意ゲインコントロール回路の応用例
を示す回路図である。
ＩＮ・・・・・・入力端子、ＯＵＴ・・・・・・出力端
子、Ａ１．Ａ２・・・・・・増幅器％ ｚｉｓ ｚ２・
・・・・・インピーダンス回路、Ｒ１゜ＲＢ・・・・・
・抵抗、Ｃ・・・・・・コンデンサ、ＶＲ・・・・・・
可変抵抗。Figure 1 is a circuit diagram showing a conventional gain control circuit.
Fig. 2 is a circuit diagram showing an embodiment of the arbitrary gain control circuit of this invention, and Fig. 3a shows a comparison of the variable resistance versus noise level characteristics of a conventional gain control circuit and an arbitrary gain control circuit of this invention. Figure 3 is a characteristic diagram comparing the relationship between the variable resistance and gain in the conventional gain control circuit and the arbitrary gain control circuit of this invention, and Figures 4a to 4C are the characteristics diagrams of this invention. FIG. 2 is a circuit diagram showing an application example of the arbitrary gain control circuit of FIG. IN...Input terminal, OUT...Output terminal, A1. A2...Amplifier% zis z2・
...Impedance circuit, R1゜RB...
・Resistance, C... Capacitor, VR...
Variable resistance.
Claims (3)
力端より出力信号を出力させ、この第１の増幅器の反転
入力端と接地間に可変抵抗または抵抗分割回路を接続し
、この可変抵抗の可動端子または抵抗分割回路の中点を
第２の増幅器の反転入力端に接続し、この第２の増幅器
の出力端を上記第１の増幅器の反転入力端に接続し、上
記第１の増幅器の出力端を上記第２の増幅器の非反転入
力端に直接またはインピーダンス分割された回路を介し
て接続してなる任意ゲインコントロール回路。(1) Introducing an input signal to a first non-inverting input terminal and outputting an output signal from its output terminal, connecting a variable resistor or a resistance divider circuit between the inverting input terminal of this first amplifier and ground, The movable terminal of this variable resistor or the midpoint of the resistance divider circuit is connected to the inverting input terminal of the second amplifier, the output terminal of this second amplifier is connected to the inverting input terminal of the first amplifier, and the An arbitrary gain control circuit formed by connecting the output terminal of the first amplifier to the non-inverting input terminal of the second amplifier directly or via an impedance-divided circuit.
入力端と接地間に接続された可変抵抗または抵抗分割回
路の中点との間にコンデンサが直列に接続されることを
特徴とする実用新案登録請求の範囲第１項記載の任意ゲ
インコントロール回路。(2) A capacitor is connected in series between the inverting input terminal of the second amplifier and the midpoint of a variable resistor or resistance divider circuit connected between the inverting input terminal of the first amplifier and ground. An arbitrary gain control circuit according to claim 1 of the utility model registration claim.
れこの抵抗と上記コンデンサとによりバイパスフィルタ
を形成することを特徴とする実用 ゛新案登録請求
の範囲第２項記載の任意ゲインコントロール回路。
−(3) The inverting input terminal of the second amplifier is grounded via a resistor, and the resistor and the capacitor form a bypass filter. circuit.
−
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7464782U JPS58176418U (en) | 1982-05-21 | 1982-05-21 | Arbitrary gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7464782U JPS58176418U (en) | 1982-05-21 | 1982-05-21 | Arbitrary gain control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58176418U true JPS58176418U (en) | 1983-11-25 |
Family
ID=30084062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7464782U Pending JPS58176418U (en) | 1982-05-21 | 1982-05-21 | Arbitrary gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176418U (en) |
-
1982
- 1982-05-21 JP JP7464782U patent/JPS58176418U/en active Pending
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