JPS5817629A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS5817629A
JPS5817629A JP56115082A JP11508281A JPS5817629A JP S5817629 A JPS5817629 A JP S5817629A JP 56115082 A JP56115082 A JP 56115082A JP 11508281 A JP11508281 A JP 11508281A JP S5817629 A JPS5817629 A JP S5817629A
Authority
JP
Japan
Prior art keywords
alumite
leads
aluminum
layer
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56115082A
Other languages
Japanese (ja)
Inventor
Tamotsu Usami
保 宇佐美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP56115082A priority Critical patent/JPS5817629A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to FR8211728A priority patent/FR2510307A1/en
Priority to GB08221354A priority patent/GB2105107B/en
Priority to IT22563/82A priority patent/IT1152455B/en
Priority to DE19823227606 priority patent/DE3227606A1/en
Publication of JPS5817629A publication Critical patent/JPS5817629A/en
Priority to GB08402099A priority patent/GB2134709B/en
Priority to GB08402057A priority patent/GB2135121B/en
Priority to SG20186A priority patent/SG20186G/en
Priority to SG18986A priority patent/SG18986G/en
Priority to HK458/86A priority patent/HK45886A/en
Priority to HK466/86A priority patent/HK46686A/en
Priority to HK467/86A priority patent/HK46786A/en
Priority to MY558/86A priority patent/MY8600558A/en
Priority to MY364/87A priority patent/MY8700364A/en
Priority to MY1987228A priority patent/MY8700228A/en
Pending legal-status Critical Current

Links

Classifications

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the moisture resistance of a semiconductor integrated circuit device by treating all leads with alumite by shortcircuiting the leads in case of alumite treating, thereby preventing the local battery effect caused due to the potential difference produced between the leads and forming uniform alumite layers. CONSTITUTION:The exposed surface of a bonding pad 28, the surfaces of an aluminum wires 9 and the surface of an aluminum deposited film 10 on the leads (not shown) are oxidized and formed with alumite layers 11, 12 and 13, respectively. In alumite treating, all the leads are shortcircuited by a shortcircuit unit 29. A bonding pad 28 formed on the pellet 1 die bonded onto a tab lead 2 is connected via a bonding wire 9 to the leads 4. The bonded leads 4 are all electically shortcircuited by the unit 29. Accordingly, the alumite layers of high quality can be formed with uniform thickness.

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は半導体集積回路装置およびその製造方法に関す
る。 従来、半導体集積回路装置（以下ＩＣと称する）の製造
においては、半導体ペレット上に形成し几ポンディング
パッドと、リード側のポスト部とを電、気的Ｋｔｌｊ続
するボンディングワイヤとして、金＃またｔｉアルミニ
ウム線が使用ちれている。このうち、アルミニウム線は
金線に比べて非常に低価格で済むと共ＶＣ，ポンディン
グパッドとの接合が熱履歴によっても劣化しないという
利点上層する。 そこで、近年のＩＣの製造コストの低減という要求を満
た丁ため、セラミック型パッケージは勿論。 従来金＊Ｖポンディングワイヤとして用すてぃたレジン
モールド型パッケージにおいてもフルミニ９ム耐か用い
られるようになってきている。 しかし、レジンモールド型パッケージではパッケージと
リードとの間の隙間やレジン自体を通してＩＣの外部か
ら内５ｔＩｃ水分が浸透して来るという欠点がある。一
方、アルミニウム巌は水分と接触すると簡単＆ｊＱ食奮
起こし、この結果ＩＣの信頼性が低下してしまうという
不具合がある。 そこで、アルミニ９ム紐のコスト的な！Ｊ！ｋｒ有効に
活用するため、アルミニ９五線の耐湿性を同上名ゼてＩ
Ｃの信頼性を高めることが必要となっテキた。、；ｒ：
の具体的方法として、アルミニ９ムリイヤまたはアルミ
ニウム配線の表面をアルマイト処理して酸化皮膜を形成
することが特開昭５２−１１７５５１号公報および特開
昭５３−９４７０号公報により提案逼れている。 しかしながら、これらの従来技術においては、効率的か
つ実用的なアルマイト処理を行うことはできず、耐湿性
を十分向上芒ゼることができなかった。丁なわち、前記
従来技術では、（１）アルマイト層の形成が効率的に行
われない、（２）　　アルマイト層の膜厚が不均一であ
る。（３）　　アルマイト層の膜質があまシ良好ではな
い等の問題点があり、また、七の原因も必ずしも明らか
ではなかった。 本発明は上述した問題点を生ずる原因を解明して上記間
燻点を解消しようとするものであろう本発明者の研究に
よれば、上記した問題点を生ずる要因は、半導体基板内
の異なる半導体領域に各々のリードか接ａ−ａれている
ことによって各リード間に生ずる電位差にあることがわ
かった。丁なわち、半導体基板内で各半導体領域が形成
するＰＮ接合部で生ずる電位差および各半導体領域とア
ルミニ９ム配線層の接続部で生ずる接触電位差の代数和
が各ポンディングパッドの相対的な電位差となって現わ
れてくる。ボンディングの条件は全リードで同一である
から、このポンディングパッドの電位差はそのまま各リ
ード間の相対的な電位差となる。そして、この様な状態
でアルマイト処理を行うためＶＣ＃化雰囲気中丁なわち
ウェットな雰囲気中［ｒＩＩｔ＜と、リード間の電位差
および雰囲気中の水蒸気か夫々１Ｍ離における２つの物
質の間の接触電位差および溶媒に相当する働きｔして１
等価的に局部的な１池を構成していることかわかった。 そして、このような局所電池の効果によってアルマイト
処Ｂ！カ良好に行なわれないことがわかった◇ 例えばある電位の妃１のボンティングパッドに、これよ
シ尚い電位を有する＃２のポンディングパッドが接続さ
れている場合には、本発明者の行った実験によれば、上
記第１のパッド上のアルマイト層の形成速度はｓ１！２
のパッド上よ抄大きく、厚いアルマイト層が形成場れて
いることがわかつ′ｆＣウアルマイト層は酸化雰囲気丁
なわちウェットな雰囲気中の水蒸気とアルミニ９ム（ム
ｔ）との間で起る酸化反応によって形成場れるが、本発
明者によれば、上記問題を生ずる原因は、この酸化反応
の過程で生ずる電子が相対的に高い電位側（第２のパッ
ドＩＩ）Ｋ引きつけられるためであることがわかった。 丁なわち、Ｉｌｌのパッドで生じた電子は第２のパッド
側に引きつけられ、この結果、第１のパッドではＷ＋が
酸化反応の系外に除かれるためにムｔのイオン化が進ん
で酸化（アルマイト化）し易くなるのに対し、第２のパ
ッドでは過剰な１．子のため４ＣＡＡのイオン化が抑え
られて酸化（アルマイト化）しにくくなるためであるこ
とがわかった。 以上のようにポンディングパッド量子なわちリード間の
ｗ１位差が、アルマイト処理によって形成もれるアルマ
イト層の膜厚、膜質が不均一となる要因であり、また効
率的な処理が行なえない要因であることがわかった。 本発明の目的は、前記した研究に基づいてな賂れたもの
であシ、各す−ド間に生じる電位差に起因する局所電池
効果全防止し、効率的なアルマイト処理會行って均一な
アルマイト層全形成し、耐浸性゛を向上さゼることので
きる半導体集積回路装置の製造方法を提供することにあ
る。 以下、本発明會図面に示す実施例にしたがって詳細に！
［Ｉ２明する。第１図から９９図は本発明によるＩＣの
製造方法を示す図である。 まず、Ｐ型のシリコン半導体基板１に、例えば第１図に
示すような半導体素子會周知の方法によって形成する。 この半導体素子はＮＰＮ型バイポーラトランジスタでア
シ、そのコレクタ領域はＮ＋型埋込層１５とＨ−型エピ
タキシャル層１７からなり、そのベース軸域はＰ型領域
１９からなり、そのエミッタ領域はＨ型領域２０からな
る。 Ｃのバイポーラトランジスタ音信の半導体素子と分離す
るために、８１０１からなるフィールド酸化膜１Ｂとこ
の下のＰ＋型チャネルストッパ１６か形成場れてｂる。 このＰ型チャネルストツノ（１６とＮ＋型埋込層１５は
例えば、エピタキシャル層１７形成前に基板１の表面に
イオン打込みなどによシ形成される。また、フィールド
酸化膜１Ｂはエピタキシャル層１７の選択酸化によって
得られる。 以上のような半導体素子を形成した後、全面にＩｌｌの
層間絶縁膜としてＯＶＤ法（ＯｋＬｅｍｉｃａｌｖａｐ
Ｏｒ　Ｄｅｐｏｓｉｔｉｏｎ法、気相化学反応法）によ
って８１０冨膜２１を形成する。そして、コレクタ、ベ
ースおよびエミッタ領域の夫々に対するコンタクトホー
ル２２．２３および２４ｔ−形成する。 次に、第２図に示すように、１層目の配線層を形成する
。丁なわち、　１３１０１膜２１上全而に真空蒸着法に
よってアルミニ９五層全２μ鶏の厚さに形成し、これｔ
所望の形状にパターニングして、１層目のアルミニウム
配線層２５．２６に形成する。 次に、第３図に示すように、２層目の配線層およびポン
ディングパッド全形成する。まず１ｗ、２０眉間絶縁膜
として全面にＯＶＤ法により８１０！膜５を形成する。 そして所望の場所にコンタクトホールを開窓した後、８
１０官膜５上全面に１蟹シリコンおよび１％銅入りアル
ミニワ五層を真空蒸着法によって４μ溝の厚さに形成し
、これを所望の形状にパターニングして、２層目（上層
）のアルミニウム配線層６．２７とポンディングパッド
２ｓ５−形成する。このシリコンはアルミニウムが浅い
接合を形成する半導体領域に接する部分１例えばアルミ
ニウム配線層２７がエミッタ領域２０へ接する部分にお
いて、熱処理によって相互に拡散反応して浅い接合全破
壊したりすることｔ防止するため４Ｃｔｉ加されるもの
であり、一方、＠はアルミニワム配線カエレクトロマイ
グレーションによって断線？生じたりすることを防止す
るために添加もれるものである。 次に、第４図に示すように、１目目のアルマイト処理を
行ってアルマイト層７會形成する。つエバー全体を温度
１２Ｌ）Ｃ，水蒸気圧２気圧の雰囲気中［１０分間放壇
することによシ、）くターニングされたアルミニ９ム配
線層６，２７およびポンディングパッド２Ｂの算出した
面に、その算出している部分に−ｅｌｆ化することＫよ
ってアルマイト層７′に形成する。アルマイト層は主と
してムを雪ＯＳからなる。このアルマイト層は、後に形
成される最終保繰展下にあって、アルミニ９ム配線層６
．２７の腐食を防止する４Ｍ５ｉ展として働くものであ
り、籍に最終保護膜に欠陥が生じた場合の腐食防止に１
効なものである。 次に、第５図に示すように、最終堡護膜としてリンシリ
ケート−ガラス膜（以下、Ｐ８（）膜という）゛８ｔ−
ウェハー上全面圧Ｏ’ＶＤ法により８０００ムの厚さに
形成する。 次［，４６図に示すように、ポンプイングツくラド２Ｂ
上のアルマイト層７およびｐｓｅ＃［８ｋ。 プラズマエツチング等により除去し、ボンティングパッ
ド２Ｂのアルｉ　二９ム表面′ｋｊｌ出さゼる。 以上のように最終保護膜に櫟われた９工／’−にダイ曾
ングにより個々のペレットに分離し、嘔らに各ペレット
をリードフレームのタブリード上にダイボンディングす
る。 そして、ペレット上のポンプイングツ（ラドおよびリー
ドフレームの外部接続リードにアルミニ９ムワイＪｆｐ
９の両端ｔそれぞれボンディングする。 このアルミニ９ムワイヤは、直径３０ｐｍの１％シリコ
ンおよび１％銅入りアルミニウムからなるものである。 このアルミニ９ムワイヤとしてはポンディングパッド２
Ｂと同一のイオン化傾向上層するものが使用逼れる。こ
のようにすることによって、後に述べる２回目のアルマ
イト処理の際にこれらのイオン化傾向の違いによって生
ずる局所電池効果を防止し、良質なアルマイト層を均一
な膜厚に形成できる。なお、仁のワイヤボンディングも
れた状態は、＃Ｉ７ム図、第７Ｂ図および第８図から明
らかであろう。 次に、第７ム図に示すように、２回目のアルマイト処理
を行って、アルマイト層１１．１２および１３’に形成
する。まず、アルマイト処理を行う前処理として、ポン
プイングツ（ラドｚ８の露出面。 了ルミニウムワイヤ２９の表面および図外のＩ）　−ド
上のアルミニ９ム蒸５１１１１０（第８図参照）の表面
に自然に形成されているアル７４１層を除く。 これは、例えばシェラ酸液中に浸漬してエツチングする
ことで除去できる。この前処理は、後に形成場れるアル
マイト層の膜質を緻密なものにし。 均一な膜厚に形成するのに有効である。次に、ペレット
がボンディング逼れたリードフレーム全体The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same. Conventionally, in the manufacture of semiconductor integrated circuit devices (hereinafter referred to as IC), gold or gold is used as a bonding wire that is formed on a semiconductor pellet and electrically and electrically connects a bonding pad to a post portion on the lead side. Ti aluminum wire is used up. Among these, aluminum wires have the advantage that they are much cheaper than gold wires and that their bonding with VC and bonding pads does not deteriorate due to thermal history. Therefore, in order to meet the recent demand for lower IC manufacturing costs, ceramic type packages are of course available. Full mini-9mm resistance has come to be used even in resin mold type packages, which were conventionally used as gold*V bonding wires. However, the resin mold type package has the disadvantage that moisture permeates from the outside of the IC through the gap between the package and the leads and through the resin itself. On the other hand, there is a problem in that aluminum can easily swell when it comes into contact with moisture, resulting in a decrease in the reliability of the IC. Therefore, the cost of aluminum 9mm string! J! In order to make effective use of the aluminum 9th staff, the moisture resistance of the aluminum 9th staff has been improved.
It became necessary to increase the reliability of C. ,;r:
As a specific method, it has been proposed in JP-A-52-117551 and JP-A-53-9470 to form an oxide film by alumite-treating the surface of an aluminum 9mm layer or aluminum wiring. However, in these conventional techniques, it was not possible to perform an efficient and practical alumite treatment, and it was not possible to sufficiently improve moisture resistance. Specifically, in the conventional technique, (1) the alumite layer is not formed efficiently, and (2) the thickness of the alumite layer is non-uniform. (3) There were problems such as the film quality of the alumite layer being not very good, and the cause of item 7 was not necessarily clear. The present invention attempts to eliminate the smoke point by elucidating the causes of the above-mentioned problems.According to the research of the present inventor, the causes of the above-mentioned problems are caused by different factors within the semiconductor substrate. It has been found that there is a potential difference generated between each lead due to the fact that each lead is connected a-a to the semiconductor region. In other words, the algebraic sum of the potential difference occurring at the PN junction formed by each semiconductor region in the semiconductor substrate and the contact potential difference occurring at the connection between each semiconductor region and the aluminum wiring layer is the relative potential difference of each bonding pad. It appears as. Since the bonding conditions are the same for all leads, the potential difference between the bonding pads becomes the relative potential difference between each lead. In order to carry out alumite treatment in such a state, contact between two substances in a VC # atmosphere, that is, a wet atmosphere [rIIt<, and a potential difference between the leads and water vapor in the atmosphere at a distance of 1 M, respectively. The force corresponding to the potential difference and the solvent t is 1
It was found that it equivalently constitutes one local pond. And, due to the effect of such a local battery, alumite treatment B! ◇For example, when bonding pad #2, which has a higher potential, is connected to bonding pad #1, which has a certain potential, the inventor's According to the experiment conducted, the formation speed of the alumite layer on the first pad is s1!2
It can be seen that a large and thick alumite layer is formed on the pad of the pad.The alumite layer occurs between water vapor and aluminum in an oxidizing atmosphere, that is, a wet atmosphere. According to the present inventor, the cause of the above problem is that the electrons generated in the process of this oxidation reaction are attracted to the relatively high potential side (second pad II). I understand. In other words, the electrons generated at the pad Ill are attracted to the second pad side, and as a result, W+ is removed from the oxidation reaction system at the first pad, so the ionization of Mut progresses and oxidation ( The second pad has excessive 1. It was found that this is because the ionization of 4CAA is suppressed due to the presence of carbon atoms, making it difficult to oxidize (alumite). As mentioned above, the bonding pad quantum, that is, the W1 position difference between the leads, is the reason why the thickness and quality of the alumite layer formed and leaked during alumite treatment are non-uniform, and it is also the reason why the process cannot be carried out efficiently. I found out something. The purpose of the present invention is to completely prevent the local battery effect caused by the potential difference generated between each electrode, and to perform an efficient alumite treatment to produce uniform alumite. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device that can form all layers and improve its immersion resistance. Hereinafter, details will be given according to the embodiments shown in the drawings of the present invention!
[I2 will be explained. 1 to 99 are diagrams showing a method of manufacturing an IC according to the present invention. First, a semiconductor device is formed on a P-type silicon semiconductor substrate 1 by a method well known in the semiconductor device industry, as shown in FIG. 1, for example. This semiconductor element is an NPN bipolar transistor whose collector region consists of an N+ type buried layer 15 and an H- type epitaxial layer 17, whose base axis region consists of a P type region 19, and whose emitter region consists of an H type region. Consists of 20. In order to isolate the bipolar transistor from the semiconductor element of C, a field oxide film 1B made of 8101 and a P+ type channel stopper 16 thereunder are formed. The P type channel horns (16) and the N+ type buried layer 15 are formed, for example, by ion implantation into the surface of the substrate 1 before the epitaxial layer 17 is formed. After forming the semiconductor element as described above, an interlayer insulating film of Ill is formed on the entire surface using an OVD method (OkLemical Vap
The 810 thick film 21 is formed by a vapor phase chemical reaction method (or deposition method, vapor phase chemical reaction method). Contact holes 22, 23 and 24t are then formed for the collector, base and emitter regions, respectively. Next, as shown in FIG. 2, a first wiring layer is formed. That is, five layers of aluminum 9 were formed on the entire surface of the 13101 membrane 21 to a thickness of 2μ by vacuum evaporation.
It is patterned into a desired shape and formed into first aluminum wiring layers 25 and 26. Next, as shown in FIG. 3, the second wiring layer and bonding pads are completely formed. First, 1W, 20 glabellar insulating film was applied to the entire surface using the OVD method with 810! A film 5 is formed. After opening the contact hole at the desired location, 8
10 Five layers of silicon and 1% copper-containing aluminum wire are formed on the entire surface of the membrane 5 to a thickness of 4 μm by vacuum evaporation, patterned into a desired shape, and the second layer (upper layer) of aluminum is formed. A wiring layer 6.27 and a bonding pad 2s5 are formed. This silicon is used to prevent complete destruction of the shallow junction due to a mutual diffusion reaction caused by heat treatment in the portion 1 where aluminum contacts the semiconductor region forming a shallow junction, for example, the portion where the aluminum wiring layer 27 contacts the emitter region 20. 4Cti is added, and on the other hand, @ is disconnected due to aluminum wiring electromigration? It is added to prevent this from occurring. Next, as shown in FIG. 4, a first alumite treatment is performed to form seven alumite layers. The entire surface of the aluminum 9m wiring layer 6, 27 and the bonding pad 2B was exposed to a temperature of 12 L) C and a water vapor pressure of 2 atm for 10 minutes. , the alumite layer 7' is formed by converting the calculated portion to -elf. The alumite layer is mainly made of silica OS. This alumite layer is under the final preservation process to be formed later, and the aluminum 9m wiring layer 6
．． It acts as a 4M5i exhibition to prevent corrosion of
It is effective. Next, as shown in FIG.
The film is formed to a thickness of 8000 μm using the O'VD method over the entire surface of the wafer. Next [,46 As shown in Fig.
The top alumite layer 7 and pse#[8k. It is removed by plasma etching or the like to expose the aluminum surface of the bonding pad 2B. As described above, the pellets are separated into individual pellets by die cutting after 9 steps/'- of the final protective film, and then each pellet is die-bonded onto the tab leads of the lead frame. Then, pumping tubes on the pellet (Aluminum 9mm Jfp on the external connection lead of the Rad and lead frame)
Bond each end t of 9. The aluminum 9 mil wire was made of 1% silicon and 1% copper aluminum with a diameter of 30 pm. This aluminum 9mm wire has a bonding pad of 2.
Those that have the same ionization tendency as B are mostly used. By doing so, it is possible to prevent the local battery effect caused by the difference in ionization tendency during the second alumite treatment to be described later, and to form a high-quality alumite layer with a uniform thickness. Incidentally, the state in which the wire bonding is leaking will be clear from Figure #I7, Figure 7B, and Figure 8. Next, as shown in FIG. 7, a second alumite treatment is performed to form alumite layers 11, 12 and 13'. First, as a pre-treatment for alumite treatment, the exposed surface of the aluminum wire 29 (the surface of the aluminum wire 29 and I (not shown)) is naturally coated on the surface of the aluminum wire 511110 (see Figure 8). The formed Al 741 layer is removed. This can be removed, for example, by immersing it in Scherer's acid solution and etching it. This pretreatment makes the quality of the alumite layer that will be formed later denser. This is effective in forming a film with a uniform thickness. Next, the pellet is bonded to the entire lead frame.

【温度１２０
℃、水蒸気圧２気圧の雰囲気中に放置することＫよって
、２回目のアルマイト層を形ｉＥＴる。つまシ、ポンデ
ィングパッド２Ｂの露出面、アルミニ９ムワイヤ９の表
面および図外のリード上のアルはニワム蒸Ｎ展１０（第
８図参照）の表向に、七の表面′に酸化してそれぞれア
ルマイト層１１．１２および１３を形成する。アルマイ
ト層は主としてムｔＳＯ嘗　からなる。このアルマイト
層１１．１２ｊＰよび１３はそれぞれボンデイングパ：
／ド２８．プルミニ９ムワイヤ９および図外のリード上
のアルミニ９ム蒸着膜１０の腐食を防止する保護膜とし
て働くものである。−また、アル７４１層１１．１２お
よび１３が連続して一体に形成場れているのみならず、
先に１回目のアルマイト処理によって形成された最終保
護膜Ｂ下のアルマイト層７とも連続して一体に形成され
ていることＫよって、後に述べるように、＃：食防止の
ための大きな効果を有する。 本発明によれば％Ｃの２回目のアルマイト処理を行うに
あたって、第７Ｂ図に示すように、全リードを短絡部２
９によって短絡しておくことが特徴的である。タブリー
ド２上にダイボンディングされたベレツ）１に形成され
ているポンディングパッド２Ｂとリード番とは、ボンデ
ィングワイヤ９によって接続されている。そして、ボン
ディングされ２１７−ド４は全て短絡部２９によって電
気的に短絡１れている。このように全リードを短絡する
ことによって、′１アルマイト処理の際にこれらリード
間の電位差によって生ずる局所電池効果を防止し、良質
なアルマイト層を均一な膜厚に形成するのに有効である
。 次［、第８図に示すようＫ、モールドレジン１４によっ
て全体を封正し、引き続き短絡部２９全切断除去してリ
ート°４を所望の形状にする。 次に、第９図に示すように、モールドされたＩＯ會例え
ば硫ＩＰ（Ｈｓ８０＊）溶液に浸漬して、１】−ド４の
表面の酸化膜を除去する。丁なわち、アルマイト処理を
行うために水蒸気雰囲気中に置いたために、４２アロイ
（又はリン青１ｉｅ）からなるリード番の表面上に形成
された不所望な酸化膜管。 アルマイト層とこの酸化膜との性質の違いを利用してこ
の酸化膜のみを選択的に除去する。このために、アルマ
イト層には作用ゼず、仁の酸化膜のみ會エツチングする
溶液として硫酸溶液が用いられ、この溶液に約５分間浸
漬することでリード４上の酸化膜が除かれる。このとき
、硫蒙溶液がモールドレジン内に浸入することがあって
も、アルミニウム蒸５１ｍ、アルミニワムワイヤ、ボン
デインクパッドＳｔどはアルマイト層によって保護チれ
ているので、全く影響はない。 以上説明したように、本発明によれば、ワイヤボンディ
ング後にアルミニウム蒸Ｍ膜、アルミニウムワイヤ、ポ
ンディングパッドをアルマイト処理する際にアルミニウ
ムワイヤが接続される全す−ド會短絡することによって
、これらの表面に良質なアルマイト層を均一な膜厚に効
率よく形成できるものである。既に述べたように、各リ
ード間に各半導体領域等への接続の具合によって生ずる
電位差に起因する局所電池効果がアルマイト処理を良好
に行えない原因である。したがって、全リードを短絡し
てリード間の電位差紫黒く丁ことによシ、全体のアルマ
イト層の成長速度全回じにでき、均一なＭ厚にできる。 また、酸化反応も表面全体で同−速度で均−ｔＣ遍むの
で良質なアルマイト層か均一の膜厚で得られる。さらＫ
、従来とは異なシ均一な膜厚にできるため、必骸な膜厚
１ｃｍ有るために他方か必要な映厚以上になってしまう
ような不都合はなく効率的なアルマイト処理かｔ＝１ｔ
ｉである。 また１本発Ｉ３１［よれば、レジンモールド後に、リー
ド表向にアルマイト処理時に形成された酸化膜をアルマ
イト層との性質の違いｔ利用して除去できる。したがっ
て、少々くともレジンモールド外に？連出しているリー
ド表面の酸化膜は完全に除去でき、リードの清浄な表面
を露出できる。このため、電気的接触を良好に保つこと
ができＩＣの信頼性會向上できる、また、リード表面に
半田付けによって半田層全形成しようとする場合には、
％に半田付けのためにリードの表面処１！Ｊ’を行なわ
ずとも、良好な半田付けができる。 さらに、本実施例によれば、ワイセボンテイング後のア
ルマイト処理に先立って、自然にアルミニ９ム表向に形
成ちれたアルマイト層全除去しているため、アルマイト
層を緻密に、かつ均一な膜厚に形成できる。 以上の効果の他に１本実施例によれば、以下のような丁
ぐ１した効果も得ることかできる。ボンティングパッド
を構成するアル、ミニラム配線層とアルミニウムワイヤ
とｔ同一のイオン化傾向１１″有する材質としているた
めに、これら両者の表面に毛らに良質なアルマイト層ｔ
よプ均一な膜厚に効率よ〈形成できるものである。丁な
わち、アルミニウム配線層とアルミニウムワイヤとの材
質の違いによシこれら両者の間に局所！池効果（イオン
化傾向の違いによる）が生じこの局所電池効果によって
もアルマイト層の形成が効率よくできない原因となるこ
ともある、ということが本発明者によって明らかにされ
た。したがって、両者全同一のイオン化傾向を有する材
質としてこれらの間ＩＦＩｉＡ所電池効果か発生するの
ｔ防止しておけば上記したリード間の電位差に基づく局
所電池効果の発生防止と共に完全に局所ｗ旭効果の発生
全防止することができアルマイト層の膜質をより良質に
できかつその膜厚もよシ均一にすることができる。 このような効果會奏するのは、アルミニウム領域への添
加物が銅である場合に限定もれない。つまシ、イオン化
傾向上層する物質を添加物としてアルミニウムからなる
ポンディングパッド６るいはボンディングワイヤのいづ
れか一方に用いた場合には、他の一方にも同一の物質を
添加量れば。 添加物か何であるかにかかわシなく上述の如き効果を得
ることかできる。仁のとき添加量もできるだけ同一の割
合となるようにするのが望ましい。 このように１本実施例によれば、先述の効果と合せてア
ルマイト処理の際に生じる局所電池効果を完全に防止で
き良好なアルマイト層を形成できる。 また、最終保鏝膜下の上層アルミニウム配線層會覆うア
ルマイト層と、アルミニウムワイヤ、ポンディングパッ
ドおよびアルミニワム蒸着膜ｔ−橿うアルマイト層の双
方を形成し、ざらにこれらｔ連続一体化したアルマイト
層としｔことによって、工０の外部から例えばモールド
レジン１４自体又は毛−ルドレジン１４とリード４との
隙間から浸入してくる水分と不純物イオンとによるアル
ミニ９ムの腐食を防止し、極めて耐湿性の良い工Ｃ１ｒ
得ることができる。アルマイト層１１．１２および１３
によって、これらが覆っているポンディングパッド、ア
ルミニ９ムワイヤ９およびアルミニウム蒸Ｍ績１０の腐
食を防止でき１名らにこれらアルマイト層が連続してい
るため上述の３つの領域の境界から腐食が進むようなこ
とはない。また。 モールドレジンの架橋反応や各領域の熱膨張係数の差異
による収縮応力に起因するモールドストレス又は様々な
様械的応力によって最終保護膜８にクラック（割れ）１
ｒ生ずるようなことがあっても。 上層了ルミニウム配線層６の腐食はアルマイト層７によ
って防止ちれる。１らに、アルマイト層７および１１が
連続して一体に形成場れているので。 最終保護膜Ｂの端部とポンディングパッドとの間の隙間
から胸糞が起ることも防止できる。 々お、本発明においては、レジンモールド會行う前に、
柔軟性を持つアンダーコートレジン、例１ｔｆＡＴＶ−
１ルジ７％ｔアンダーコートしてもよい。それによシ、
アルミニワムワイヤがモールドストレスによって断線し
大り、モールドレジンとアルミニウムワイヤが剥離して
水分がペレットに違することｔ防止てき、アルミニウム
の腐食を防止することが可能となる。 また、本発明はレジンモールド型以外のパッケージ、た
とえはセラミック型、ガラス型、キャビティ型等のパッ
ケージにも応用でき、各パッケージの特徴を生かしなが
ら、低コスト化や高信頼化を図ることができる。[Temperature 120
A second alumite layer is formed by leaving it in an atmosphere at a temperature of 2 atm and a water vapor pressure of 2 atm. Al on the exposed surface of the tab, the bonding pad 2B, the surface of the aluminum wire 9, and the leads (not shown) are oxidized to the surface of the aluminum alloy 10 (see Figure 8). Alumite layers 11, 12 and 13 are formed, respectively. The alumite layer mainly consists of MutSO. These alumite layers 11, 12jP and 13 are bonding pads:
/Do28. It functions as a protective film to prevent corrosion of the aluminum 9m deposited film 10 on the pulley 9m wire 9 and leads (not shown). -Also, not only are Al 741 layers 11, 12 and 13 formed continuously and integrally,
It is formed continuously and integrally with the alumite layer 7 under the final protective film B previously formed by the first alumite treatment.Therefore, as described later, #: has a great effect on corrosion prevention. . According to the present invention, when performing the second alumite treatment of %C, as shown in FIG.
It is characteristic that it is short-circuited by 9. The bonding pad 2B formed on the tab 1 die-bonded onto the tab lead 2 and the lead number are connected by a bonding wire 9. The bonded nodes 217-4 are all electrically short-circuited by the short-circuit portion 29. By short-circuiting all the leads in this manner, it is effective to prevent the local battery effect caused by the potential difference between these leads during the '1 alumite treatment, and to form a high-quality alumite layer with a uniform thickness. Next, as shown in FIG. 8, the whole is sealed with mold resin 14, and then the short-circuit portion 29 is completely cut and removed to give the reed 4 a desired shape. Next, as shown in FIG. 9, the molded IO solution is immersed in, for example, a sulfur IP (Hs80*) solution to remove the oxide film on the surface of the 1]-domain 4. In other words, an undesired oxide film tube formed on the surface of the lead number made of 42 alloy (or phosphor blue 1ie) because it was placed in a steam atmosphere for anodizing. Utilizing the difference in properties between the alumite layer and this oxide film, only this oxide film is selectively removed. For this purpose, a sulfuric acid solution is used as a solution that etches only the oxide film on the core without acting on the alumite layer, and the oxide film on the lead 4 is removed by immersing it in this solution for about 5 minutes. At this time, even if the sulfuric solution penetrates into the mold resin, it will not affect the aluminum evaporator 51m, the aluminum wire, the bonding ink pad St, etc. because they are protected by the alumite layer. As explained above, according to the present invention, when anodizing the aluminum vaporized M film, aluminum wire, and bonding pad after wire bonding, all the wires to which the aluminum wire is connected are short-circuited. It is possible to efficiently form a high-quality alumite layer with a uniform thickness on the surface. As already mentioned, the local battery effect caused by the potential difference caused by the connection between each lead to each semiconductor region, etc. is the reason why the alumite treatment cannot be performed satisfactorily. Therefore, by short-circuiting all the leads, the potential difference between the leads can be reduced, and the growth rate of the entire alumite layer can be increased at all times, making it possible to obtain a uniform M thickness. In addition, since the oxidation reaction is uniformly distributed over the entire surface at the same rate, a high-quality alumite layer with a uniform thickness can be obtained. Sara K
, unlike the conventional method, it can be made to have a uniform film thickness, so there is no inconvenience such as one film having a film thickness of 1 cm and the other being more than the necessary film thickness, making it an efficient alumite process.
It is i. Further, according to I31 [1], after resin molding, the oxide film formed on the surface of the lead during alumite treatment can be removed by taking advantage of the difference in properties from the alumite layer. Therefore, a little spider outside the resin mold? The oxide film on the surface of the extended lead can be completely removed, exposing the clean surface of the lead. Therefore, good electrical contact can be maintained and the reliability of the IC can be improved.In addition, when trying to form a complete solder layer on the lead surface by soldering,
Surface treatment of leads for soldering to %1! Good soldering can be achieved without performing J'. Furthermore, according to this example, the alumite layer that is naturally formed on the surface of the aluminum 9mm is completely removed prior to the alumite treatment after Wise Bonding, so the alumite layer can be formed into a dense and uniform layer. Can be formed into a thick film. In addition to the above-mentioned effects, according to this embodiment, the following advantages can also be obtained. Since the bonding pad is made of a material that has the same ionization tendency 11" as the aluminum wiring layer and the aluminum wire, a high-quality alumite layer is coated on the surface of both.
It can be efficiently formed to a uniform film thickness. In other words, due to the difference in material between the aluminum wiring layer and the aluminum wire, there is a local area between the two! The inventor of the present invention has clarified that a pond effect (due to a difference in ionization tendency) occurs and that this local cell effect may also be a cause of inability to form an alumite layer efficiently. Therefore, if both materials have the same ionization tendency and prevent the IFIiA battery effect from occurring between them, the local battery effect due to the potential difference between the leads can be prevented and the local Asahi effect can be completely eliminated. can be completely prevented from occurring, and the quality of the alumite layer can be improved, and its thickness can also be made more uniform. Such an effect is produced not only when the additive to the aluminum region is copper. However, if a material with ionization tendency is used as an additive in either the bonding pad 6 made of aluminum or the bonding wire, the same amount of the material should be added to the other one. The above-mentioned effects can be obtained regardless of the additives used. When using kernels, it is desirable to keep the amount added in the same ratio as possible. As described above, according to this embodiment, in addition to the above-mentioned effects, it is possible to completely prevent the local battery effect that occurs during alumite treatment, and form a good alumite layer. In addition, an alumite layer covering the upper aluminum wiring layer under the final protective film and an alumite layer covering the aluminum wire, the bonding pad, and the aluminum evaporated film are formed, and these alumite layers are roughly integrated into one continuous layer. This prevents corrosion of the aluminum 9 due to moisture and impurity ions entering from the outside of the workpiece, for example, through the mold resin 14 itself or the gap between the mold resin 14 and the lead 4, making it extremely moisture resistant. Good engineering C1r
Obtainable. Alumite layers 11, 12 and 13
This prevents corrosion of the bonding pad, aluminum wire 9, and aluminum evaporation layer 10 that are covered by these layers.Since these alumite layers are continuous, corrosion progresses from the boundary between the three areas mentioned above. There is no such thing. Also. Cracks (cracks) in the final protective film 8 due to mold stress caused by crosslinking reaction of the mold resin and shrinkage stress due to differences in thermal expansion coefficients of each region, or various mechanical stresses.
Even if something like that happens. Corrosion of the upper lumen wiring layer 6 is prevented by the alumite layer 7. First, the alumite layers 7 and 11 are formed continuously and integrally. It is also possible to prevent feces from occurring from the gap between the end of the final protective film B and the padding pad. In the present invention, before the resin molding process,
Flexible undercoat resin, example 1tfATV-
It may be undercoated with 7% t. Besides,
This prevents the aluminum wire from breaking due to mold stress, causing the mold resin and the aluminum wire to separate and turning moisture into pellets, thereby making it possible to prevent corrosion of the aluminum. Furthermore, the present invention can be applied to packages other than resin mold type, such as ceramic type, glass type, cavity type packages, etc., and it is possible to reduce costs and increase reliability while taking advantage of the characteristics of each package. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図〜１ｍ１９図は本発明による半導体集積回路装置
の製造プロセスを順次示す図である。 １・・・半導体基板、２・・・タブリード、４・・・リ
ード。 ６・・・上層アルミニウム配線層、７・」・アルマイト
層８・・・Ｉ終保１ｉｔ　９・・・アルミニウムワイヤ
、１１゜１２．１３・・・アルマイト層、１４・・・モ
ールドレジン、２Ｂ・・・ポンディングパッド、２９・
・・短絡部、３０・・・ｉｌ酸の溶液。 代理人　弁理士　簿　１）利　幸 第　　１　　１−７； 第　　２　１ 第７β図 第　　８　　図 第　　９　　図1 to 1m19 are diagrams sequentially showing the manufacturing process of a semiconductor integrated circuit device according to the present invention. 1... Semiconductor substrate, 2... Tab lead, 4... Lead. 6... Upper aluminum wiring layer, 7... Alumite layer 8... I final warranty 1it 9... Aluminum wire, 11°12.13... Alumite layer, 14... Mold resin, 2B...・・Ponding pad, 29・
...Short circuit part, 30...Il acid solution. Agent Patent Attorney Register 1) Toshiyuki No. 1 1-7; No. 21 Fig. 7β Fig. 8 Fig. 9

Claims (1)

【特許請求の範囲】 １、アルミニウム材料よりなるポンディングパッドに了
ルミニウムワイヤをボンディングした後。 ポンディングパッドの露出向およびアルミニウム９イヤ
の表向會アルマイト処理する際に、全り一ドを短絡して
アルマイト処ｍｔ−行う半導体集積回路装置の製造方法
。 ２、アルミニウム材料よ動なるポンディングパッドにア
ルミニウムワイヤをボンディングした後、ポンディング
パッドの露出面およびアルミニウムワイヤの表面會アル
マイト処理する際に、全り一ド會短絡してアルマイト処
理を行い、パッケージ内に封止した後、リードの表面酸
化膜を該表面酸化膜とアルマイトとの材質の違いｔ利用
して洗浄により除去する半導体集積回路装置の製造方法
う[Claims] 1. After bonding the aluminum wire to the bonding pad made of aluminum material. A method for manufacturing a semiconductor integrated circuit device, in which when performing alumite treatment on the exposed side of a bonding pad and on the surface side of an aluminum layer, all leads are short-circuited and alumite treatment is performed. 2. After bonding the aluminum wire to the bonding pad made of aluminum material, when anodizing the exposed surface of the bonding pad and the surface of the aluminum wire, short-circuit all the wires once and then perform the alumite treatment. A method for manufacturing a semiconductor integrated circuit device, in which the surface oxide film of the lead is removed by cleaning using the difference in material between the surface oxide film and alumite.
JP56115082A 1981-07-24 1981-07-24 Manufacture of semiconductor integrated circuit device Pending JPS5817629A (en)

Priority Applications (15)

Application Number Priority Date Filing Date Title
JP56115082A JPS5817629A (en) 1981-07-24 1981-07-24 Manufacture of semiconductor integrated circuit device
FR8211728A FR2510307A1 (en) 1981-07-24 1982-07-05 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE
GB08221354A GB2105107B (en) 1981-07-24 1982-07-23 Semiconductor device and fabrication method thereof
IT22563/82A IT1152455B (en) 1981-07-24 1982-07-23 SEMICONDUCTOR DEVICE AND PROCEDURE FOR ITS MANUFACTURE
DE19823227606 DE3227606A1 (en) 1981-07-24 1982-07-23 SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION
GB08402099A GB2134709B (en) 1981-07-24 1984-01-26 Semiconductor device and fabrication method thereof
GB08402057A GB2135121B (en) 1981-07-24 1984-01-26 Semiconductor device and fabrication method thereof
SG20186A SG20186G (en) 1981-07-24 1986-03-03 Semiconductor divice and fabrication method thereof
SG18986A SG18986G (en) 1981-07-24 1986-03-03 Semiconductor device and fabrication method thereof
HK458/86A HK45886A (en) 1981-07-24 1986-06-19 Semiconductor device and fabrication method thereof
HK466/86A HK46686A (en) 1981-07-24 1986-06-19 Semiconductor device and fabrication method thereof
HK467/86A HK46786A (en) 1981-07-24 1986-06-19 Semiconductor device and fabrication method thereof
MY558/86A MY8600558A (en) 1981-07-24 1986-12-30 Semiconductor device and fabrication method thereof
MY364/87A MY8700364A (en) 1981-07-24 1987-12-30 Semiconductor device and fabrication method thereof
MY1987228A MY8700228A (en) 1981-07-24 1987-12-31 Semiconductor device and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56115082A JPS5817629A (en) 1981-07-24 1981-07-24 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5817629A true JPS5817629A (en) 1983-02-01

Family

ID=14653734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56115082A Pending JPS5817629A (en) 1981-07-24 1981-07-24 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5817629A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3882965A1 (en) * 2020-03-17 2021-09-22 Kabushiki Kaisha Toshiba Semiconductor device with an electromigration reducing area

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3882965A1 (en) * 2020-03-17 2021-09-22 Kabushiki Kaisha Toshiba Semiconductor device with an electromigration reducing area
JP2021150374A (en) * 2020-03-17 2021-09-27 株式会社東芝 Semiconductor device and inspection device

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