JPS581754B2 - electronic clock device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an electronic timepiece device.

In conventional electronic clock devices, "hour", "minute",
One idea is to have a switch for adjusting the time corresponding to the seconds.

In this way, with separate switches for time adjustment for each time unit of "hour", "minute", and "second", it is not possible to adjust the time independently for each time unit. Although it has the advantage of being very easy to operate, it has the problem that a large number of correction switches not only complicates the structure but also increases cost.

For this reason, the time is divided into time divisions corresponding to "hour", "minute", and "second", and the time is adjusted in the order of "hour" → "minute" → "second" using one or two switches. There is something that allows you to do this.

However, as mentioned above, when the time is adjusted using a small number of switches, it is not possible to stop the adjustment midway through the time adjustment operation, and for example, when adjusting the time difference when going overseas. case etc. "minute" or "
Even if you do not need to adjust the time in seconds, be sure to use the hour →
Correction operations must be performed in the order of "minutes" → "seconds", which is cumbersome.

The present invention has been made in view of the above points, and an object of the present invention is to provide an electronic timepiece device that can arbitrarily cancel the time adjustment operation when adjusting the time using a small number of switches.

An embodiment of the present invention will be described below with reference to Figure F.

Figure 1 shows the general configuration of the entire clock.
a reference signal generation circuit 2 that generates a reference pulse signal; a frequency division circuit 3 that divides the reference signal output from the reference signal generation circuit 2 to obtain, for example, a 32 Hz clock pulse φ and a pulse signal with a period of 1 second; A sexagesimal second counter 4 that counts the 1 second signal output from the frequency dividing circuit 3 to obtain second information, a pulse signal of 2 seconds in period and 1 minute;
Decimal 1 to obtain minute information and a pulse signal with a period of 10 minutes by counting the 1 minute signal given through the AND circuit 8.
a minute digit counter 5; a hexadecimal 10 minute digit counter 6 which counts the 10 minute signal given from the 1 minute digit counter 5 via an AND circuit 9 to obtain information in units of 10 minutes and a pulse signal with a period of 1 hour; It consists of a 12-digit time counter 7 which counts the 1-hour signal given from the 10-minute digit counter 6 via an AND circuit 10 to obtain hour information.

The time information output from each of the counters 4 to 7 is sent to the decoder/driver 11 and digitally displayed on the display section 12.

Thus, the gates of the AND circuits 8 to 10 are controlled by control signals I1 to I3 supplied from the control circuit 13.

This control circuit 13 operates in synchronization with the clock pulse φ given from the frequency dividing circuit 3 and the 2-second signal given from the second counter 4 when the correction control switch sb and the time correction switch Sa are operated, although the details will be described later. A correction signal is given to the hour counter 7, 10 minute digit counter 6, and 1 minute digit counter 5, a second clear signal is given to the frequency divider 3 and second counter 4, and a second clear signal is given to the AND circuits 8 to 10. provides control signals I1-I3 as described above.

Next, details of the control circuit 13 will be explained with reference to FIG.

In FIG. 2, 21 is a delayed flip-flop that reads the operation output of the correction control switch sb, and the inverter 2
The correction control switch sb operates in synchronization with the clock pulse φ applied through the correction control switch sb, and has the function of preventing the influence of chattering of the correction control switch sb.

The set output of the flip-flop 21 is a trigger flip-flop 2 which operates inverted every time an input signal is applied.
The counter signal is supplied to the trigger input terminal T of No. 3, and the reset terminal R of the flip-flops 25 and 26 constituting the Johnson counter 24.

Furthermore, the Q side output of the flip-flop 23 is connected to the AND circuit 2.
7 to 30 and the inverter 3.
1, applied to one input terminal of NAND circuits 32 and 33.

The output of the inverter 31 is taken out as a control signal 1 for the AND circuits 1 and 0 in FIG.

Further, the NAND circuit 32 receives the Q side output of the flip-flop 25 at its other input terminal, and outputs a control signal (2) to the AND circuit 9.

Further, the NAND circuit 33 receives the Q side output of the flip-flop 26 at its other input terminal, and outputs a control signal (3) to the AND circuit 8.

Further, the AND circuits 21 to 30 are selected and designated by the output of the counter 24, and the output of the AND circuit 27 is sent to the time counter 7 as a correction signal in units of hours, and the output of the AND circuit 28 is sent to the 10-minute digit. ``10 minutes'' to Kaunk 6
As for the unit correction signal, the output of the AND circuit 29 is given to the 1-minute digit counter 5 as a correction signal in units of "1 minute", and the output of the AND circuit 30 is given to the frequency divider circuit 3 and the seconds counter 4 as a seconds clear signal. ing.

Thus, in the Johnson counter 24, the Q-side output of the flip-flop 25 is supplied to the data input terminal D of the flip-flop 26, and the Q-side output of the flip-flop 26 is supplied to the data input terminal D of the flip-flop 25. The .26Q side output is applied to the third input terminal of the AND circuit 27 via the AND circuit 34.

And the Q side output of the flip-flop 25 is the AND circuit 2.
8.29, and the Q side output is applied to the second input terminal of the AND circuit 30.

In addition, the Q side output of the flip-flop 25 is connected to the AND circuit 2.
9 and the third input terminal of the AND circuit 30 , and the Q side output is applied to the fourth input terminal of the AND circuit 28 .

That is, when the counter 24 is reset, the AND circuit 27 is specified via the AND circuit 34, when the counter 24 counts one input pulse, the AND circuit 28, and when the counter 24 counts two input pulses, the AND circuit 29 and three input pulses are specified. Connections are made between the AND circuits 27 to 30 and the counter 24 so that the AND circuit 30 is specified when this occurs.

On the other hand, the operation output of the time correction switch Sa is applied to the data input terminal D of the delayed flip-flop 35, and the Q1 law output of this flip-flop 35 is applied to the data input terminal D of the delayed flip-flop 36. It is sent to the clock input terminal C of the flip-flop 25,26.

The flip-flops 35 and 36 operate in synchronization with the clock pulse φ applied via the inverter 22.

Then, the Q side output of the flip-flop 35, the Q output of the flip-flop 36, the clock pulse φ, and the AND circuit 3.
The output of 4 is sent to flip-flop 2 via AND circuit 37.
It is applied to the reset terminal R of No. 3.

In addition, the operation outputs of the switches Sa and Sb are passed through an OR circuit 38 to a 2-second signal generation circuit 39 that generates a signal with a 2-second period.
It is applied to the reset terminal R of the delayed flip-flop 40 constituting the circuit.

This flip-flop 40 has a data input terminal D constantly supplied with a "1" signal, and a clock input terminal C supplied with a 2-second signal from the second counter 4 via an inverter 41.

Then, the Q side output of the flip-flop 40 is applied to the AND circuit 42 together with the 2 second signal, and the AND circuit 42
The outputs of are applied to the second input terminals of AND circuits 27-29.

Next, the operation of the present invention configured as described above will be explained.

In a normal state, that is, a state in which the correction control switch Sb is not operated, the frisop flop 23 is in a reset state, and the output at its output terminal Q is "0".

Therefore, the control signals (1) to (3) outputted from the inverter 31 and the NAND circuits 32 and 33 are all "1", opening the gates of the AND circuits 8 to 10.

Therefore, each of the counters 4 to 7 of the timekeeping section 1 counts the pulse signals outputted from the reference signal generation circuit 2 via the frequency dividing circuit 3 and outputs timekeeping information for "hours", "minutes", and "seconds". ing.

The clock information output from the counters 4 to 7 is sent to the decoder/driver 11 and digitally displayed on the display section 12.

When adjusting the time, first, the correction control switch sb is closed.

The operation output of this switch sb is read into the flip-flop 21 in synchronization with the clock pulse φ.

As a result, "1" is output from the Q side output terminal of the Frisop flop 21.
A signal is output, and the flip-flop 23 is set by the rising edge of the signal.

In other words, the operation of switch sb or the flip-flop 23
is memorized.

When the switch sb is opened, the flipflop 21 reads a "0" signal with the next clock pulse φ and enters the reset state.

Since the flip-flop 23 outputs a "1" signal, the control signal output from the inverter 31 becomes "0" and the gate of the AND circuit 10 is closed.
Input from the 10 minute digit counter 6 to the hour counter 7 is prohibited.

Furthermore, the output signal of the flip-flop 23 is output from the NAND circuit 3.
2.33, but at this point the counter 24 is in a reset state and the Nante circuit 32.
Since the "0" signal is given to the other input terminal of the NAND circuit 32, the control signal ■2, which is output from the NAND circuit 33,
■Both 3 are held in the “1” state, and the AND circuit 8
, 9 gates are open.

Therefore, the 1-minute digit counter 5 and the 10-minute digit counter 6 continue to measure time.

On the other hand, “
The "1" signal is applied to the AND circuits 27 to 30, but at this point, the counter 24 is in the reset state as described above, so the AND circuit 34 outputs the "1" signal and the AND circuit 27 is designated. .

Therefore, the 2 second signal sent from the 2 second signal generation circuit 39 is output from the AND circuit 27 and sent to the time counter 7 as a count up signal.

The 2-second signal generating circuit 39 prohibits the output of the 2-second signal when the switches Sa and Sb are operated, and outputs the 2-second signal after the switch is opened.
The first pulse signal is removed and the next pulse signal is output.

That is, when the switch Sa or sb is closed, the output of the OR circuit 38 becomes "1" as shown in FIG. 3B, and the flip-flop 40 is reset.

When this flip-flop 40 is reset, the Q side output becomes "0", the gate of the AND circuit 42 is closed, and the third
As shown in Figure e, the output of the 2 second signal is prohibited.

Next, when the closed switch is opened, the OR circuit 3 is activated.
8 becomes "0" as shown in FIG. 3b, so when the 2-second signal shown in FIG. 3a is given from the second counter 4, at the falling point, that is, in FIG. The rise of the output of the inverter 41 shown in FIG.
A “1” signal is read into 0.

Therefore, the Q side output of the flip-flop 40 becomes "1" as shown in FIG. 3d, and the gate of the AND circuit 42 is opened.

Therefore, from the next 2 second signal, the AND circuit 42 outputs the signal as shown in FIG. 3e.

In this way, by removing one signal for two seconds immediately after the switch operation, the time adjustment operation can be performed easily and accurately.

Thus, the content of the time counter 7 is counted up by the signal output from the AND circuit 27.

When the contents of the time counter 7 match the correct time due to this count-up, the time correction switch Sa is closed at the instant.

The operation output of this switch Sa is read into the flip-flop 35 in synchronization with the clock pulse φ.

The Q side output of this flip-flop 35 is connected to the counter 24.
The flip-flop 25. 26, and a "1" signal is read into the flip-flop 25 at its rising edge.

As a result, the gate of the AND circuit 34 closes and its output becomes "0".
” becomes.

Therefore, by the time the next cross pulse φ is applied, the output of the AND circuit 34 has already become "0", and the logic condition of the AND circuit 37 is not satisfied, and the flipflop 23
is kept set.

The counter 24 receives one from the flip-flop 35.
Read the first signal and put “1” in the flip-flop 25.
When "0" is stored in the flip-flop 26, the AND circuit 28 is designated.

Therefore, the 2-second signal output from the 2-second signal generating circuit 39 as described above is sent to the 10-minute digit counter 6 via the AND circuit 28, and the contents of this counter 6 are counted up by "1". .

When the AND circuit 28 is specified by the counter 24, that is, when "1" is stored in the flip-flop 25 and "0" is stored in the flip-flop 26, the control signal I1 is output from the inverter 31 and the NAND circuit 32. , I2 becomes "0", the gate of the AND circuit 9.1''O is closed, and input from the previous stage counter to the 10-minute digit counter 6 and the hour counter 7 is prohibited.

At this time, since the output of the NAND circuit 33 is held at the "1" signal state and the gate of the AND circuit 8 is open, the counting operation of the one-minute digit counter 5 is always performed.

When the count-up operation of the 10-minute counter 6 matches the correct time, the switch Sa is instantaneously closed.

When the switch Sa is operated, a "1" signal is read into the flip-flop 35 in synchronization with the clock pulse φ as described above, and the "1" signal output from the Q side output terminal is sent to the counter 24 as a clock signal. sent as.

As a result, the contents of the counter 24 count up, "1" signals are read into the flip-flops 25 and 26, and the outputs of each Q1 become "1" and the AND circuit 29 is designated.

Therefore, the 2-second signal output from the 2-second signal generating circuit 39 is sent to the 1-minute digit counter 5 via the AND circuit 29, and the contents of the counter 5 are incremented by "1".

Further, when a "1" signal is stored in the flip-flops 25 and 26, the control signals I1 to I3 outputted from the inverter 31 and the NAND circuits 32 and 33 become "0", and the gates of the AND circuits 8 to 10 are closed. , 1 minute digit counter 5, 10
Input from the preceding stage counter to the minute digit counter 6 and hour counter 7 is prohibited.

Therefore, by counting up the 1-minute digit counter 5,
When the content becomes one minute ahead of the correct time, the switch Sa is instantaneously closed.

When the switch Sa is operated, a "1" signal is read into the flip-flop 35 in synchronization with the clock pulse φ, and its Q
A "1" signal output from the side output terminal is sent to the counter 24 as a clock signal.

As a result, the contents of the counter 24 are counted up, and the flip-flop 25 is set to "0" and the flip-flop 26 is set to "1".
"The signal is read and the AND circuit 30 is specified.

Therefore, the second clear signal is output from the AND circuit 30, and the frequency divider circuit 3 and the second counter 4 are cleared.

In this state, wait until the time displayed on the display unit 12 matches the correct time, and operate the switch Sa when the time unit reaches 0 seconds.

By operating the switch Sa, a "1" signal is read into the flip-flop 35 in synchronization with the clock pulse φ, and the "1" signal output from its Q-side output terminal is sent to the counter 24 as a clock signal.

As a result, the contents of the counter 24 return to the initial state, the contents stored in the flip-flops 25 and 26 both become "0", and the AND circuit 34 outputs a "1" signal, which is applied to the AND circuit 37.

Also, at this point, the "1" signal output from the Q-side output terminal of the flip-flop 35 and the "1" signal output from the Q-side output terminal of the flip-flop 36 are sent to the AND circuit 37.
is given to.

Therefore, when the next clock pulse φ is applied, the logical condition of the AND circuit 37 is satisfied, and the AND circuit 37 outputs "1".
A signal is output and flip-flop 23 is reset.

By resetting the flip-flop 23, the gates of the AND circuits 27 to 30 are closed, and the output of the correction signal is prohibited, and the inverter 31 and the NAND circuit 3 are
The control signals I1 to ■3 output from 2 and 33 are all “1”.
” becomes.

Therefore, gates 1 of AND circuits 8 to 10 are opened, and the frequency dividing circuit 3 and each of the counters 4 to 7 in the timer section 1 all start normal operation.

This completes the time adjustment operation.

Further, if the correction is canceled during the above-mentioned repair operation, the switch Sb is operated.

For example, if it is only necessary to correct the time counter 7 in units of "hour" and not the following minutes and seconds, switch sb is operated when the correction of the time counter 7 is completed.

When the switch sb is operated, the flip-flop 21 is set in synchronization with the clock pulse φ, and the set output inverts the flip-flop 23, so that the signal output from the Q side output terminal becomes "0".

As a result, the gates of the AND circuits 27 to 30 are closed, and the output of the correction signal is prohibited, and the inverter 31 and the NAND circuits 32 . Control signals (1) to (3) outputted from 33 are all "1".

Therefore, the timekeeping section 1 restarts the timekeeping operation from the time when the switch sb is operated.

Also, the “1” output from the flip-flop 21 is
``The signal is sent to the reset terminal H of the counter 24 and resets the counter 24, so that everything returns to its initial state.

Furthermore, even when the contents of counters other than the time counter 7 are being modified, the modification operation can be immediately ended by operating the switch sb.

Although the embodiment of the present invention has been described as a device for correcting the hour, minute, and second digits, the present invention is not limited thereto, and can be applied to a device for correcting the month, day, and day of the week digits.

For example, the time is usually displayed in hours, minutes, and seconds, and the display is switched to the month, day, and H calendar using a switching means, and the contents are corrected.

A separate switch may be provided as the switching means, but
Here, the time adjustment switch Sa is used.

Therefore, the display contents are switched from time display to calendar display only when only switch Sa is operated.

If you want to correct the month, day, and day of the week digits in the calendar, use
By operating the switch sb while the switch Sa is being operated, correction of the month digit is started.

If you operate the switch Sa again in sequence, the correction will be made in the order of the day and day of the week digits, but for example, if you want to finish correcting the contents of the calendar by correcting only the month digit, you would operate the switch sb. Then, the operation of correcting the contents of the calendar is completed by correcting only the month, and normal operation starts.

It should be noted that if the user wishes to change the display content back from the calendar display to the time display, the display content can be changed by operating the switch Sa at any time.

Furthermore, while the time is being corrected, it goes without saying that the output from the time counter to each counter of the calendar is controlled.

In short, it goes without saying that various changes can be made without departing from the gist of the present invention.

As described above, the electronic timepiece device of the present invention is set by the first operation of the first switch means for switching between the normal timekeeping state and the time adjustment state, and allows correction by the correction means; a correction control memory circuit that is set by the second operation to prohibit correction by the correction means and return to the normal timekeeping state; so that the count storage section is designated by the count storage section designation means;
initial designated state setting means for setting the count storage section designating means to a predetermined designated state in response to the operation of the first switch means; When switching to the correction state, the predetermined count storage section is automatically designated, and the count storage sections other than the predetermined count storage section are sequentially designated by operating the second switch means. Therefore, corrections to the count storage section that are frequently corrected can be made by simply switching to the time correction state using the first switch means and the correction means, and the correction can be made to any of the count storage sections. When the time adjustment is completed, the time adjustment can be stopped and the normal timekeeping state can be restored by operating the first switch means again.

Therefore, according to the present invention, it is possible to provide an electronic timepiece device with a small number of switches and a simplified correction operation.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing details of a control circuit in the same embodiment, and Fig. 3 explains the operation of the 2-second signal generation circuit in Fig. 1. This is a timing chart for DESCRIPTION OF SYMBOLS 1...Timekeeping part, 11...Decoder driver, 12...Display part, 13...Control circuit, 23...T type flip-flop circuit,
24...Johnson counter, 25.26,
35.36.40...Flip-flop circuit,
Sa...Time adjustment switch, Sb...
Shuichi control switch.

Claims (1)

[Claims] 1. A plurality of counting storage units that count and store time information including at least hours and minutes by time interval, and a first switch means for switching between a normal timekeeping state for counting clock signals and a time correction state. a second switch means for selecting a desired number storage section from the plurality of count storage sections; and a second switch means for predetermining the plurality of count storage sections by operating the second switch means. In the electronic timepiece device, the electronic timepiece device is provided with a count storage section designating means for selectively specifying the contents of the count storage section in the specified order, and a modification means for modifying the contents of the count storage section designated by the designation means. a correction control memory circuit that is set by a first operation of the clock to enable correction by the correction means, and reset by a second operation to prohibit correction by the correction means and return to a normal timekeeping state; and this memory circuit. is set, the designation means is set to a predetermined designation in response to the operation of the first switch means, so that a predetermined count storage unit among the plurality of count storage units is designated by the designation unit. initial designated state setting means for setting the state, and when the first switch means is operated to switch from the normal timekeeping state to the time adjustment state, the predetermined count storage section is automatically designated; A count storage unit other than the predetermined count storage unit is the second count storage unit.
An electronic timepiece device characterized in that the designation is made sequentially by operating a switch means.