JPS58175322A - Reset signal generating circuit - Google Patents

Abstract

PURPOSE:To prevent a defect of resetting due to noises, etc., by providing a means which works by a reset signal when said reset signal is delivered and continues the reset signal. CONSTITUTION:The power supply voltage VCC of an electronic device 2 of a microcomputer, etc. rises up completely when a fixed time elapses after application of a power supply. At the same time, the terminal voltage of a capacitor 3 which is charged via a resistance R5 rises up gradually and then exceeds the sum of the Zener voltage of a Zener diode 18 and the base-emitter voltage of a transistor TR15. Then the TR15 conducts to apply a reset signal to the device 2, and this signal makes a TR16 conduct. The conduction of the TR15 is held via the TR16. As a result, no effect is given to the reset signal even though the charging voltage of the capacitor 3 has variations.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset signal generation circuit IIK, and in particular to a switch means that receives feedback of an operating signal by outputting a reset signal even if there is a level fluctuation due to ripples or noise at power-on. To prevent the occurrence of defective reset tubes, a reset signal generation circuit for a microcomputer (hereinafter referred to as a "microcomputer") is provided.

For example, there is a circuit as shown in FIG. 1 as a reset signal generation circuit for one icon. Figure 1 shows a power-on reset circuit that outputs a signal of "KrHJ→1" (or rlJ→"0") after a predetermined time after the power is turned on. microcomputer 2 (for example, jIPD
71101), power-on reset section 1
is composed of a resistor R1 and a capacitor +3, and has an integrator circuit and an inverter 10 connected to the terminal of the capacitor 3.

In the above configuration, the operation will be explained with reference to the time chart shown in FIG. capacitor 3)
The terminal voltage of the capacitor 3 in the integrating circuit 1 rises along with the power supply voltage curve vcc, as shown by a line 3, depending on the setting of the time constant. The output voltage of the inverter 10 changes from rHJ to rLJ when the input voltage crosses the threshold and the hold voltage vtkt-9. The microcomputer 2 performs a predetermined time (for example, counting If,
pulse time) is reset when rLJt is input.

In such a conventional reset pulse signal generation circuit, the time it takes for the capacitor terminal voltage 3 to cross the threshold voltage v0 from power-on is comparable to the rise time of the power supply voltage vce. If there is smoke, the inverter 10 may not be able to generate a reset signal to the microcomputer, etc.
By using a C-Meal type IC as a thread.

Increasing the hold voltage Vth: yinde 7
This is dealt with by increasing the time constant determined by t3 and resistor R1.

19. Even if the output voltage of inverter 0 changes from "K" to rLJ, if the power supply voltage vec has not sufficiently risen to a voltage that guarantees the correct operation of the circuit elements of the i icon group, the reset signal rLJ will be activated. Even if you input The problem can be solved by using a combination of comparator 11 and Zener diode 12. The reset pulse generating circuit shown in FIG. 3 includes an integrating circuit connected to the power supply V, , and consisting of a resistor Rs and a capacitor 3, and a comparator ! ! Connected to the inverting input terminal of the
Zener diode 12 and resistor 1) with characteristics R
It consists of a reference voltage generation source consisting of s and an inverter 10 connected to the output terminal of a comparator 11. The operation of the circuit will be explained using the time chart shown in Figure 4. A reference voltage 13 is applied to the 110 inverting input terminal, and a capacitor voltage 3 is compared to the non-inverting input terminal.
is applied, and as a result, when the capacitor voltage 3 becomes greater than the reference voltage 13, an output voltage 11 is output, and further, the output voltage 11 is inverted and output 10 via an inverter 710, and - ) Microcontroller 2 as a pulse
It is set to K so that it will be input.

However, in these reset signal generation circuits, #
! Figure 2 and Figure 4 Q Kyuso 3m + 10m and 11m
As shown in the figure, when the voltage at the terminal t30 becomes unstable and rises or falls at the hold level vtht due to ripples or noise in the power supply, the inverter voltage changes accordingly.
The output voltage 10a of O is rHJ and [LJ O output t<bReturn 9th, there is a risk that the microcomputer 2 will have a reset failure.

As one solution to this problem, a method has been proposed in which the threshold voltage is separated into upper and lower levels using an inverter circuit equipped with a trigger circuit. The upper and lower hysteresis is OSV
The degree of variation in '&p1 capacitor terminal voltage 3a is 0.8
This method is ineffective if a power supply voltage greater than or equal to v is not used.

The present invention #! above! When the power is turned on, a reset signal is output to prevent reset failure even if there is a level fluctuation due to pull, noise, etc. The present invention provides a reset signal generating circuit which generates a reset signal ta11 by applying a signal of a predetermined level to a means for generating a cough set signal ta.

The reset generation circuit according to the present invention will be explained in detail below.

FIG. 5 shows an embodiment of the present invention. The same parts as in FIGS. 1 and 3 are indicated by the same reference numerals, so redundant explanation will be omitted). One end of the Zener diode 18 is connected to the output terminal of the nine integrating circuit, and the other end is an NPN transistor ISO.
connected to the base. The collector of the transistor 15 is connected to the reset terminal 20 of the microcomputer 2. The collector of transistor 1B is connected to PNP via resistor 115Ryt.
The collector of the transistor 16 is connected to the base of the transistor 16, and the collector of the transistor 150 is connected to the resistor l!
Connected through the wings. 17i switching diode.

In the above configuration, the operation will be explained using the main power supply shown in FIG. Also, the voltage V of the power supply diode 18 rises with a delay of the power supply voltage vc, and the voltage V between the base voltage of the transistor 15 and the sum of 0 V
, +V,, increases at t. zener diode 18
The current flowing through t- is determined by the terminal voltage 3 of capacitor t3 being V, +
When the voltage is below the level of V, , it flows through the resistance R, (choose a constant value of 1 for KR so that the voltage at the connection point 9 does not exceed vlm), the capacitor terminal voltage S + V, + V,
When the level of 1 is exceeded, current begins to flow to the base of the transistor 15, and the voltage at the base becomes higher than the voltage at the collector.
A ground potential is applied to the transistor 15t through the transistor 15t.

In parallel with this, the PNP type transistor 16 inputs this ground potential as a base voltage and turns on. When the transistor 16 is turned on, the base current of the transistor 15 is supplied, and the base voltage of the transistor 15 becomes higher than the voltage between the collector and emitter, and the collector-emitter continues to conduct, and the reset terminal 2o of the microcomputer 2 receives the rLJ level. Reset signal 201 for a predetermined period of time (for example, the number m
At the time of y pulse @) To supply.

In this way, by feeding the change in the output into positive feedback to the input)
, transistors 15 and 16 are instantly turned on, and the input signal of the reset terminal 2o of the microcomputer changes from H to L level K.
tkru. Therefore, after the transistors 15 and 16 are in the -HON state, the terminal voltage 3a of the capacitor changes to the time 1.0 as shown in FIG. Even if the output 20 fluctuates thereafter, the output 20 will not change back and forth between the H and L levels, and therefore will not output a pulse that does not require resetting.

As explained above, according to the cut signal generation circuit according to the present invention, when the reset signal is output, the hand RK is activated by the cough reset signal and generates the hit signal.
Since the reset signal is continued to be generated by applying the predetermined level 014tt, it is possible to prevent the V cell F from failing even if there is a level fluctuation due to ripples, noise, etc. when the power is turned on.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional reset generation circuit, FIG. 2 is a time chart of FIG. 1, and FIG. 3 is a diagram showing an improved conventional reset generation circuit. #I
Figure 4 is the time chart of Figure 3. FIG. 5 is a block diagram showing one embodiment of the present invention, and FIG. 6 is a time chart of FIG. 5. Explanation of symbols l...Power-on reset, )11.2...Microcombi, -ta, 3...Capacitor, 10--Inverter, 11--Comparator, 15...
・NPN type first transistor, 16... PNP type second transistor, 17... Diode, 1
8... Zener diode e) nl l R wealth l1l
s lR41RI #Ra l wing 1 tRs IR@・
··Resistor. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] Means for outputting a time signal that increases as the power supply voltage increases or decreases depending on the running time that has elapsed since the power was turned on; and first switch means having an actuation level that is actuated after rising and outputs a reset signal when the time signal reaches the actuation level; and when the first switch means is actuated, at least the actuation level is A reset signal generating circuit comprising a second switch hand lRt for supplying a control signal having a level to the first switch means.