JPS58175039A - Connecting state management system - Google Patents

Connecting state management system

Info

Publication number
JPS58175039A
JPS58175039A JP5757182A JP5757182A JPS58175039A JP S58175039 A JPS58175039 A JP S58175039A JP 5757182 A JP5757182 A JP 5757182A JP 5757182 A JP5757182 A JP 5757182A JP S58175039 A JPS58175039 A JP S58175039A
Authority
JP
Japan
Prior art keywords
address
channel
input
register
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5757182A
Other languages
Japanese (ja)
Inventor
Haruo Sugizaki
杉崎 治男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5757182A priority Critical patent/JPS58175039A/en
Publication of JPS58175039A publication Critical patent/JPS58175039A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To recognize the connecting state of a provided input/output device at a channel device, by reporting and managing the connecting state. CONSTITUTION:When the inputs of a comparator 101 are coincident, a forming circuit 103 forms a status bit ''1''. Then, the content of an area of a memory corresponding to an address stored in an address register 108 in advance is read out in a register 110. When it is a status bit ''0'', ''1'' is written in an area of a memory 109 corresponding to the said address as the registration processing, the reception number is returned to the I/O to complete a series of setting procedure. When a readout register reads out the status bit ''1'', it is discriminated as the duplicated use of the device number or the address. The content of the area corresponding to the address is not revised, a refusal signal is transmitted to the I/O and the failed state of the said address is displayed and outputted to a suitable display means such as a display panel 114.

Description

【発明の詳細な説明】[Detailed description of the invention]

(イ)分針 本発明は計鼻機等のチャネル装置と、該チャネル装置の
各チャネルに配設されている各入出力装置間のインター
フェース制御に係り特に紋装置の鉄杭・非設続状況のV
進方法に関する。 (ロ) 従来技術 従来こうし九チャネルに配設されている各入出力装置に
ついてチャネル側から見てどの呼出アドレス(通常、装
置機番を用いている。)の入出力装置が接続状態、すな
わち動作可能の状態になっているかを知るためKは各入
出力装置の表示パネル等を個々Kliぺなければならな
がりた。また配設されている装置の機番(呼出アドレス
)が誤まって重複して設定されている場合はシステムの
正常な運用を阻書するが、重複して設定されているか否
かの調査のためにも各入出力装置のアドレス設定回路t
iはスイッチを個々に調べねばならず、システム設置1
lIToるいは変更時、あるいは故障し走入出力装置が
ある場合チャネル側では簡単に知る手段がなかつ九〇 (ハ) 目的 不発明社こうした背′tKかんがみ成されたものであり
目的とするところは配設された入出力装置の&続状況を
報告させ、管理することKよりチャネル装置側で知シ得
る橡にすることでToシ、本発明の特*Fi上記i的を
実装するため入出力装置を接続するチャネル装置と入出
力装置間のインターフェース制御において、入出力装置
が接続状態となった直後と非接続状態となる直前を判断
しチャネル装置に報告する判断および信号手順を有し、
チャネル装置は該信号を割込情報として該装置のメモリ
で管理しているチャネルに配設されている入出力装置の
管理テーブルを頁新して配設されている各入出力装置の
機番と接続状況を管理することである。 に)実施例 以下不発間管よシ具体的に説明するため実施例を引いて
説明する0 第1図は発明対象の概念図で、図中1は計算機、2はそ
のチャネル装置、11,12.13.  ・・・・1m
+ ・・・・・・!1.1.  n2.・・・・・nm
、はチャネル装置の1からnのチャネルに配設された入
出力装置(以下110と通称す)である0 藤2図は本発明の一実施例の説明図で、チャネル!!皺
とIloとの間の信号の送受を脱狗するものである。 絽3図は本発明の一実施例の説明図で、チャネル装rj
IIt個で110の接続状態を管理するための必賛機能
部の説明図である〇 なお図は省略したが夫々のI10側r(は特定コードの
送出手順を有しておF)Iloの電源をONにしてモー
ドスイッチを接続にした時、状絢信号が上るとともにチ
ャネルに割り込み登録のための特定コードと自己の機番
を報告させ、またモードスイッチを非接続にするとき状
態信号が下がるまでの間にチャネルに割や込んで自己機
番と登録解除のための特定コードt−報告するものとす
る0図中の101. 1o2ijt10から受信したデ
ータ中の特定コード検出用の比較器、103と104は
夫々接続状mを登録管理する丸めの状態ビットの〔1〕
(a) Minute hand The present invention relates to interface control between a channel device such as a nose meter and each input/output device installed in each channel of the channel device, and particularly relates to control of the interface between a channel device such as a nose meter and each input/output device installed in each channel of the channel device. V
Regarding the advance method. (b) Prior art For each input/output device arranged in nine channels, it is determined from the channel side which calling address (usually a device number) the input/output device is connected to, that is. In order to find out whether the devices were ready for operation, K had to individually check the display panels of each input/output device. In addition, if the machine number (calling address) of the installed equipment is incorrectly set and duplicated, it will prevent the normal operation of the system. Therefore, the address setting circuit of each input/output device is
i have to examine the switches individually and system installation 1
There is no easy way to know on the channel side when changing or changing the running input/output device, or when there is a malfunction. The special feature of the present invention is to report and manage the status of the installed input/output devices on the channel device side. In interface control between a channel device that connects a device and an input/output device, it has a judgment and signal procedure for determining and reporting to the channel device immediately after the input/output device is in a connected state and immediately before it is in a disconnected state,
The channel device uses the signal as interrupt information to refresh the management table of the input/output devices installed in the channel managed in the memory of the device, and calculates the machine number of each installed input/output device. It is to manage the connection status. 2) Examples Below, in order to specifically explain the unexploded tube, examples will be used to explain it. Figure 1 is a conceptual diagram of the object of the invention, in which 1 is a computer, 2 is its channel device, 11, 12 .13. ...1m
+・・・・・・! 1.1. n2.・・・・・・nm
, is an input/output device (hereinafter referred to as 110) arranged in channels 1 to n of the channel device.0 Fuji Figure 2 is an explanatory diagram of an embodiment of the present invention, and the channel! ! This eliminates the transmission and reception of signals between the wrinkles and Ilo. Fig. 3 is an explanatory diagram of one embodiment of the present invention, in which the channel equipment rj
This is an explanatory diagram of the required function unit for managing the connection status of 110 units in IIt.Although the diagram is omitted, each I10 side r (F has a specific code sending procedure) and the power supply of Ilo. When the mode switch is turned on and the mode switch is connected, the status signal goes up and the channel reports the specific code for interrupt registration and its own machine number, and when the mode switch is disconnected, the status signal goes down. 101 in Figure 0, interrupt the channel and report the own machine number and a specific code for deregistration. Comparators 103 and 104 are for detecting a specific code in the data received from 1o2ijt10, respectively, and the rounding status bit [1] registers and manages the connection state m.
and

〔0〕の作成回路、105. 106. 107は夫
々オアゲート、108はメモリ走査用のアドレスレジス
タで、咳アドレスは110の機番と対応付けられている
。109はIloの1ik絖状WIを登録管理するメモ
リ、110Fi耽出しレジスタ、113はインバータ、
111と112tl夫々比較回路で接続状態にあるIA
が四−機番(アドレス)で2重登録されるのを監視する
ものである。また114はチャネル装置又は計算機の表
示パネルで、この外に当然チャネル装置の170制御と
父信のための通常構成の機能は保有しているものとする
。こうした構成において配設されている110のどれか
が電源ONされオンラインのスイッチを入れて接続状態
に入るとすると接続するシーケンスとして#当110は
割込要求信号をチャネル装置に送シ、チャネルをつかま
える。割込が出来て選択モードとなり父信軒可信号が戻
ると、該110からアドレス通知信号とともにアドレス
情報(機#Iti等呼称アドレス)を転送ブロックとし
て送り出すと、チャネル装置側はこれをアドレスレジス
タ108に格納し受付信号を戻すと、110側はステー
タス通知信号ととも(ステータス情報としての特定情報
;ここでは接続状u (Enableと略称する)K変
化することを報告する情報、を転送ブロックとして送シ
出し、チャネル餉が該ブロックを受付けると、特定情報
をここでは比較−101で検出して登録処理に入る。ナ
なわち比較器101が一致すると作成回路103で状態
ビットの(1)1作成し、先にアドレスレジスタ108
に:格納されていたアドレスに#当するメモリの領域の
内容を読出しレジスタ110でよみ出しそれが状態ピッ
)0(0)であれば比較回路112の出力が(1)とな
るOでこの場合は登録処理として該当のアドレスに対応
するメモリ109の領域に〔1〕を書き込み110には
受付信号を返送して一連のセツティング手順を終了する
し、読出しレジスタが状態ビットの〔1〕を読出してい
る時は比較回路11111i1が一致して出力〔1〕と
なるのでこの場合は機番あるいはアドレスの二1使用と
判定し、該当アドレスに対応する領域の内容は更新せず
170には拒絶信号金送るとともに当該アドレスが異常
であることti示パネル114等の適当な表示手段に表
示出力する。なお接続状態を解消する場合Fi110@
でオンラインのスイッチをオフラインにするとき、一連
の接続解除のシーケンスとして割込要求信号を上げ先の
接続時とはぼ同様の手順で交価しながら特定情報として
今度は比較器102が一致する情報を送受し作成回路1
04で状態ピッ)(0)t−作成し該尚アドレス対応の
メモリ109の領域を
[0] creation circuit, 105. 106. 107 is an OR gate, 108 is an address register for memory scanning, and the cough address is associated with the machine number 110. 109 is a memory for registering and managing Ilo's 1ik wire WI, 110 is a Fi indulgence register, 113 is an inverter,
111 and 112tl are connected in each comparison circuit.
This monitors whether the machine number (address) is registered twice. Further, 114 is a display panel of a channel device or a computer, and in addition to this, the display panel 170 of the channel device naturally has the functions of a normal configuration for controlling the channel device and sending messages to the father. When one of the 110s arranged in such a configuration is powered on and turned on and enters a connected state, the connection sequence involves #110 sending an interrupt request signal to the channel device and seizing the channel. . When an interrupt is generated and the selection mode is entered and the father's credit card enable signal is returned, the 110 sends out the address information (name address such as machine #Iti) along with the address notification signal as a transfer block, and the channel device side transfers this to the address register 108. When the reception signal is returned, the 110 side sends a status notification signal (specific information as status information; here, information reporting that the connection status U (abbreviated as Enable) K has changed) as a transfer block. When the channel block receives the block, the specific information is detected by comparison -101 and the registration process begins.In other words, when the comparator 101 matches, the creation circuit 103 creates the state bit (1)1. Then, first address register 108
To: Read out the contents of the memory area corresponding to the stored address in the register 110. If the state is 0 (0), the output of the comparison circuit 112 will be (1). In this case, O. writes [1] in the area of memory 109 corresponding to the corresponding address as a registration process and returns an acceptance signal to 110 to complete a series of setting procedures, and the read register reads out the status bit [1]. When the comparison circuit 11111i1 matches and outputs [1], in this case, it is determined that the machine number or address 21 is used, and the contents of the area corresponding to the address are not updated and a rejection signal is sent to 170. At the same time as sending the money, a display is output to an appropriate display means such as the panel 114 indicating that the address is abnormal. In addition, if you want to cancel the connection status, please use Fi110@
When an online switch is brought offline, an interrupt request signal is raised as a series of disconnection sequences, and the information that comparator 102 matches as specific information is exchanged in roughly the same procedure as when the destination was connected. Sending/receiving creation circuit 1
(0) t-Create the area of memory 109 corresponding to the address.

〔0〕に書き換える。なお接続状
nKあるか否かをさがすため読出しアドレスAと読出し
タイきングTiあたえてメモリ109の皺当アドレスに
対応する内容をよみ出すことが出来る。以上t−l10
側あるいは計算機匈からの蚤求によって行うことによっ
てチャネル側では配設されているIloの接続状態のが
管理出来、異常接続の発見が容易となる。なおアドレス
ニJk使用の場合表示をあとから割込んだ110の表示
パネル岬に行うことも出来この場合は110群の中から
当該110をさがすことが容易になる。 (ホ)効果 以上説明した様に本発明によれはチャネル装置側で配設
されている110の接続状況を把握すゐことが出来るの
で異常の発見が′#易となり、さらにはシステム運用時
必賛な110が接続しているか否かの判定も可能となる
と云う%徴ある効果tMするものである。 第1図は発明対象の概念図。 第2図は本発明の一実施例の説明図。 第3図は本発明の一実施例の説明図。 図中、l祉計算機、2はチャネル装置、11゜12、・
・・・・・1m、・・・・・・nl、n2.・・・ n
m、は入出力装置(Ilo )t  101と102は
比較器、103と104は作成回路、105と106と
107はオアゲー)、  108Fiアドレスレジスタ
、109はメモリ、110は読出しレジスタ、  11
3Fiインバータ、111と112は比較回路〇 々/  12       71’7’2第 l 図 第2図 第3閃
Rewrite to [0]. In order to find out whether or not there is a connection state nK, it is possible to read out the contents of the memory 109 corresponding to the wrinkled address by giving the read address A and the read timing Ti. More than t-l10
By requesting requests from the side or the computer, the channel side can manage the connection status of the installed Ilo, making it easier to discover abnormal connections. In addition, when using Address Ni Jk, the display can be displayed later on the display panel cape of 110, which makes it easy to search for the 110 in the 110 group. (E) Effects As explained above, according to the present invention, it is possible to grasp the connection status of the 110 installed on the channel device side, which makes it easier to discover abnormalities, and furthermore, when necessary during system operation. This has a significant effect in that it becomes possible to determine whether or not 110 is connected. FIG. 1 is a conceptual diagram of the subject of the invention. FIG. 2 is an explanatory diagram of one embodiment of the present invention. FIG. 3 is an explanatory diagram of one embodiment of the present invention. In the figure, 1 is a computer, 2 is a channel device, 11°12, ・
...1m, ...nl, n2.・・・n
101 and 102 are comparators, 103 and 104 are creation circuits, 105, 106 and 107 are or game), 108 Fi address register, 109 is memory, 110 is read register, 11
3Fi inverter, 111 and 112 are comparison circuits / 12 71'7'2 No. l Figure 2 Figure 3 Flash

Claims (1)

【特許請求の範囲】[Claims] 入出力装置を接続するチャネル装置と入出力装置間のイ
ンターフェース制御において、入出力装置が接続状−と
なった直後と非接続状態となる直前を判断しチャネル装
置に報告する判断および佃号+順を清し、チャネル装置
は該信号を割込情報として該装置のメモリで管理してい
るチャネルに配設されている入出力装置の管理テーブル
を更新して、配設されている各入出力装置の機番と接続
状況を管理することを特徴とする接続状態管理方式0
In interface control between a channel device that connects an input/output device and the input/output device, judgment and order in which the input/output device determines when it becomes connected and immediately before it becomes disconnected and reports it to the channel device. The channel device uses the signal as interrupt information to update the management table of the input/output devices installed in the channel managed in the memory of the device, and updates the management table of the input/output devices installed in the channel. Connection status management method 0 characterized by managing the machine number and connection status of
JP5757182A 1982-04-07 1982-04-07 Connecting state management system Pending JPS58175039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5757182A JPS58175039A (en) 1982-04-07 1982-04-07 Connecting state management system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5757182A JPS58175039A (en) 1982-04-07 1982-04-07 Connecting state management system

Publications (1)

Publication Number Publication Date
JPS58175039A true JPS58175039A (en) 1983-10-14

Family

ID=13059525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5757182A Pending JPS58175039A (en) 1982-04-07 1982-04-07 Connecting state management system

Country Status (1)

Country Link
JP (1) JPS58175039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158661A (en) * 1986-12-23 1988-07-01 Nec Corp Recognition system for adjacent processor for inter-processor communication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158661A (en) * 1986-12-23 1988-07-01 Nec Corp Recognition system for adjacent processor for inter-processor communication

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