JPS58172577A - Electronic time piece - Google Patents

Abstract

PURPOSE:To realize an electronic time piece capable of maximizing a high stability of a high frequency oscillation circuit with a low power consumption by supplying a high frequency oscillation signal to a high frequency switching circuit in an electronic time piece designed to obtain a reference time signal corrected by a high frequency signal. CONSTITUTION:A correction circuit 6 obtains the sum of frequency between a front stage division signal f71 and an interrupt pulse signal f3 and outputs a correction signal f5. In a comparator circuit 3, a high frequency switching circuit 31 and a switching control circuit 32 of a phase comparator circuit 4 (41) samples a high frequency signal fH as a correction signal fed from an input terminal P1 at the rising of the front stage division signal f71 as a sampling signal fed from an input terminal P2 and a phase difference signal preparation circuit 33 outputs a phase difference signal f4. The frequency is expressed by the formula 4. When a frequency deviation is determined with respect to 1Hz of the reference time signal, using f3=f4/2<9>, f71=fL/2<2> and fS=f6/2<13>, the formula 5 is given. This demonstrates that correction can be done by the high frequency oscillation signal fH.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a high-precision electronic timepiece that is equipped with a highly stable high-frequency oscillation circuit and that obtains a time reference signal that is calibrated using the highly stable oscillation signal.

Currently, electronic watches are widely used as crystal watches due to the adoption of crystal oscillators. Among these, 32KFlz for watches.
A device that uses a tuning fork type crystal oscillator and has a monthly lead/lag of several tens of seconds is in widespread use. In recent years, electronic clocks have been commercialized or developed that improve upon this crystal clock and can keep time within a few seconds or even tens of seconds a year. The following two methods are the main methods for improving these high-precision electronic watches.

(1) Using the tuning fork type crystal resonator of the 32 KHz range, the frequency-temperature characteristic, which is approximately a quadratic curve, is corrected by the output of a separately prepared temperature sensor.

c2) Use a 4MRz AT board crystal oscillator that is highly stable due to thickness shear vibration and has good frequency-temperature characteristics that form an approximately cubic curve.

Of these, the latter is suitable for high-precision watches because it has good aging performance, but it consumes a lot of power for high-frequency oscillation and frequency division, and it is difficult to mass-produce crystal units with good temperature characteristics. That's funny. In this respect, since the former has a low frequency, power consumption is small, and mass production is possible because it is only necessary to correct (hereinafter referred to as temperature compensation) the frequency-temperature characteristic, which is a quadratic curve that is stable in mass production.

From the above point of view, the electronic timepiece using the former method has a great advantage in wristwatches with limited battery capacity. However, in this method, since the amount of temperature compensation itself is large, it is difficult to improve the accuracy of temperature compensation, and deterioration of temperature compensation accuracy due to aging of the temperature sensor 7 is unavoidable. Therefore, the output signal of the high frequency oscillation circuit such as the 4M[Tz range is used as a calibration signal, and the calibration signal is sampled based on the output signal of the low frequency oscillation circuit such as the 32KHz range.
The applicant of the present invention has proposed a method of correcting a time reference signal obtained by frequency-dividing the low-frequency oscillation signal based on the sampling result.

This method is hereinafter referred to as a high frequency calibration method.

This high-frequency calibration/correction method makes use of good aging characteristics, which is an essential condition for high-precision timepieces, and also allows only the high-frequency oscillation circuit to operate at high frequencies, thereby minimizing the increase in current consumption. Note that this high-frequency calibration method produces the following effects.

(1) The high frequency oscillation circuit can be caused to perform intermittent oscillation, further reducing power consumption.

(2) When temperature compensation is performed, good temperature compensation accuracy is achieved due to the correction of the gentle frequency temperature characteristics of the high frequency crystal resonator.

In addition to this, it has various effects because it enables digital correction.

As explained above, the high-frequency calibration method has many advantages, but the sampling of the high-frequency calibration signal has an adverse effect on the high-frequency oscillator circuit9. It was very difficult to set the conditions. For this reason, the high frequency calibration method has been mainly applied to a high frequency oscillation circuit in which intermittent oscillation is performed at considerably long time intervals, and its range of application has been limited.

The present invention provides a comparator circuit that samples the output signal of the high-frequency oscillation circuit based on the output signal of the low-frequency oscillation circuit and compares the output signals of both oscillation circuits in an electronic watch using this high-frequency calibration method. The objective is to achieve a comparison circuit that has almost no adverse effect on the oscillation circuit, consumes low power, and provides reliable comparison results.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment of an electronic timepiece using the phase comparator circuit according to the present invention, and FIGS. 2(A) and (B)
is the circuit block diagram of the embodiment of the phase comparator circuit in Figure 1.
3 and 4 are voltage waveform diagrams of FIG. 2 (A) and CB).

The configuration shown in FIG. 1 will be explained.

1 is a low frequency oscillation circuit, and its oscillation frequency fL is 32
It is set slightly lower than 768Hz.

2 is a high frequency oscillation circuit, the oscillation frequency fB of which is adjusted by 4194304H2K by a trimmer capacitor. 7 is a frequency dividing circuit which inputs the low frequency oscillation signal fL from the low frequency oscillation circuit 1 and outputs the pre-stage frequency divided signal '? A two-stage pre-stage frequency dividing circuit 71 that outputs +, and this pre-stage frequency dividing signal f7+
and a correction circuit 6 consisting of an exclusive OR circuit which takes the interrupt pulse train word f3 as an input signal from a comparison circuit 6 to be described later and outputs a correction signal fak, and inputs this correction signal f6 and generates a 1 second signal as a time reference signal f. It consists of a 13-stage rear-stage frequency dividing circuit 72 that outputs. Reference numeral 8 denotes a time display means for displaying the time based on the time reference signal f.

Reference numeral 6 denotes a comparator circuit which receives a high frequency oscillation signal f! from the high frequency oscillation circuit 2 as a reference signal for calibration from an input terminal P.
I is supplied from the input terminal P2, and a pre-stage divided signal f91 obtained by dividing the output signal f of the low frequency oscillation circuit 1 by the pre-stage frequency dividing circuit 71 is supplied as a sampling signal from the input terminal P2, and from the output terminal P, both inputs are supplied. It consists of a phase comparison circuit 4 which outputs a phase difference signal f4f having a phase difference frequency of the signal, and a phase difference counter 5 consisting of a nine stage counter which uses this phase difference signal f4 as an input signal and outputs an interrupt pulse train signal f3.

The operation of the electronic timepiece having the above configuration will be explained.

The correction circuit 6 is a known mixing circuit that calculates the frequency sum of the pre-stage frequency-divided signal f7+ and the interrupt pulse signal f, and the frequency of the correction signal f6 which is its output is calculated by the following equation.

'6-'? ＋＋'3
・・・・・・・・・(1) Here
'? +”fL/2”, using fB=f6/2+s,
The frequency deviation of the time reference signal with respect to IHz is calculated as follows: =fL/2ISf,/213-1 □-1011,100, (2). Here, if the frequency of the interrupt pulse train signal f is set to zero, the equation (2) is transformed into the following equation.

That is, the time reference signal f8 is 15 times higher than the low frequency oscillation signal fL.
The signal is frequency-divided by the frequency divider circuit in the second stage, and the low-frequency oscillator circuit 1
, the frequency dividing circuit 7, and the time display means 8 operate as a normal electronic watch.

As explained in the configuration, the low frequency oscillation frequency fL is 32768H
It is set slightly lower than z, and according to equation (3), the frequency error of the time reference signal f8 is slightly negative. The comparator circuit 6 is a circuit that generates the interrupt pulse train signal f in equation (2) to correct this frequency error.

As explained in the configuration, the phase comparison circuit 4 in the comparison circuit 3 outputs a phase difference signal f4 having a phase difference frequency between the pre-stage frequency-divided signal '71 and the high-frequency oscillation signal f8, but this frequency is 32768 Hz in the pre-stage frequency-divided signal f7+. Since it is a low frequency oscillation signal set to a lower frequency and is a signal obtained by dividing the frequency of , and the high frequency oscillation signal fH is set to exactly 4194304Hz, the following formula % formula %) This formula (4) and '3=f4 /29 When using fC)
The equation is transformed into the following equation.

This equation (5) shows that the electronic timepiece according to this embodiment is calibrated by the high frequency oscillation signal fM.

The configuration of FIG. 2(A) will be explained.

Reference numeral 41 denotes a phase comparator circuit to which a high frequency oscillation signal f8 is supplied from the input terminal P, and a pre-stage frequency divided signal ' which is obtained by dividing the low frequency oscillation signal fL as a sampling signal from the input terminal P2.
71 is supplied, and the output terminal P outputs a phase difference signal f4.

The configuration of the phase comparison circuit 41 will be explained.

Reference numeral 61 denotes a high-frequency switching circuit, which takes both the input terminal P and the higher frequency signal fM as input signals, and the other input signal is the switching control signal S, 2, and its inverted signal S3□ by the inverter 311, and the f-phase phase signal, respectively. A NAND gate 312 and a NOR gate 3, which are respectively regarded as an AND gate and an inverter, and an OR gate and an inverter, and are configured by CMO8, output an inverted signal of U, 0 phase signal V.
16 and an inverter 314 that inverts the output of the NOR gate 613 and outputs an O phase signal V.

62 is an opening/closing control circuit, which outputs an anti-phase detection signal PD as input signals of the 1 phase phase signal U and 0 phase signal vl.
The ND circuit 622 and the sampling enable signal S8. which is set at logic O of the pre-stage frequency divided signal f7+ as a sampling signal supplied from the anti-phase P2. NAN to output
A flip-flop 34 consisting of two D circuits and this sampling permission signal S5. and input terminal P, and an AND circuit 621 which receives the pre-stage frequency-divided signal f7+ from the input terminal P as an input signal and outputs the opening/closing control signal S,2.

Reference numeral 33 denotes a phase difference signal generating circuit, which outputs a phase difference signal f, which is reset at logic 0 of the phase signal V made up of two signals outputted from the high frequency switching circuit 31, to a terminal P. K
It consists of a flip-flop that outputs.

Next, the operation of the phase comparator circuit 41 having the above configuration will be explained using FIG. 3.

In FIG. 3, (a) is the high frequency signal fH, (b) is the pre-stage frequency division signal '71, (c) is the 1-phase signal U1, (d) is the 0-phase signal V, (e) is the anti-phase detection signal PD, (y is the sampling permission signal 834, (g) is the opening/closing control signal SSt
, (H) are waveform diagrams of the phase difference signal f4 with circuit delays partially exaggerated.

As mentioned above, the pre-stage frequency division signal '71 is a signal obtained by dividing the low frequency oscillation signal fL, which is set slightly lower than 32,768 Hz, by the two-stage pre-stage frequency divider circuit 71, so its frequency is slightly lower than 8,192 Hz. The high frequency signal f[I is set to exactly 4194304 Hz. From this, fR is '? + about 512 times, and the phase relationship is the high frequency oscillation signal f! shown in (a). For every 512 signals indicated by diagonal lines in I), the pre-stage frequency divided signal '? "Is"*, which indicates the rising edge of 1,...
..., moves to the right at time t6.

Now, immediately before each time point tl, t2, . Therefore, the clip-flop 34 is set and the sampling permission signal S5. is logic 1, but the AND circuit 321 outputs the pre-stage frequency divided signal '? + is logic. Therefore, the opening/closing control signal ssx' shown in (g) is set to logic 0. At this time, NAN
Both the D circuit 312 and the NOR circuit 316 are closed, and (
C) As shown in (d), both the 1-phase signal U and the Q-phase signal V are logic 1. As a result, the AND circuit 322 (
The anti-phase detection signal -PD- shown in (p) is set to logic 1.

Now, when the pre-stage frequency division signal f7+ shown in (b) rises at each time point of tI% t2..., t6, the sampling permission signal S44 shown in (f) is already logic 1, so AND
The circuit 321 inverts the opening/closing control signal S32 to logic 1 as shown in (g). As a result, N A N D circuit 3
12. The NOR circuit 313 is opened, and at time tI, tl, t, the high frequency oscillation signal f shown in (A) is within the range of logic 1, so at time t8 and t4 shown in (C), the high frequency oscillation signal fH is logic 0. Since it is within the range of , the 0 phase signal ■ is inverted to logic 0 as shown in (d).

The AND circuit 322 generates the anti-phase detection signal PD shown in (e) by inverting the two-phase phase signal U or V. In order to make the logic 0, the flip-flop 34 is reset and the sampling permission signal S shown in (e) is generated. 4 is inverted to logic O. As a result, the AND circuit 621 inverts the opening/closing control signal S3□ shown in (g) again and makes it logic 0, so N
AND circuit 612 and NOR circuit 316 are closed again (
As shown in c) and (d), both phase signals U%V are logic 1.
to be reversed.

As described above, the high frequency switching circuit 61 and the switching control circuit 32 receive the pre-stage frequency divided signal '?' as a sampling signal supplied from the input terminal P2. At the rising edge of +, a downward convex pulse signal is output as a high frequency phase signal U as a calibration signal supplied from the input terminal P1, and when the logic is 0, an O phase signal V is output.
It was shown that the circuit outputs a downwardly convex pulse signal. The phase difference signal generating circuit 33 is set by the pulse signal of the 1-phase signal U and reset by the pulse signal of the O-phase signal V, and outputs the phase difference signal f4 shown in (H).

The configuration of FIG. 2(B) will be explained.

42 is a phase comparison circuit which is an improved version of the phase difference signal generation circuit 33 in the phase comparison circuit 41 explained in FIG.

In the phase comparator circuit 42, 35 is a phase difference signal generating signal S,
and the clip front processor 61 which outputs the inverted signal thereof via the inverter 362, and the current phase signal S supplied from the data input terminal at the rising edge of the pre-stage frequency divided signal '71 supplied from the clock input terminal T. a shift register 66 consisting of a flip-flop 366 that samples at the output terminal Q and outputs the previous phase signal S and its inverted signal; and a NAND circuit 371 that receives the current phase signal S and the previous phase signal S2 as inputs. NAND with inputs of the inverted signal of this current phase signal S and the inverted signal of the previous phase signal S.
The phase difference stabilizing circuit 37 includes a circuit 672 and a flip-flop 373 which is set by the logic 0 of the output signal of the NAND circuit 371 and reset by the logic 0 of the output signal of the NAND circuit 372.

The operation of the phase comparator circuit 42 having the above configuration will be explained using FIG. 4.

In Fig. 4, (a) is the 1-phase signal U, (b) is the O-phase signal V, (c) is the current phase signal S1, (d) is the previous phase signal S2, and (e) is the phase difference signal f4. It's a shame that the circuit delay is partially exaggerated in the waveform diagram.

The high-frequency switching circuits 3 and 1 and the switching control circuit 62 generate the high-frequency signal fM at the rising edge of the pre-stage divided signal f7+, and when the logic is 0, a downwardly convex pulse signal is output as the O-phase signal V.
Normally, the pulse signals of the phase signals U and V are output continuously and alternately. However, according to experiments, when the phase difference is set to be small or due to external disturbances, the pulse signals of the phase signals U and (2), which are larger than the phase difference, are often repeated.

In this example, the low frequency oscillation frequency fL is 3276
Since the phase difference can be increased by making the frequency smaller than 8 Hz, malfunctions due to a small phase difference can be avoided.

An example is shown in which a pulse signal is outputted to the one-phase signal U due to a disturbance or the like at time t during which pulse signals are continuously and alternately outputted to the signal V. At this time, it is reset by the signal V and outputs the current phase signal S as shown in (c), and furthermore, the flip-flop 663 outputs the current phase signal S.
1 is sampled by the pre-stage frequency division signal '71, and the pre-phase signal S, which is obtained by shifting the current phase signal, is output as shown in 2).

The flip-flop 373 is set when the current phase signal S1 and the previous phase signal S shown in (c) and (d) are both logic 1, and reset when both are logic 0, so that the flip-flop 373 generates a phase difference signal as shown in (e). is output.

In other words, the influence of the disturbance at t is ignored.

As described above, according to the present invention, in an electronic watch that includes a low frequency oscillation circuit and a high frequency oscillation circuit and obtains a time reference signal calibrated with a high frequency signal, a comparison circuit that compares the output signals of both excavation circuits is provided. By adopting a configuration that includes a phase comparison circuit consisting of a high-frequency switching circuit, a switching circuit, and a phase difference signal generation circuit, power consumption can be reduced by supplying the high-frequency oscillation signal as it is to the high-frequency switching circuit. By inputting the high frequency oscillation signal to the CMOS gate in the switching circuit, a high input impedance can be obtained, making it possible to almost eliminate the adverse effects of sampling on the high frequency oscillation circuit. By constructing a pair of AND gate and OR gate, the opening/closing control circuit controls the opening and closing of both gates using a sampling signal based on the output signal of the low frequency oscillation circuit, and the phase signal as the phase information passing through is controlled by the opening/closing control circuit. After obtaining the signal, both gates can be controlled to close immediately, and reliable phase comparison can be achieved without the need for elements that operate at high frequencies all the time, resulting in lower power consumption. Furthermore, the phase difference signal creation circuit is configured with a two-stage shift register that receives the phase signal as input, and a phase difference stabilization circuit, and by creating a phase difference signal using information from two consecutive phase signals, more reliable A phase difference signal is obtained.

According to the present invention described above, it is possible to realize an electronic timepiece that takes full advantage of the high stability of a high frequency oscillation circuit with low power consumption. This will greatly contribute to the improvement of high-precision electronic watches.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of an electronic timepiece to which the present invention is applied. FIGS. 2A and 2B are circuit block diagrams of an embodiment of the phase comparator circuit according to the present invention. FIGS. 3 and 4 are voltage waveform diagrams of FIGS. 2(A) and (B), respectively. 1...Low frequency oscillation circuit, 2...
...High frequency oscillation circuit, 3...Comparison circuit, 4.41.42...Phase comparison circuit, 31...
...High frequency switching circuit, 32... Switching control circuit, 36.35... Phase difference signal creation circuit. Figure 1 Figure 2; Figure 3 Figure 4

Claims (1)

[Claims] A low frequency oscillation circuit that generates a reference signal, a frequency dividing circuit that divides the frequency of the reference signal to create a time reference signal, and a time display means that displays time using the time reference signal, and further generates a calibration signal. A high frequency oscillation circuit comprising a high frequency oscillation circuit, a comparison circuit for comparing output signals of the low frequency oscillation circuit and the high frequency oscillation circuit, and a correction circuit for correcting the time reference signal using the output signal of the comparison circuit. In the electronic clock that obtains a time reference calibrated by the electronic clock, the comparison circuit has a pair of AND gate and OR gate that both receive the high frequency signal of the high frequency oscillation circuit as input signals, and controls the opening and closing of the high frequency signal. a high-frequency switching circuit that outputs a phase signal made up of two signals; and a switching control circuit that controls opening and closing of the high-frequency switching circuit using a signal based on the output signal of the low-frequency oscillation circuit and controlling the closing based on the phase signal. and a phase difference signal creation circuit that creates a phase difference signal having a frequency according to the phase difference from the phase signal.