JPS58170119A - Semiconductor analog switch - Google Patents

Abstract

PURPOSE:To obtain a semiconductor analog switch which has reduced dependance on the input voltage with small error voltage, by using two switching field effect transistors (TR) having equal conductive channels and connected in parallel and a compensating field effect transistor having the same conductive type as the switching field effect transistors with the source and the drain short- circuited to each other. CONSTITUTION:When an analog switch is turned off, i.e. gates G1 and G2 are set at 0 and 1 respectively, the channels of the 1st and the 2nd TRs QMN2 and QMN2 disappear. Instead a channel is formed under the gate of the 3rd TR QCN1 for compensation whose gate is connected to the 2nd gate terminal which is driven with the polarity opposite to the 1st gate terminal. As the current is set at 0 at a moment when the analog switch is turned off, the carriers within the TRs QMN1 and QMN2 are discharged by 1/2 toward the source and drain sides respectively and then absorbed almost completely by the channel of the TR QCN1 and not delivered to the outside of the switch.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor analog switch, and more particularly to a spike charge compensated semiconductor analog switch suitable for high-precision analog circuits.

Conventional semiconductor analog switches include junction field effect transistors and metal oxide field effect transistors (hereinafter referred to as M
O8) is used.

For example, an example of an analog switch with 0MO8ICK6 is shown in FIG. 1, and an example of its application is shown in FIG.

In Fig. 1, QMN and QMP are N-channel and P-channel MO8 (Metal
Oxide 9emiconductor) type transistor, 011G, is the first. second gate terminal, 'r,
e'r is an input/output terminal of the analog switch. FIG. 2 shows an example in which this analog switch is applied to a Zampl hold circuit, where 5=rz, C is a capacitor, operational amplifier vI is an input voltage, and v and Fi are output voltages. Op Amp Hidden #1%
In FIG. 2, the analog switch 8. The waveform of the output voltage V when the switch is turned off is as shown in FIG. 3(a). That is, analog switch S
When , is o/, what was V I-V @ becomes,
When the analog switch S is turned off as shown in Figure 3 (-), a spike voltage is generated at V as shown in Figure 3 (a), and a spike charge enters from the gate circuit. The terminal voltage of the capacitor C increases, and an error voltage of 0V is generated between the input and output voltages.This error voltage is 0V.

is a serious obstacle when constructing high-precision analog circuits. As a means for reducing this error voltage ΔV, the channel widths of transistors Qmw and Qwp are made equal in FIG. 1. This is both the N and P channel transistor QIIw.

Since the polarity of the gate voltage of QMP is opposite, the polarity of the spike charge of both transistors is opposite, and this canceling effect is aimed at. Input voltage V at this time
FIG. 4 shows the relationship between + and error voltage lv. That is, if the power supply voltage is a symmetrical voltage of positive and negative, the error voltage Δv, >Q will be obtained when the input voltage v1=0. However, as is clear from the figure, the error voltage ΔV has an extreme dependence on the input voltage vI, and the spike charge cannot be canceled over the entire input voltage range. Fig. 5 shows an improvement by adding N and P channel transistors 1 and transistors Qc*tQcp for spike charge compensation to the switching transistors QMN and QMP, and these compensation transistors Qc, QC! P is approximately 1/of the channel width of the switching transistors Qm and Qmp.
In addition, the source and drain are short-circuited and connected to one terminal T of the analog switch. For example, this configuration is an N-channel switching transistor Qmw.
The spike charge entering from the gate terminal G,
This is intended to be canceled out by the spike charge from the gate terminal G, which operates with the opposite polarity to G of the same N-channel compensation transistor Qc wing. FIG. 6 shows the relationship between the input voltage Vs and the error voltage ΔV in this case. With this method, the dependence of the error voltage ΔV on the input voltage vt is improved to about 1710. However, the non-linearity of the error voltage V remains, and as shown in FIG. There is a problem in terms of yield due to large size dependence. That is, FIG. 7 shows the input voltage v1 and Vt. Error voltage ΔV with respect to the channel width Wcp of the compensation transistor QCP when
, where the error voltage Δv changes linearly with changes in the channel width WCP. This is an error voltage ΔV due to manufacturing variations in the process.

This means that the probability of obtaining the optimal product is low. A similar problem also occurs in the compensation transistor Qcw.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and provide a semiconductor analog switch with a small error voltage ΔV and less dependence on the input voltage Vt.

The features of the first invention that achieves the above object are as follows:
A first . a second field effect transistor; A third field-effect transistor having the same conductive properties as the second field-effect transistor has its source and drain connected to either one of the input terminal and the output terminal, and its gate connected to the other gate terminal. a field effect transistor;
, half of the sum of the channel areas of the second field effect transistor and the channel area of the third field effect transistor are approximately equal.

Furthermore, the second invention is characterized in that the first...
a second field effect transistor; a third field effect transistor of the same conductivity type as the second field effect transistor, whose source and drain are connected to the output terminal, and whose gate is connected to the other gate terminal;
゜Second. a fourth field effect transistor of the same conductivity type as the third field effect transistor, whose source and drain are connected to the input terminal, and whose gate is connected to the other gate terminal; ．． 2nd above 3rd
．． The reason is that the sum of the respective channel areas of the fourth field effect transistor is approximately equal.

The present invention provides that the spike charge that causes the error voltage ΔV is caused by carriers that constitute a channel essential for forming a field effect transistor, and that the total amount of carriers is determined not only in the planar shape of the transistor but also in the vertical structure. The aim is to compensate for spike charges using the total amount of carriers in the channel, taking into account the three-dimensional carrier distribution. transistor and
It has the same conductivity type as this, and its source and drain are short-circuited, and it is connected to the terminal of the switching transistor tfeJ, and the gate of the compensation field effect transistor is opposite to the gate of the switching transistor. The reason is that it is driven by a polar signal.

A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 8, the QM wing +QM)It is a switching first wing whose drain is connected to the input terminal T1, whose source is connected to the output terminal T, and whose gate is connected to the first gate terminal G1. Second 8MO8) transistor, Qc*1t!
The source and drain are output terminals T.

, the gate is connected to the second gate terminal G, respectively.
The third 8MO8) for compensation followed by U/Jister.

Here, the channel area 8cw1 of the third compensation transistor Qcws is calculated by the channel area 8cw1 of the transistor Qcws as shown in equation (1). Q-in-law 1 channel area S MNt, 8
This is approximately half of the sum of wwH.

In this embodiment, the first. Second. Equation (1) is satisfied by making the channel shapes of the third transistors Qmws e Qxxt a QC) 11 substantially equal.

In the above configuration, the first gate terminal Gt and the second gate terminal G are driven by signals of opposite polarity. Therefore, in order to turn on the input terminal Tle and the output terminal T8, the first gate terminal G1 is driven to 1 (high level) and the second gate terminal G is driven to 0 (low level). At this time, the first and second transistors Qww@*QM)1m are turned on and a channel is formed. Figure 9 shows the first example at this time. 2nd 8MO8) transistor QIIWI IQ
FIG. 9 (Jl
) is a plan view, (b) is a cross-sectional view of Mu, (C) is B-BM
It is a front view. In the figure, the hatched area is the channel, and it shows that carriers are induced by the application of the gate voltage. A characteristic feature of the application in the sample-and-hold circuit shown in Figure 2, or in the application of switches and capacitors, etc., is that the current in the channel is zero at the moment when the analog switch turns from on to off (in Figure 2, the capacitor C charging is completed). Therefore, carriers are distributed almost uniformly within the channel as shown in FIG. However, as shown in FIG. 9, carriers gradually decrease at the channel boundaries. So ζ is the first. When the second transistors Qm*1 and Qmxl are turned off, the carriers induced in the channel disappear through the source and drain. At this time, the carriers discharged from the channel cause the error voltage ΔV mentioned above. In FIG. 8, when the analog switch is off, that is, the gate G1 is 0 and the gate G is 1, the first . In place of the disappearance of the channel of the second transistor QMNI I Qmxl, a third compensating transistor Q c w 1 whose gate is connected to a second gate terminal driven with a polarity opposite to that of the first gate terminal A channel is formed under the gate. That is, the transistor Q c * 1 includes the transistor QM)11 * Q shown by hatching in FIG.
Similar to xxt, it is induced by carriers. Here, as mentioned above, since the t current is zero at the moment of switch-off, the first . Second transistor QMM@e
1/2 of the carriers in the channel of QMW@ are discharged to the source side and drain@. As shown in equation (1), the channel area Scwt of the transistor Q1 is the channel area Scwt of the transistor Qmwt *Qm*ffi, 8w*
Since it is approximately half of the sum of tl and 8MW1, the first . The carriers discharged from the channel of the second transistor Qmyt*Qmwt are almost completely absorbed into the channel of the third compensating transistor Qcws, and there is no bet on going in or out of the switch. That is, the spike charge is almost completely compensated for by the third compensation transistor. This compensation effect is the first and second
The transistor Q01. The channel shapes of QM) tl and the third compensation transistor Qcw1 are approximately the same.
When the shape is the same, the boundary lengths of channels exhibiting a delicate carrier distribution are also equal, so it appears the most. Also, the number of switching transistors is two compared to the conventional one, but
The size of each can be halved, so the exclusive area remains the same. Furthermore, the switching transistor Q Mll
Since l#QM)It and the compensation transistor Qcwt are the same size, manufacturing becomes easier and reliability increases.

As a result, as shown in FIG. 10, the error voltage ΔV with respect to the input voltage vI is almost flat, and there is almost no dependence on the input voltage, so that a semiconductor analog switch can be obtained that can be fully used in high-precision analog circuits.

In this embodiment, the first switch for switching is used. A third transistor Qcwl for compensation is installed only at the output terminal T, which corresponds to the load side of the second transistor QMNI, QM)II.
However, in this case, since the compensation effect is not closed inside the switch, it is necessary to make the impedance connected to the drive side of the input terminal TI and the load side of the output terminal T substantially stronger.

FIG. 11 is a diagram showing a second embodiment of the present invention.

In FIG. 11, Qcw* is a fourth compensating transistor whose source and drain are connected to the input terminal TtK= and the gate is connected to the second gate terminal G, and the others are shown in FIG. This embodiment has the same configuration as the first embodiment shown in FIG.

Here, the third . Fourth transistor Qmxt
The sum of the channel area of eQM*1 8cwH and 8cmg is:
As shown in equation (2), the channel area SMWI of the first and second transistors QMWI and QwwH for switching is
, 81111.

S eel + Scw1= 8 i*xt + S
MNI ``''・(2) Therefore, even when the impedances on the drive side and the load side are different, the amount of energy discharged from the channels of the first and second switching transistors QMN1 and QM1 to the source side and drain/side is The career is
The third one is almost completely for compensation. Fourth transistor Qcm,t
The spike charge is absorbed by the channel of Qcw1, and the spike charge is absorbed by the third channel for compensation. Almost completely compensated by the fourth transistor.

Furthermore, in this embodiment, the first. Second. 3rd, 4th
By making the channel shape of the transistor approximately strong, the expression () is satisfied, and as mentioned above, the boundary length of the channel exhibiting a delicate carrier distribution becomes equal, so that this compensation effect is maximized. In addition, one input terminal T1
1 output terminal T.

Since compensation transistors are provided on both of the input terminals TI, T, and K, a good compensation effect can always be obtained regardless of the applied circuit, regardless of the internal impedance of the circuit connected to the input terminals TI, T, and K.

Above 1. Although the second embodiment will be explained using an NMO8) transistor as an example, the present invention is not limited thereto.
It can also be applied to CMOS transistors as shown in FIGS. 2 and 13.

FIG. 12 is a diagram showing a third embodiment of the present invention.

In FIG. 12, the first . Second NM
O8) Ranjistaro's purchase t*QMxl and the third for compensation
The NMO8) U/distor Q c M I Fi has the same configuration as the first embodiment shown in FIG. 8"), QM?++
The Q iris has a drain connected to the input terminal T, a source connected to the output terminal T8, and a gate connected to the second gate terminal GL for switching. The sixth PuO2) transistor, Q c p t is the seventh −MO8) transistor for compensation, whose source and drain are connected to the output terminal T, and whose gate is connected to the first gate terminal G1, respectively. be.

Here, as shown in equation (3), the channel area of the third compensation transistor Q c w l is 8c, and the channel area of the seventh compensation transistor Q c p t is 8 ap.
1 for switching, and a first .l for switching. The channel area of the second transistor Q lid wteQww@ is 8w@, half of the sum of 8ww@, and the fifth transistor for switching. The channel area of the sixth transistor Qmpt *Qwvl is 8wp1.

8　M　F　m is approximately equal to half of the sum of m.

Fifth. 6th. Seventh transistor QMllll#QSei1゜Q cwt + Qmpt + Qmpt e Qcp
By making the channel shapes of l approximately equal, equation (1)
2〇) and the perimeters are also approximately equal.

Therefore, this embodiment also has the same effects as the first embodiment described above.

Furthermore, since this embodiment has an 0MO8 configuration, the spike charge compensation effect is greater than that of the first embodiment, which has a single channel configuration.

That is, the first gate terminal GK and the second gate terminal G,
Since it is driven by a signal of opposite polarity to the first one for switching, 2nd 8MO8) transistor Qm*teQ
m**, when a spike charge is injected from the gate to the drain to the source, the fifth. 6th P
MO8) In the transistor Q[1°QMPI, spike charges are discharged from the source drain to the gate, and the sum becomes close to zero. The first embodiment compensates for this near-zero spike charge, so it has a much greater compensation effect and can construct a semiconductor analog switch with much higher performance.

FIG. 13 is a diagram showing a fourth embodiment of the present invention, in which the first . 2nd 8 MO8) 57 Jister QM
Ift*Q allowance 1 and ll for compensation: 3. 4th 8MO
8) Transistor Q cr @ -e Q c y !
has the same configuration as the second embodiment shown in FIG.
5th for switching. 6th PMO8) Runstar Q
MP1eQwv@ and seventh PMOε transistor for compensation Q CP I Fi It has the same configuration as the third embodiment shown in FIG.

In FIG. 13, Qcp@u is an eighth transistor for compensation whose ground and drain are connected to the human power terminal T1, and whose gate is connected to the first gate terminal GtK.

Here, as shown in equation (4), the third . Channel area of fourth transistor Qcw@*QcNt 8cwt
e 8 cm, and the 7th for compensation. Channel area of the eighth transistor Qc11QCP, 5c1s8ctl
and the first for switching. second transistor Qw
The channel area of w* eQww@ is the sum of 8 MW 1° S Ml and the 5th channel area for switching. 6th transistor QMPI
The channel area of e Qmpt is approximately equal to the sum of 8wp1°8MP1.

S CM, + 8 cat = 8 cP% + S
ell = S MNI + S 1oll = S
Mal + S MN (4) Furthermore, in this embodiment, by making the channel shapes of the first to eighth transistors approximately equal, the formula (2
) formula et al.) is satisfied.

Therefore, in this embodiment as well, the above-mentioned 1st, 2nd, . There are effects similar to those of the third embodiment.

In the embodiments of the present invention, a MOS transistor has been described as an example, but the present invention can also be applied to a junction field effect transistor.

As described above, according to the present invention, it is possible to obtain a semiconductor analog switch with a small error voltage ΔV and less dependence on the input voltage vIK.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional semiconductor analog switch, Figure 2 is an example of an application of a semiconductor analog switch, Figures 3 and 4 are diagrams showing the operation and performance of the circuit in Figure 1, and Figure 5 is Other conventional semiconductor analog switch configuration diagrams, Figures 6 and 7
The figure shows the characteristics of the circuit shown in Fig. 5, Fig. 8 is a block diagram showing the first embodiment of the present invention, and Figs. 9 and 10 show the operation and characteristics of the circuit shown in Fig. 8. , tJX11 figure, 12th
Figure 13 shows the second embodiment of the present invention. wJ3. A conceptual diagram showing the fourth embodiment is shown. Qwwt *Qww*”・NMO8 for switching
Ransistor, QNPI tQwx...Switching PMO8) Ransistor, Qcpt e QC? !・・・
・Compensation PMO8) transistor, TI...input terminal,
TI...Output terminal, G1-478 Fig. 2 1st QC Δη

Claims (1)

[Claims] 1. Each drain is an input terminal, each source is an output terminal,
The same circuit where each gate is connected to one gate terminal respectively.
The first type of conductivity. a second field effect transistor, and the @1
．． a third field effect transistor which is of the same conductivity type as the second field effect transistor, has a source and a drain connected to one of the input terminal and the output terminal, and has one gate connected to the other gate terminal; A semiconductor analog switch, characterized in that the sum of the channel areas of the first field effect transistor #I3 is approximately equal to the sum of the channel areas of the field effect transistor #I3. 2. In claim 1, the above 1.2.
A semiconductor analog switch characterized in that each channel shape of the third field effect transistor is substantially equal. 3. Each drain is an input terminal, each source is an output terminal,
The same circuit where each gate is connected to one gate terminal respectively.
The first type of conductivity. a second field effect transistor and aI#
1. of the same conductivity type as the second field effect transistor;
a third field effect transistor having a source and a drain connected to the output terminal and a gate connected to the other gate terminal; Second. a fourth field effect transistor having the same conductivity type as the third field effect transistor, having a source and a drain connected to the input terminal, and a gate connected to the other gate terminal; ．． The sum of the respective channel areas of the second field effect transistor and the third field effect transistor. A semiconductor analog switch characterized in that the sum of the areas of each channel of the fourth field effect transistor is approximately equal. Table In claim 3, the above-mentioned items 1 and 2.
$3. A $4 semiconductor analog switch characterized in that each channel shape of a field effect transistor is substantially equal. & Each drain is an input terminal, each source is an output terminal,
The first gate terminal is connected to one gate terminal of each gate terminal.
The first type of conductivity. a second field effect transistor; and a third field effect transistor of a first conductivity type, the source and drain of which are connected to one of the input terminal and the output terminal, and the gate of which is connected to the other gate terminal. , each drain is connected to the input terminal, each source is connected to the output terminal, and each gate is connected to the other gate terminal. a sixth field effect transistor;
a seventh field effect transistor of a second conductivity type, the teeth and the drain of which are connected to one of the input terminal and the output terminal, and the gate of which is connected to the one of the gate terminals; half of the sum of the respective channel areas of the second field effect transistor, the channel area of the third field effect transistor, and the fifth. half of the sum of the channel areas of the sixth field effect transistor and the seventy-first field effect transistor;
A semiconductor analog switch characterized in that the channel area of the field effect transistor □ is approximately equal to that of the field effect transistor □. 6. In claim 5, the above-mentioned items 1 and 2.
Third. @5. 6th. A semiconductor analog switch characterized in that each channel shape of a seventh field effect transistor is substantially equal. 7. Each drain is an input terminal. Each source is an output terminal.
a first one in which each gate is connected to one gate terminal respectively;
The first type of conductivity. a second field effect transistor; a third field effect transistor of a first conductivity type, the source and drain of which are connected to the output terminal; and the gate of which is connected to the other gate terminal; and the source and drain of which are connected to the input terminal. a fourth field effect transistor of a first conductivity type having gates connected to the other gate terminal, each drain connected to the input terminal, each source connected to the output terminal, and each gate connected to the other gate terminal; the second connected to the terminal respectively
Conductivity type 5. a sixth field effect transistor; a seventh field effect transistor of a second conductivity type, the source and drain of which are connected to the output terminal, and the gate of which is connected to the one gate terminal; and the source and drain of which are connected to the input terminal; a second conductivity type eighth field effect transistor whose gate is respectively connected to the one gate terminal; The sum of the respective channel areas of the second field effect transistor and the third field effect transistor. The sum of the respective channel areas of the fourth field effect transistor and the fifth. The sum of the channel areas of the sixth field effect transistor and the seventh field effect transistor. A semiconductor analog switch characterized in that the sum of the respective channel areas of the eighth field effect transistor is substantially larger. & In claim 7, the above-mentioned items 1 and 2.
Third. 4th. Fifth. 6th. 7th. A semiconductor analog switch characterized in that each channel shape of an eighth field effect transistor is substantially the same.