JPS58168351A - Parallel transmission system - Google Patents

Abstract

PURPOSE:To reduce the burden of the delay compensation in each terminal, by compensating the delay due to exchange, which exist on the way of each transmission line, in an exchange just before a receiving terminal and compensating only a final small delay error in the receiving terminal. CONSTITUTION:A transmitting terminal 1 divides a high-speed data frame into three (data frames A-C) and transmits them to a receiving terminal 2. A station number information part area consisting of several bits is provided in each divided data frame; and each time every data frame passes through the exchanges (3-6), the number of exchanges is counted, and the counted value is written in said area. In an exchange 7, a station number information detecting circuit 31 reads out station number information of each data frame, and a controlling circuit 37 operates selecting circuits 32 and 36 in accordance with this value, and thus, the data frame passes through one of delay circuits 33-35 different in delay time, and as the result, the delay time is compensated in accordance with the number of exchanges.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a parallel transmission method for dividing one data frame and transmitting the divided data frames in parallel between terminals via a plurality of transmission paths.

(2) Background of the technology Current digital networks are based on a frequency band of 4@Hz (transmission speed*44 L bits/S), which is the main frequency band for voice signals. In such a network, 64
A data frame of bits/S is transmitted between terminals via one transmission path.

In this case, one or more switching stations exist on the transmission path between the terminals.

By the way, in the near future, large amounts of information such as single signals will be transmitted in a frequency band of 4 MHz (transmission speed 100 Mbit/hata).
It is conceivable to transmit this information using the low-speed transmission path of the digital network described above, but in this case, it is necessary to use a plurality of transmission paths. That is, it is necessary to divide one data frame into a plurality of parts and transmit them in parallel through each transmission path.

In the parallel transmission described above, the maximum delay is due to the switching center in the middle of the transmission path. Therefore, in parallel transmission of data frames from one terminal to another, it is necessary to compensate for these delays and synchronize the data frames. One possible method for this is to compensate the delay at each receiving terminal all at once, but in this case, there is a problem that the burden on each terminal is heavy, and therefore the manufacturing cost is high.

(3) Purpose of the Invention The purpose of the present invention is to compensate for the delay caused by the switching center located between each transmission path at the switching station immediately before the receiving terminal, and to compensate only for the final small delay error at the receiving terminal. First, it is intended to reduce the burden on each terminal, thereby reducing manufacturing costs and solving the above-mentioned problems.

(4) Structure of the Invention In order to achieve the above-mentioned object, according to the present invention, one data frame is divided and transmitted in parallel from a transmitting terminal to a receiving terminal via a plurality of transmission paths. In this method, a field number information section is provided for each of the divided data frames, and the station number information section data of the data frame is counted up or down at an intermediate switching station of each transmission path, and the station number information section data of the data frame is counted up or down. Delaying each of the divided data frames by a delay time based on the station number information part data at the final switching station, and compensating for the delay error of each of the nine divided data frames at the receiving terminal; A parallel transmission system is provided that is characterized by frame synchronization.

(6) Examples of the invention Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing a parallel transmission system as an embodiment of the present invention. In FIG. 1, 1 is a transmitting terminal and 2 is a receiving terminal. Reference numerals 1 to 1A denote switching stations, and each switching station is connected by a plurality of low-speed transmission lines K (not shown). If the transmitting terminal 1 transmits a high-speed data frame to the receiving terminal 2 by dividing it into three parts, a transmission path is first set. For example, as shown, A: 5→4-→5→7 B: 5→4→6→5→7 C:! S transmission paths of 1-44→7 are set. When the transmission paths are different in this way, the delay time (transmission time) is different.

This delay time mainly depends on the number of exchanges.

According to the present invention, a station number information section of several bits is provided in each divided data frame, and each time each data frame passes through an exchange, the number of exchanges is counted and the counted value is stored in the station number information section. I am writing.

No. 21111 is a block circuit diagram of the rounding position for counting the number of exchanges through which a data frame passes in each exchange. The data frame is supplied to a delay circuit (a turtle that collectively represents the functions of Ii) 21, and a detection circuit 22.
detects the station number information part of the data frame. This detected value is multiplied by +1 by the adder circuit 25. The 0th order 1 control circuit 25 operates the selection circuit 24 and writes the result of the arithmetic operation of the adder circuit 25 into the position of the station number information part of the data 7 frame. This causes the number of exchanges to be counted up.

Therefore, at the exchange 7 in FIG.

The values of the station number information section for the data frames that transmitted B and C are @4Ta and @5'', respectively.

5".Next, in this exchange 7, the number of stations is 14".
w 5 m , ' m 5''K[Compensation for the same delay time is performed.

FIG. 5 is a circuit diagram of a device for compensating the delay time of a data frame at the exchange 7 of FIG. 1 in accordance with the number of exchanges through which the data frame has passed. In FIG. 5, each data frame is supplied to a station number information detection circuit 51 for reading out the value of its station number information section. Control circuit 37
The selection circuits 52, 34, . ! You will pass through one of the 15. As a result, the delay time is compensated according to the number of exchanges. Note that the number of delay circuits is set according to the possible number of switching stations.

At the receiving terminal 2, delay errors in each of the seven data frames are compensated. This late arrival error is smaller than the delay error due to the number of exchanges passed through.

FIG. 4 is a block circuit diagram of a rounding device for compensating for delay errors in each data frame at the receiving terminal 2 of FIG. 411, each data frame, in this case, each data frame divided into S memory 41;
42 and 4S, respectively. At this time, the arrival time of each data item IJ41 is detected by the delay detection circuit 44, and based on this detection, the delay control circuit 45 detects each memory IJ41.

Controls the data transmission timing of 42.45.

As a result, the seven frames of data sent out from the memories 41, 42, and 45 are synchronized.

In the above-described embodiment, the terminals 1 and 2 are specified as the transmitting terminal and the receiving terminal, and the exchange 7 is specified as the final station, but these are all specified for convenience, and the terminals 1 and 2 are specified as the final station. 2 is equivalent, and is equivalent to exchanges 3 to 74. In the above description, the value of the station number information part of the data frame is counted up, but it may be better to give a fixed value in advance and count down.

(According to the present invention, as described in the detailed description of the invention, delay time compensation is
The compensation function of the first stage is common to multiple terminals connected to the last switching center, so the terminal The number of personnel required can be reduced, and therefore manufacturing costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a parallel transmission system as an embodiment of the present invention, FIG. 2 is a block circuit diagram of a device for counting the number of exchanges that a data frame passes through in each exchange, and FIG. 4 is a circuit diagram of a rounding device that compensates for the delay time of the data frame at the 10th exchange station 7 according to the number of exchange stations through which the cough data frame has passed, and FIG. 1 is a block circuit diagram of an apparatus for compensating delay errors in data frames; FIG. 1: Sending [4 stations 2: Receiving terminal stations 5 to 7: Switching stations IBeC@transmission line. Patent applicant Fujitsu Limited Patent attorney Akira Yamaguchi Part 3 Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akira Yamaguchi

Claims (1)

[Claims] t In a rounding parallel transmission method in which 7 frames of data are divided and transmitted in parallel from a transmitting terminal to a receiving terminal via a plurality of transmission paths, a station number information section is provided for each of the divided 9 data frames, and each The station number information part data of the seven data frames is counted up or down at the intermediate switching station of the transmission path, and the common final switching station of each transmission path counts up or down the number of stations data by the delay time based on the station number information part data. Each of the divided 9 data frames is delayed, and the receiving terminal synchronizes the data frames with Jin and K, which compensates for the delay error of the divided nine data 7 frames. Parallel transmission method.