JPS58168320A - Flip flop circuit - Google Patents
Flip flop circuitInfo
- Publication number
- JPS58168320A JPS58168320A JP57050111A JP5011182A JPS58168320A JP S58168320 A JPS58168320 A JP S58168320A JP 57050111 A JP57050111 A JP 57050111A JP 5011182 A JP5011182 A JP 5011182A JP S58168320 A JPS58168320 A JP S58168320A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- output
- trs
- load
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
Abstract
Description
【発明の詳細な説明】
（１） 発−の技術分野
本発明は集積回路用の７す、グア０．ｆ囲路に関し、４
１にマスタ・スレイｆｉｊ１回路のスレイプ部の低電力
化を計った７リツグフロツ！回路形成に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention is directed to a 7-stage, a 7-stage, a 7-stage circuit for integrated circuits. Regarding the f-wall, 4
7 Ritz Flots designed to reduce the power consumption of the slave section of the master/slay fij1 circuit! It is related to circuit formation.
（２）従来技術と問題点 第１図は従来の７リツグ７０ッ！回路を示す。(2) Conventional technology and problems Figure 1 shows the conventional 7-rig 70! Shows the circuit.
図においてマスタ一部はゲート１．ｒ−）２、ｒ−ト３
およびインバータ４よりなシデータ人力りおよびクロ、
クツ４ルスＣＫを入力し、データが負入力であってクロ
、クノクルスが正から負に反転するとｒ−１−１の出力
Ｎ１は高レベルにｒ−ト３の出力Ｎ！は低レベルにイン
バータ４の出力Ｎ、は高レベルとなる。スレイプ部はト
ランジスタＴ１〜Ｔ−およびトランジスタ’ｒ、、’ｒ
、よりなシそれぞれマスク部よりクロックツ奢ルス、出
力Ｎ、およびＮ１を入力して、その出力Ｑ、Ｑは負荷容
量ＣＬヲ駆動する。ここにおいてＣＬは一般に配線容蓋
で多りＬＳＩの大規模化にともなって大きくなる傾向に
ある。大容量ＣＬ會急速に充電させるためＶＣはｆ”イ
ーｆレッジ、ン型トランジスタＴ、、Ｔ。In the figure, the master part is gate 1. r-)2, r-to3
and inverter 4 manual power and black,
When CK is inputted and the data is a negative input and the clock is reversed from positive to negative, the output N1 of r-1-1 becomes high level and the output N of r-to3! is at a low level, and the output N of the inverter 4 is at a high level. The sleeve section includes transistors T1 to T- and transistors 'r, ,'r
, the clock pulses, outputs N, and N1 are inputted from the mask portions, respectively, and the outputs Q, Q drive the load capacitance CL. Here, the CL is generally found in the wiring enclosure, and tends to become larger as the scale of the LSI becomes larger. In order to quickly charge a large capacity CL, VC is an f''edge, n-type transistor T,,T.
のり“−ト輪を大きくし大′−流を流せるようにする必
資があるがこのため定常状態においても電源からＧＮＤ
に大電流が流れ電力消費が大きくなる。It is necessary to make the glue wheel larger so that a large current can flow, but for this reason even in steady state there is no connection between the power supply and the GND.
A large current flows through the circuit, increasing power consumption.
このようにＩ／Ｄ［フリ、ｆフロ、！では定常状態の消
費電力が大きくなるがこの部分はスレイプ部で消費され
マスク部は負荷容量が小さいことから電流は少なくてよ
い。In this way, I/D [Furi, f-Flo,! In this case, the power consumption in the steady state is large, but this portion is consumed in the scrape portion and the mask portion has a small load capacity, so the current may be small.
（３）発明の目的
本発明は上記従来の欠点Ｋかんがみ定常状態における消
費電力を少なくし九低電力盤フリ、グフロ、！回路を提
供することを目的とする。(3) Purpose of the Invention The present invention overcomes the above-mentioned drawbacks of the conventional art by reducing power consumption in a steady state, making it a low-power board! The purpose is to provide circuits.
（４） 発明の構成
この目的は本発明によればマスク部とスレイプ部を有し
、マスク部にデータ入力とクロックｊ４ルスを入力しス
レイプ部よ〉出力Ｑおよび互を出力するマスク・スレイ
プ型７９１７７０１７回路において、該スレイプ部の出
力Ｑ用フリ、ｆフロ。(4) Structure of the Invention This object is a mask-slape type according to the present invention, which has a mask section and a slepe section, inputs data input and clock j4 pulses to the mask section, and outputs an output Q and an output from the slepe section. In the 79177017 circuit, the output Q flow of the scrape section, f flow.
グの負荷として直列接続された第１．１１２のトランジ
スタと、出力画用７リツ／フロ、ｌの負荷として直列接
続され九＠３．第４のトランジスタを設け、該第１．第
３のトラ７ゾスタを該クロ、り・臂ルスでオン・オフ制
御し、該第２．第４のトランジスタを鋏マスク部の出力
でオン・オフ制御するようにし九ことを特徴とする低電
力蓋７す、ｆ７０ッ！回路を提供することによって達成
される。The 1.112nd transistor is connected in series as a load for the output voltage, and the 9th transistor is connected in series as a load for the output voltage. A fourth transistor is provided, the first . The third Tora 7 Zosta is controlled on and off by the black, rear and armrests, and the second. The fourth transistor is controlled on and off by the output of the scissor mask section. This is achieved by providing a circuit.
（５）発明の実施例
以下本発明にかかる実施例を図面により詳細に説明する
。(5) Embodiments of the Invention Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.
８２図は本発明の実施例を示し、同図において第１図と
同−表はたらきをする部分は第１図におけると同一の記
号を用いる。第２図を第１図と比較するとマスク部は同
一のに／Ｄ［回路を用いるがスレイプ部にスイ、チ／ダ
用負荷としてトランジスタＴｌ＠ ｅ Ｔ’ｉｔ ｅ
’ｒｔ＊ ｌ Ｔｔｓｔ−接続しトランジスタＴ１ｏの
ｒ−）をクロックＣＫに、テロのｒ−トをノードＮｓに
、Ｔ’ｔｓのｒ−）をクロ、りＣＫに、ＴＩＯダートを
ノードＮｍ Ｋ接続する。上記トランジスタＴ、・〜Ｔ
ｔｓはエンハンスメント製でも低ドーズのディ／し、シ
、ン型でもよいがエンハンスメン）Ｉｔの場合にはハイ
レベルを維持するためには第２図のようにレベル維持用
デプレ、シ冒ントランノスタ７１４ ＋ Ｔｏが必要と
なる。トランシス／Ｔ１４．テ１ｓ□は第１図のディグ
レッジ、ントツンゾスタと仁とな〉レベル維持用である
のでｒ−）幅は小さくてよくし九がって定常的な消費電
力は少ない。FIG. 82 shows an embodiment of the present invention, in which the same symbols as in FIG. 1 are used for parts having the same functions as those in FIG. 1. Comparing Fig. 2 with Fig. 1, we can see that the mask part is the same, but the /D circuit is used in the scrape part, and the transistor Tl@ e T'it e is used as the load for the chip/da.
'rt* l Ttst- connected, r-) of transistor T1o to clock CK, r- of T'ts to node Ns, r-) of T'ts to clock, R-CK, TIO dart connected to node Nm K do. The above transistors T,...T
ts may be made by Enhancement or a low-dose D/C type. + To is required. Transys/T14. Since TE1s□ is for maintaining the level of the degree shown in FIG.
第３図に第２図の回路のタイムチャートを示す。FIG. 3 shows a time chart of the circuit of FIG. 2.
このタイムチャートにし九がって本発明の囲路の動作を
説明する。ＨＳ図においてＤはデータ入力、ＣＫはタロ
、夕、ｑは出力、互は反転出力を示す。The operation of the enclosure of the present invention will be explained with reference to this time chart. In the HS diagram, D indicates data input, CK indicates taro, q indicates output, and mutual indicates inverted output.
Ｄ１１７す、７’７Ｅｍ、７’０場金出力Ｑ、Ｑはクロ
ツタの立上〉で変化する。D117S, 7'7Em, 7'0 The field money output Q, Q changes with the rise of the clover.
第３図においてまず初期状態としては出力ｑが高レベル
、可が低レベルＯ場会を考える。この場谷１−１１では
負荷トランジスタテ１・はオン、Ｔｌｌはオフ、Ｔｌｍ
はオン、ｅｌｍはオンであ）駆動トランジスタはｉ息が
オン、Ｔｓがオン、Ｔ１がオン、Ｔ４がオン、Ｔｓがオ
フ、テ・がオフとな〉スレーノ部ｏｅ側では駆動トラン
ジスタオンに対して負荷トランジスタがオフとなり、Ｑ
側では駆動トランジスタオフに対して負荷トランジスタ
がオンとなって電流としてはトランジスタ１口のレベル
維持用トランジスタからの電流のみとなシ消費は少ない
。次にデータ人力りが反転して低レベルとなシつぎのク
ロ、りでＱ、Ｑが反転する場合を考える。ｔ−ｔｌです
でにマスク部はデータ入力にし九がって反転しノードＮ
、は低レベル、ノードＮ、は高レベルとなっている。こ
の状態ではトランジスタＴｌｌはオンとなり駆動トラン
ジスタＴｓもオンとなっているがクロックが低レベルで
あるためトランジスタＴ１・がオフしておシトツンゾス
タＴ１・、ＴＩの経路には電流が流れない。つづいてｉ
＝ｃ ｔｓでクロ、りが高レベルになるとトランジス
タＴ１・がオンになシま九ＱｌｌｌのトランジスタＴ４
ｐＴＩの経路がオンになるためＱは低レベルとなりトラ
ンジスタＴｓがオフとなる。これによってトランジスタ
Ｔ１・、ＴＩの経路からＴ１・１７１１のｒ−）電極に
ハイレベルが入力しているため大きな電流がＣＬを充電
し出力が反転する。反転が終った状態では各トランジス
タは画側がＴ１・がオン、ＴＩがオン、ＴＩがオン、Ｔ
Ｉがオフ、Ｔ３がオフとな）Ｑ側が７１１がオン、Ｔ１
１がオフ％Ｔ４がオン、テＳがオン、Ｔ・がオンとな如
それぞれ負荷側あるいは駆動側がオフとなるので電流は
流れずトランジスタＴ１酪の電流のみとなり消費電力は
少ない。In FIG. 3, first consider an initial state in which the output q is at a high level and the output is at a low level. In this case 1-11, the load transistor T1 is on, Tll is off, and Tlm
is on, elm is on) The drive transistor is on, Ts is on, T1 is on, T4 is on, Ts is off, T is off. The load transistor turns off and Q
On the other hand, when the drive transistor is off, the load transistor is on, and the current is only from one level maintenance transistor, so consumption is small. Next, let us consider a case where the data input is reversed and becomes a low level, and Q and Q are reversed at the next black mark. At t-tl, the mask part is already inverted according to the data input, and the node N
, is at a low level, and node N is at a high level. In this state, the transistor Tll is on and the drive transistor Ts is also on, but since the clock is at a low level, the transistor T1 is turned off and no current flows in the path of the transistors T1 and TI. followed by i
=c When the voltage at ts becomes high level, the transistor T1 is turned on.
Since the pTI path is turned on, Q becomes low level and transistor Ts is turned off. As a result, since a high level is input from the path of the transistors T1 and TI to the r-) electrode of T1 and 1711, a large current charges CL and the output is inverted. When the inversion is complete, each transistor is on the image side, T1 is on, TI is on, TI is on, T
I is off, T3 is off) 711 is on, T1 on the Q side
When T4 is on, TS is on, and T.
第４図にスレイプ部Ｏ電流を示す。上述の理由によ）本
回路ではスイッチング時のみに２で示すような大きな過
渡電流が流れるが定常状態では少ない。これに対して従
来の１／ＤＷにおいては第４図でＩＫ示すように定常状
態でも大きな電流が流れる。Figure 4 shows the O current at the scrape section. For the reason mentioned above) in this circuit, a large transient current as shown by 2 flows only during switching, but it is small in the steady state. In contrast, in the conventional 1/DW, a large current flows even in a steady state, as shown by IK in FIG.
（６） 発明の効果
以上詳細に説明したごとく本発明によればスレイゾ部に
スイッチング用負荷トランジスタを接続することによ）
スイッチング時だけに大電流を流しうるようＫして定常
状態では消費電力をおさえるようＫしたものであって、
本発明は集積回路用７９、ｆフロッグ回路に適してその
効果は特に大なるものかあゐ。(6) Effects of the Invention As explained in detail above, according to the present invention, by connecting a switching load transistor to the SLZ section)
The K is set so that a large current can flow only during switching, and the K is set to suppress power consumption in a steady state.
The present invention is suitable for integrated circuits and f-frog circuits, and its effects are particularly great.
第１図は従来のＤｊｌ１７す、ｆｙａ、ｆｏＩｍＷｒＥ
、第２図は本発明Ｋかかる７リツｆ７０ッグ回路の１実
施例の回路図、第３図は第２図の回路の動作を示すタイ
ムチャート、第４図は本発明Ｋかかる回路の電流特性を
示す図である３゜
図においてＴ１・ｐ Ｔ ＄１ ａ Ｔ １１ ｅ ”
３ｍがそれぞれ負荷トランジスタを示ス。
特許出願人
富士通株式会社
特許出願代理人
弁理士青水 朗
弁理士西舘和之
弁理士内田幸男
弁理士 山 口 昭 之
第１図
つ け
＝Ｃ上
第２図
？益
ＣＬ
第３図
１ １１
第４図Figure 1 shows the conventional Djl17, fya, foImWrE
, FIG. 2 is a circuit diagram of one embodiment of the 7-bit f70 circuit according to the present invention, FIG. 3 is a time chart showing the operation of the circuit of FIG. 2, and FIG. 4 is a current diagram of the circuit according to the present invention. In the 3° diagram showing the characteristics, T1・p T $1 a T 11 e ”
3m each indicates a load transistor. Patent Applicant Fujitsu Limited Patent Application Agent Patent Attorney Akira Aomi Patent Attorney Kazuyuki Nishidate Patent Attorney Yukio Uchida Patent Attorney Akira Yamaguchi Figure 1 attached = Figure 2 on C? Profit CL Figure 3 1 11 Figure 4
Claims (1)
り四ツク／４ルスを入力しスレイプ部よシ出力Ｑおよび
互を出力するマスタ・スレイプ製フリッｆｙａッデ回路
において、諌スレイプ部の出力Ｑ用７リツｆ７’ｃ１．
ｆｌＤ負荷として直列接続され要用１．第２のトランジ
スタと、出力互用フリッｆ７０ツノの負荷として直列接
続された第３゜第４のトランジスタを設け、＃謔１．謔
３のトランジスタを鋏クロ、クツ臂ルスでオン・オフ制
御し、該第２．第４０）ランジスタを該マスク部の出力
でオン・オフ制御するようにした仁とを特徴とする７リ
ツｆ７０ッ！回路。In a master/sleip flipfyadde circuit that has a master part and a sleip part, the mask part takes data input, and the 4x/4 pulse is input, and the sleip part outputs the output Q and the output of the yoshisrap part. 7ritsu f7'c1 for Q.
Connected in series as flD load and required 1. A third transistor and a fourth transistor connected in series as a load of the second transistor and the output compatible flip f70 horn are provided. The third transistor is controlled on and off using the scissors and the elbow of the shoe. 40th) A 7-bit f70 featuring a transistor in which on/off control is controlled by the output of the mask section! circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050111A JPS58168320A (en) | 1982-03-30 | 1982-03-30 | Flip flop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050111A JPS58168320A (en) | 1982-03-30 | 1982-03-30 | Flip flop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58168320A true JPS58168320A (en) | 1983-10-04 |
Family
ID=12849976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57050111A Pending JPS58168320A (en) | 1982-03-30 | 1982-03-30 | Flip flop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58168320A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0282711A (en) * | 1988-09-19 | 1990-03-23 | Fujitsu Ltd | Transmission gate type flip flop |
-
1982
- 1982-03-30 JP JP57050111A patent/JPS58168320A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0282711A (en) * | 1988-09-19 | 1990-03-23 | Fujitsu Ltd | Transmission gate type flip flop |
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