JPS58168172A - Multiprocessor debugging device - Google Patents

Abstract

PURPOSE:To inhibit the execution such as unnecessary memory access and to avoid confusion of a common bus, by providing a control circuit which inputs a debug monitor program start signal and starts debugging when a true value is inputted. CONSTITUTION:The 1st and the 2nd CPUs 1, 2, a debug monitor program 3, an application program 4, a typewriter 5 giving instruction, and the 1st flip-flop 6 are connected mutually via a common data bus 10. When the 2nd flip-flop 7 stores the stop state of the CPU1 and the debug monitor program start signal and a true value are inputted from the 1st flip-flop 6, a control circuit 9 starts debugging.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides at least two or more central processing units (hereinafter referred to as CP).
Conview tag with (abbreviated as σ).

This is for a multiprocessor hang device that performs depacking.

Traditionally, in the case of machines that develop programs for microcomputers, an IC debug monitor program other than Application Progera A to be debugged is installed in the main memory, and the debug monitor program checks the contents of a specified address in the main memory. Modify or refer to CPU internal registers.

Performs value settings, etc., and performs detailed program debugging.

Now, program debugging as described above is started by inputting the interrupt signal 'f: CPσ, and during debugging, the main memory and CPU internal registers are referenced and modified in response to a debugging start command from an external typewriter. do. When the execution of debugging is completed, the device waits again for a debugging end command from an external typewriter and enters an idle state. That is, since the CPU does not stop and continues to maintain an idle state, it continues to receive seven commands from the main memory. When a command instruction to execute an application program is received from an external type 2 iter, the return address from the debug execution interrupt is set to the value specified by the TIG writer command, and the target application program is executed by executing the return instruction. Start execution.

However, the above-described debugging method is inappropriate for debugging a multiprocessor system composed of a plurality of e C'PUs.

In other words, when depacking as described above is performed on a multiprocessor system consisting of 111f CPUs with several fi CPUs, the debug monitor program cannot be stopped midway, and even in the idle state waiting for command input, the instructions in the main memory are As a result, each CPU that accesses the above-mentioned hidden part always includes an idle CPU, congesting the common bus of the multiprocessor system and significantly reducing the performance of the multiprocessor system. lower.

In view of the above-mentioned drawbacks, the present invention executes a debug monitor program when at least one CPU is in a stopped state, and when the debug monitor program ends, executes a debug monitor program termination instruction and does not execute subsequent programs. By doing so, a multiprocessor debugging device is provided that prevents congestion of a common bus in a multiprocessor system by prohibiting execution of unnecessary memory accesses.

An embodiment of the present invention will be described below with reference to the drawings.

The drawing is a block diagram of a multiprocessor depacking device in one embodiment of the present invention. In the figure, 1 is f! J
1 is a CPU, 2 is a second CPU, a is a debug monitor program stored in a storage device other than the main memory (not shown), 4 is an application program stored in the main memory, 6 is an external From 1st. Second CPU1. A typewriter 6 gives instructions to the first ``2'' and ``6'' outputs a debug monitor program start signal to the first ``1''. 2nd CP
This is a 5g1 7 lip-flop feeding U1.2.

The configuration of the first CPU 1 will be described in more detail below.

7 is a second 7 lip-flop that stores the stop state of CPU 1 or the application program execution state;
It is allocated to an appropriate location in the address space of PU1. 8 is the output of ffJ2's 7 lip/70 tube 7 and the first
The flip 70 is an AND element that takes the logical product of the debug monitor program start signal of the switch 6, and outputs the debug monitor program start signal only when the CPU 1 is in a stopped state. Reference numeral 9 denotes a control circuit that starts debugging control in response to a debug monitor program start signal sent from the AND element 2, and a buffer 11 that temporarily stores the program of the debug monitor program 3 via the common data bus 1o.
Enter from. A debug monitor program counter 12 is used only for the program progress state of the debug monitor program 3, and the address of the debug monitor program 3 is specified by the count number. Although not shown, the second CPU 2 also has the same configuration as the first CPU 1.

The operation of the multiprocessor debugging device configured as described above will be described below.

(~ First, if only the first CPU 1 is in a stopped state, the second 7-lip flop 7 is outputting a High signal. On the other hand, in order to perform debugging, the first clip/70 lip flop 7 is output by operating the typewriter 6. 6 sends a digh signal to the AND element 8, and also sends information (hereinafter referred to as true value) to the control circuit 9 to start executing the debug program 3.
1) Output. Therefore, the control circuit 9 outputs the depack monitor program start signal of the AND element 8 and the first control circuit 70.
Start debugging by straightening from Tsug 6. That is, the control circuit 9 sets an initial value in the debug monitor program counter 12 and also sets the debug monitor program counter 3 to an initial value.
The program is inputted from the common data bus 1o via the buffer 11. The control circuit 9 then interprets the program content of the debug monitor program 3, performs an operation corresponding to the command of the program content, and then inputs the next program content stored in the buffer 11.

Thereafter, the operation continues in the same manner, and one program depack is performed, such as referencing and modifying the contents of main memory # (not shown), and setting reference values of the CPU built-in registers.

Since an instruction indicating the end of program execution is provided at the final location of the debug monitor program 3, when the control circuit 9 interprets and executes this program execution end instruction, the subsequent debug monitor program 3 Stop progressing. That is, since the control circuit 9 stops the access operation with the debug monitor program 3, the exchange of information between the control circuit 1@9 and the debug monitor program 3 is no longer carried out on the common data bus 10.

(B) Furthermore, when the first CPU 1 is in the RUN state, that is, executing the application program 4, and the second CPU 2 is in the stopped state, the second 7-lip flop 7 is in the Lo
By outputting the vv signal to the AND element 8,
The AND element 8 does not output the Depach 2 monitor program start signal to the control circuit 9. Therefore, the first CPU 1 continues executing the application program 4 without starting the debug monitor program 3. On the other hand, the second CPU 2 in the stopped state is connected to the first CPU 1 by the second 7 lip 70 knob 6 and the internal clip frog (as explained in ~).
Start debugging similar to .

q Also, when the first CP (Jl) and the second CPU 2 are both in a stopped state, the first flip-flop 6 is
Detecting multiple 1-IUN status d of PU, TEST ArJD RES at start of debug monitor program 3
Ii: Execute the T instruction and execute the first instruction within the same memory cycle.
The control circuit 70 and the control circuit 6 of the first Cf'U1 are
Sends true +1& to the control circuit (not shown) of the second CPU2, puts the first CPU1 in the debugging start state, and prohibits the second CPU2 from starting debugging. By doing this, exclusive debugging control of multiple CPUs is performed.

As described above, according to this embodiment,! @1. 1st. By debugging the control circuit of the halted CPU using the block flop 6.7, it is possible to execute the depack monitor program 3 without reducing the execution efficiency of the CPU. Even when the CPU is in a stopped state, exclusive control can be performed with a simple configuration. Furthermore, by providing the debug monitor program counter 12 in addition to the main memory area where the application program is stored, the debug monitor program counter 12 is provided separately from the program counter (not shown), so that the storage area for the application program is narrowed by the debug monitor program. There is no such thing.

As described above, the present invention starts debugging when the second 7-lip-flop inputs the stop state of one of the plurality of central processing units and also inputs the true value from the first 7-lip-flop. By providing a control [l] circuit to prevent unnecessary memory access, etc., it is possible to prevent congestion of the common bus of a multiprocessor system, and this has great industrial value.

[Brief explanation of drawings]

The figure is a block diagram of a multiprocessor debugging device according to an embodiment of the present invention. 1..1.First CPU, 2..-.Second CPU
U. 3...Debug monitor program, 6...
・First 7-lip flop, 711...Second 7-lip flop, 8......Normal 4 product element, 9...
...Control circuit, "2...Debug monitor program counter.

Claims (1)

[Claims] a first 7-lip flop that sends a debug monitor program activation signal to a plurality of central processing units in response to a command from a printer; a second 7-lip flop 70 block, an AND means for inputting the debug monitor program activation signal and the output of the second 7-lip flop, and an output of the AND means and the output from the first 7-lip flop. a control circuit activated by the true/false value of the it; a debug monitor program counter controlled by the control circuit;
The memory device storing the debug monitor program sent to the 's circuit and the metal fittings are leaked, and the second 7 lip +
When the debug monitor program activation signal is inputted when the 170 knob records the stop state of one of the plurality of central processing units, and the true value is supplied to the control circuit. . A multiprocessor depacking device characterized in that said control circuit starts up and starts and executes said debug monitor program in said memory device stored at an address designated by said program counter.