JPS58166832A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To decrease the power consumption, by connecting plural MOS transistors between a potential and an output of one side along with MOS transistors connected opposite to other MOS transistors between a potential and an output of the other side and then applying signals of phases opposite to each other to the gates. CONSTITUTION:MOS transistors TR11 and TR12 are connected in series, and input signals A1 and B1 are applied to the gates of these MOSTRs, respectively. Then the source side of the series circuit is earthed to form a circuit 1. MOSTRT13 and TRT14 are connected in parallel to the drain side of the circuit 1, and the drain side and the source side are connected to a power supply VDD and the drain side of the circuit 1 respectively to form a circuit 2. Then signals A1 and B1 and signals -A1 and -B1 of opposite phases to the signals A1 and B1 are applied to the gates of the TRT13 and TRT14, respectively. The joint of the circuits 1 and 2 is defined as an output terminal OUT1 of an NAND gate. When both signals A1 and B1 are set at 0 or one of these two signals is 0, the OUT1 is cut off from an earth potential and delivers logic 1. Both A1 and B1 are set at 1, the VDD is separated from the OUT1. Thus the OUT1 is set at logic 0. As a result, no DC current flows to the earth from the VDD. This decreases the power consumption.

Description

[Detailed description of the invention] [Basic Q+ 17J Orbital Bonno] This device is an integrated circuit device consisting of channel M08 transistors. [Technical background of the invention] 1.1 High-speed operation and high integration density As a logic circuit device that does not consume much power, a logic integrated circuit device with a single channel M08 transistor structure is widely used.

These single channel M08 transistors (hereinafter referred to as M
A tend gate of a logic integrated circuit based on L) 8T) has conventionally been used as shown in FIG. 1, second factor, or third factor:
In other words, an enhancement type MO is configured, that is, the gate electrodes A and Bt are each supplied with input signals.
8TaJ and the stand are connected in series to form a drive unit YM, one end of which is grounded on the source side and the other end is the drain side, and a depletion type M (J8T/D) for load is connected to the drive unit YM. Apply the power supply potential vDDf through the load MO8T/D and the drive side MO&T-Ml as the output terminal 0υT.
As shown in the above load MO8TI-62, there are cases where an appropriate voltage VGGt' is applied from the outside. First, a low level signal (hereinafter referred to as "0 When input is indicated as "#", "01 signal is input to enhancement type drive MO8T-J or Mos'r-a".
, is turned off, and the output terminal 0υTc outputs the voltage of the power supply Vnn, that is, the "1" signal. On the other hand, input terminal A, and A, C simultaneous 1: When signal "l" is input, M on the driving side
O8T-T and T are turned on at the same time, the ground potential and the output terminal L)LIT are electrically connected, and the output terminal 0LIT is turned on.
o”@@ At this time, when the load MLJ&T-D is !Jll!v and a constant positive voltage is applied to the gate electrode C, the depletion type ML) 8T・D is Since it is always on, a DC current will flow from the 1W source potential Vnn to the ground potential.Furthermore, as shown in Part 2, the load MO8T-
When AiU8TΦEI and E on the drive side become conductive by applying the source potential of J8T, the gate electrode of the load MLI8T-D: @o" signal voltage ( M for a depression type load
O8T@D is in OFF state 1: Cannot be achieved, still useless I:
Direct current flows through Nandgeyat.

Figure 4 C2 shows an example of the configuration of Noah Gate, namely:
Enhancement type driving Mus'r-ba and No. 8, each of which has input signals A' and B' inputted to the gate electrodes, are connected in parallel between the ground potential and the output terminal LOUT,
This parallel connection point, that is, output terminal 0 [JT and power supply potential Vl
) Between 10 and 6; Connect the MO8T and DV for the load which are always in a conductive state. ◎ In such a circuit C2, when either input signal A' or B' reaches the level "1", the signal "
The drive Mυ8T・ supplied with “l” becomes on state,
A wasteful DC current will flow from the power supply potential VDD to the ground potential through the load Mo8T-Dv, which is always in a conductive state.Similarly (:, other logic gate circuits also have an input signal supplied to the gate electrode ≦; A drive unit that connects multiple Mo8Ts in series, in parallel, or in series-parallel to turn on and off according to the Wk principle is constructed between the ground potential and the output terminal, and between this output terminal and the power supply potential VDD - two-tap tension IMMU.
It has a configuration in which a load of 8T is connected. [Problems with the background technology] For this reason, the single channel MO8T4;
In the path, as described above, i: logic level I: Therefore, a wasteful DC current flows through the driving MO8Tt-.

It has the disadvantage of high power consumption.

Due to this drawback, the size of integrated circuits is limited due to problems such as package heat resistance, and the operating speed is also adversely affected, and as the logic scale of integrated circuits continues to expand, some Improvement was needed.

[Purpose of the invention]

The present invention is considered to be similar to the points mentioned above, and is intended to provide an integrated circuit device at' having a single channel MLI8T configuration with reduced power consumption.

[Summary of the invention]

That is, in the integrated circuit device k according to the present invention, in the mmb path having a single channel MO8T configuration, the driving section is configured without using the conventional depletion type MO8T as a load of the driving section that turns on and off based on the logic state of the gate input signal. A signal of completely opposite phase to the input signal to the gate electrode supplied to each of the plurality of M08Ts is used as the input signal to the gate electrode of the plurality of M08Ts (J8T4. - C: Connect so that the on-off operation is all (reverse), and use a circuit configured so that the on-off operation is the opposite, and regardless of the output signal level, from one power supply to the other power supply within this logic circuit. It is designed to prevent direct current from flowing.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to e I! 2 Mo8T11 and 1
An input gate signal is supplied from input terminals A, , B to each gate electrode of m1jd and W! 2 Mo8
T11.1zVii are connected in series, and the source side of this series circuit is grounded to form a sliding door circuit Jv. In addition, the input terminal A is hereinafter referred to as input terminal A.

The gate signals given by B and C are expressed as signals A and B, respectively.The other end of this series-connected pair of ML18Tj, Jj, that is, 1#
The drain C2 of MU8TJJ of Sl is Thl, respectively.
and the second M (J8TJ l.

Signals A and B given to the gates of IJ, and signals A and B in opposite phase; gate electrode g: third and t given;
Connect one parallel circuit of i44's MU8TJ j and J4. Then, make this parallel circuit @2's circuit 2, supply power VDD to this second circuit 2, and connect I82's circuit 2 and the first The connection point with the circuit is connected to the output terminal L) of the Nantes gate.
Take out the signal as JT.Here, as mentioned above, the gate electrode I: of the first ML)8TJJ is connected to the signal A when the signal A is 1. Second MLI8TJJ feeling;
signal B is applied to the third MO8TJ, signal A is applied to the third MO8TJJ, and signal B is applied to the ML18TJ4 of W&4.Now, as the power supply potential VDDv is positive, a voltage signal higher than the threshold voltage of one circuit is applied with positive logic. ', and the ground potential is °O
Assuming that a is the output state for the combination I of each input signal A and B, the following table shows the output state.

For example, when both A and H are C;@0'', both $1 and the second MO8TI J@72 are in the off state.

Conversely, A, Bl: are given a signal level of 112,
Collection 3 and 4th MU8TJ After circuit 2.

The voltage level VDD appears at the output terminal 0LIT.

Similarly, when one of 4tsQ4 and B is 11'' and the other is 01, either of the series-connected ?l and second ML) 8TJ I I 1 j is in the off state, fs3 and fourth M connected in parallel
One of O8TJ3.14 is turned on, and the output terminal L)LIT is disconnected from the ground potential and becomes the power supply potential VDD.
and outputs the logic signal "l". On the other hand, if both S signals A and B are °l#, the serially connected A and the second MO8TJJ*J# are connected together. C
: Turns on and output terminal t)LIT.

is connected to the ground potential Vl)D and vice versa.

3rd and 4th ML) JTI 1 connected in parallel.

14 are all turned off, and the power supply potential VDD and the output terminal 0υT are disconnected.

From power supply potential Vnn to ground potential 6: No significant direct current flows. 1! 6 h l The two wires are an example of a NOR circuit, and the false times A and B are connected to each gate electrode I:
Ta! and No. 6 (rJMt) 8T15 and Ig are connected in parallel to form circuit 1 of this parallel 1 circuit, and its source side is grounded.The other end C2 of this parallel circuit 1, which is not grounded, is connected in parallel. Signals A and B are applied to the gate electrodes of
, and the seventh and eighth MO8T1 F applied to signals A and B*' having opposite phases.

A second circuit 2 having a series circuit configuration of 18 circuits is connected. A power supply voltage VDDt is applied to the drain side of this series circuit, and the sliding door 5 and the sixth ML18TJ 5 are connected.

Take out the signal by using the connection point with the parallel 1 of 16 as the output terminal OUT. In this case, if at least one of the signals A, jtf, and B is @l", 14B and the sixth MLla
At least one of TJ5.7g is turned on,
The ground potential and the output terminal 0 [JT, are connected to each other. On the other hand, the given sound 7 of gate No. 41 of sAI and B,
The series circuit of MO8TI 7 and J a of -8 and -8 is
When at least one of M(JbTIF and ta is turned off, the output terminal becomes 0υT and the electric key position VDD
and set the logic level of the output signal to "0". Also, when both signals A and B are @0'',
With reverse C2 υυT, the ground potential is cut off and the power supply potential VDD
and the output terminal (JU'l') become conductive, and the logic of the output signal becomes '11'.

1. Output a signal of +Bl. As shown in the above two examples.

It is configured as the circuit 1 of the logic circuit vw41 similar to the drive section of a conventional logic circuit, and the circuit 1C of this Ill is configured as the circuit 1C of this Ill circuit; A second circuit 1v is constructed which operates in a complementary manner with the connection relationship reversed.

1) By applying different potentials to the circuit 41 and the second circuit, and making their connection point the output terminal 5.

During normal operation, it is possible to prevent DC current from flowing between the power supplies.
, J is an example of a complex logic circuit in which signals A and B are applied to electrode 6;
J, and MuBTI D vm column connection through, signal C field to gate electrode a: given ML) 8Tz1 to this series circuit - 2 pairs to 1gl1 column; connect, wedge 1ml'
One end of the ungrounded side of this first circuit l, z2-2, the series path 1 of the MO8TJ # and ML)8T20: Correspondingly, the gate electrode is connected to the signal A, and B, given MOaTj 3.
24 parallel circuits and MLJ8T,? JC corresponding C1
A signal from the gate electrode 1 is input to the gate electrode 1;
Supply D.

Then, the connection point 12 between the second circuit t1 & 1, where the signals of AH, Bs, and C are inputted, and the 1st circuit l of the 1st circuit of the 1st circuit, where the signal of Abata aBgmCB is inputted, is connected to the connection point 12 of this complex logic circuit. The output terminal is 0LIT, and the signal is taken out.Such a complex logic circuit (also in the second case, as in the second example of IiJ), the ground potential 4 as seen from the output terminal OUT: the first connected The circuit I and the second circuit 1 connected to the voltage potential VDD (I: the power supply connected to each other).

Output #1iij! ! ! Level l: Therefore, conduction is interrupted in a complementary manner; wasteful DC current does not flow between the power supply potential VDD and the ground potential; g: operates.
In the case of the complex logic circuit of A-B+CJ, 6 has been explained, but it is clear that other logic circuits can be similarly constructed using C; [Effect of the invention] As described above, C: According to this invention i: It is possible to provide an integrated circuit with a single-channel MO8 transistor configuration that has almost no direct current flowing between the power supply potential and the ground potential, and has significantly reduced power consumption.

[Brief explanation of the drawing]

11!1 factor ~ W44- are respectively conventional accumulation roads and installations!
The circuit to be explained, the fifth factor to the seventh eclipse are an embodiment of the present invention C; related integration circuit iii! A detailed example is shown (
b) In the road e l...11!1 road 1, 1...弗2 [g1 road, 7
7-11, JJI-14...MO8 transistor. Attorney-at-Law Patent Attorney Dosu Hiko No. 111 Figure 2 Figure 311 Figure 4

Claims (1)

[Claims] An input signal is given to the gate electrode, and one potential and the output end are connected in series, in parallel, or in series-parallel!
l! 1) 8) Between the range meta and the other potential and the output terminal C; 1 for each of the plurality of transistors; Correspondingly, a reverse phase signal is applied to the gate electrode, and the transistors are connected in series;
8 so that the parallel and series-parallel connection relationships are also correspondingly reversed.
: An integrated (b) schematic arrangement characterized in that it comprises a plurality of M08 transistors and a t-type structure.