JPS5816617B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5816617B2
JPS5816617B2 JP54052325A JP5232579A JPS5816617B2 JP S5816617 B2 JPS5816617 B2 JP S5816617B2 JP 54052325 A JP54052325 A JP 54052325A JP 5232579 A JP5232579 A JP 5232579A JP S5816617 B2 JPS5816617 B2 JP S5816617B2
Authority
JP
Japan
Prior art keywords
solder
pellet
substrate
brazing material
pellets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54052325A
Other languages
Japanese (ja)
Other versions
JPS55145349A (en
Inventor
馬場博之
薄田修
服部宰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP54052325A priority Critical patent/JPS5816617B2/en
Publication of JPS55145349A publication Critical patent/JPS55145349A/en
Publication of JPS5816617B2 publication Critical patent/JPS5816617B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係わり、特にペレット
(半導体素子)をペレットマウント基板に固着するため
の方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for fixing a pellet (semiconductor element) to a pellet mount substrate.

一般に半導体ペレットをペレットマウント基板に固着す
るろう材としては半田が主に用いられている。
Generally, solder is mainly used as a brazing material for fixing semiconductor pellets to a pellet mount substrate.

ところで自動組立においては第1図a、bに示す如く、
上記ろう材の半田リボンを所定の大きさに切断して半田
プリフォーム1を形成し、銀めっき或いはニッケルめつ
き2が施されたペレットマウント基板3に半田プリフォ
ーム1を圧接した後、中性雰囲気中或いは還元性雰囲気
中で溶融し、その溶融半田上に半導体ペレット4を配置
して固着するようにしている。
By the way, in automatic assembly, as shown in Figure 1 a and b,
A solder preform 1 is formed by cutting the solder ribbon of the brazing filler metal into a predetermined size, and after pressure contacting the solder preform 1 to a pellet mount board 3 that has been subjected to silver plating or nickel plating 2, a neutral It is melted in an atmosphere or a reducing atmosphere, and semiconductor pellets 4 are placed and fixed on the molten solder.

ここで半田プリフ、オーム1の大きさは、平面的に見て
ペレット4のそれより大きくしてペレット4と完全な接
着がはかれるようにしている。
Here, the size of the solder pref Ohm 1 is larger than that of the pellet 4 in plan view so that it can be completely bonded to the pellet 4.

しかるに、基板4に施された銀めつき2は容易に硫化し
、半田プリフォーム1を圧接した後これを溶融する際、
半田とのなじみをわるくして半田が一部に片寄ってしま
うという現象が生じる。
However, the silver plating 2 applied to the substrate 4 easily sulfurizes, and when melting the solder preform 1 after pressure-welding it,
A phenomenon occurs in which the solder becomes unevenly distributed due to poor compatibility with the solder.

なお第1図Cにおいて1、は半田プリフォーム1がもと
もと配置されていた個所、12はこの個所の一部に片寄
ってしまった半田、41はペレット4のマウント領域を
示す。
In FIG. 1C, reference numeral 1 indicates a location where the solder preform 1 was originally placed, reference numeral 12 indicates the solder that has shifted to a part of this location, and reference numeral 41 indicates the mounting area of the pellet 4.

このように半田の片寄りが生じると、ペレット4の直下
にほとんど半田が存在しないことになり、従ってペレッ
ト4と基板3との接着は不充分となり、熱抵抗が増大し
たり、熱疲労試験や熱衝撃試験等の信頼性試験で熱抵抗
が大きく変動したり、熱歪が不均一に生じてペレット4
にクラックが生じたりする等の問題がある。
If the solder is unevenly distributed in this way, there will be almost no solder directly under the pellet 4, and therefore the adhesion between the pellet 4 and the board 3 will be insufficient, leading to an increase in thermal resistance and failure in thermal fatigue tests. During reliability tests such as thermal shock tests, thermal resistance fluctuates greatly or thermal distortion occurs unevenly, resulting in pellets 4
There are problems such as cracks occurring.

一方、ニッケルめつき2が施された基板3では、ニッケ
ルめつき2の表面が非常に酸化されやすいこともあり、
半田とのなじみが極端に悪く、略100係近く半田の片
寄りがみられ、上記のような信頼性試験で不良が発生す
ることは勿論、組立工程においてペレット4を基板3に
固着することも不可能な状態になるという致命的な欠点
がある。
On the other hand, in the case of the substrate 3 with nickel plating 2, the surface of the nickel plating 2 may be very easily oxidized.
The compatibility with the solder is extremely poor, and the solder is unevenly distributed by approximately 100 mm, which not only causes failures in the reliability test described above, but also causes the pellet 4 to stick to the board 3 during the assembly process. It has the fatal drawback of being in an impossible state.

本発明者等は上記のような問題点を改善するため種々検
討を行なった結果、第2図a〜dに示す方法を見出した
The present inventors conducted various studies to improve the above-mentioned problems, and as a result, they discovered the methods shown in FIGS. 2a to 2d.

即ちニッケル或いは銀めっき層2を有した基体3上にろ
う材(半田)を介してペレット4をマウントするに当り
、前記半田13として、平面的に見てペレット4の面積
よシ小さな面積を有したものを用い、かつこの半田13
をペレット4下のペレットマウント領域内に配置するこ
とにより、溶融半田がいずれに片寄っても、ペレット4
の直下には常に半田13が存在し、従ってペレット4へ
適当な荷重と振動を与えれば、基板11の下面全面に略
半田13が行きわたり、良好なマウントが行なえる。
That is, when mounting the pellet 4 on the substrate 3 having the nickel or silver plating layer 2 via a brazing material (solder), the solder 13 has an area smaller than the area of the pellet 4 in plan view. Use this solder 13
By placing the molten solder in the pellet mount area under the pellet 4, the pellet 4
There is always solder 13 directly under the substrate 11. Therefore, if an appropriate load and vibration are applied to the pellet 4, the solder 13 will spread substantially over the entire lower surface of the substrate 11, and a good mounting can be achieved.

しかしペレット4の大きさが4,0關口を越えるような
大きなものについては、半田なじみが不均一でまた半田
13に厚みの大のものを用いる等の関係上、半田1.の
飛び出しが起こり、このため半田14の厚さが一定せず
、従って熱抵抗のばらつき或いは信頼性試験などで不良
品が発生するおそれがある。
However, if the size of the pellet 4 exceeds 4.0 mm, the solder 1. As a result, the thickness of the solder 14 is not constant, which may lead to variations in thermal resistance or defective products during reliability tests.

本発明者等はこのような現象を調べる過程で、上記飛び
出し半田15が生じる原因は、溶融半田にペレットを入
れる際、ペレット4が溶融半田を押し拡げる速さが早す
ぎるため、めつき2となじみ切らずに半田が飛び出して
しまうことを見出した。
In the process of investigating such a phenomenon, the present inventors discovered that the cause of the above-mentioned popping out solder 15 is that when the pellets are put into the molten solder, the speed at which the pellet 4 pushes the molten solder and spreads it is too fast, resulting in a problem with plating 2. I discovered that the solder would jump out without being completely absorbed.

これを防止するには、ペレット4を半田13に配置する
速さを落せばよいが、すると生産性が大幅に悪化してし
まう。
In order to prevent this, the speed at which the pellets 4 are placed on the solder 13 may be reduced, but this will significantly reduce productivity.

本発明は上記実情に鑑みてなされたもので、ろら材特に
半田とのなじみの悪いニッケル或いは銀めっき等が施さ
れた基板へのペレット固着に当り、使用するろう材をそ
の幅がペレットのそれより狭くなるように形成すると共
に、ろう材の一部をペレットマウント領域よりはみ出す
ように配置することにより、前記従来の問題点を掃し得
る半導体装置の製造方法を提供しようとするものである
The present invention has been made in view of the above-mentioned circumstances, and is intended for fixing pellets to substrates coated with nickel or silver plating, etc., which have poor compatibility with solder. The object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the above-mentioned conventional problems by forming the brazing material to be narrower than that and by arranging a part of the brazing material to protrude from the pellet mount area. .

以下第3図を参照して本発明の一実施例を説明する。An embodiment of the present invention will be described below with reference to FIG.

なお本実施例は前記第1図または第2図の場合と対応す
る場合の例であるから、対応する個所には同一符号を付
して説明を省略し、特徴とす。
Note that this embodiment is an example corresponding to the case of FIG. 1 or FIG. 2, so corresponding parts are given the same reference numerals and explanations are omitted, and are characterized.

る点のみを説明する。I will only explain the points.

即ち本実施例では、第3図a、bに示す如く半田16と
して、平面的に見た幅がペレット4の幅よシ狭いものを
用い、かつこの半田4の一部をペレット4下のペレット
マウント領域よりはみ出すように配置し、圧接するもの
・である。
That is, in this embodiment, as shown in FIGS. 3a and 3b, solder 16 whose width in plan view is narrower than the width of the pellet 4 is used, and a part of this solder 4 is attached to the pellet below the pellet 4. It is placed so that it protrudes from the mounting area and is pressed against it.

このようにすれば、溶融状態の半田16上にペレット4
が配置された時に押し拡げられた半田は、最初からはみ
出した部分17に集中する。
In this way, the pellet 4 can be placed on the molten solder 16.
The solder that is pushed and spread when placed is concentrated on the part 17 that has protruded from the beginning.

従って第2図endの如き半田のとび出しは防止でき、
ペレット配置後に行なう摺動により、半田16はめつき
2となじむと共に、はみ出し部17の半田はペレットマ
ウント領域側に戻り、第3図Cの如く半田14の厚みが
均一でかつ確実なペレット固着が可能となり、信頼性に
富んだ製品が得られるものである。
Therefore, it is possible to prevent the solder from popping out as shown in the end of Figure 2.
By sliding after placing the pellet, the solder 16 blends in with the plating 2, and the solder in the protruding portion 17 returns to the pellet mount area, making it possible to ensure that the thickness of the solder 14 is uniform and the pellet is firmly fixed as shown in Figure 3C. Therefore, a highly reliable product can be obtained.

またペレットマウント後の半田の厚みが均一でないと、
放熱状態が均一にならないため、ペレットとペレットマ
ウント基板との間の熱抵抗のばらつきとなるが、本発明
の方法で行なったものは上記熱抵抗のばらつきが非常に
小さく、安定した。
Also, if the thickness of the solder after pellet mounting is not uniform,
Since the heat dissipation condition is not uniform, there will be variations in thermal resistance between the pellet and the pellet mount substrate, but when the method of the present invention is used, the variation in the thermal resistance is very small and stable.

第6図に熱抵抗値のデータを示す。Figure 6 shows data on thermal resistance values.

第6図aはNiめっきされた基板上にペレットより大き
な半田プリフォームを圧接したのちマウントしたもの(
第1図aの方法)、第6図すは同様の基板にペレットよ
り小さな半田プリフォームを介してマウントしたもの(
第2図aの方法)、第6図Cは同様の基板に本発明の第
3図すの方法でマウントしたものの結果である。
Figure 6a shows a solder preform larger than a pellet pressed onto a Ni-plated substrate and then mounted (
The method shown in Figure 1a), and the method shown in Figure 6 is a method mounted on a similar substrate via a solder preform smaller than the pellet (
2(a)) and FIG. 6(C) are the results of mounting on a similar substrate by the method of FIG. 3(a) of the present invention.

ところで第6図a、bのように熱抵抗のばらつきが犬で
あると、熱抵抗が犬のときは、半田厚が厚すぎる等の原
因で不良である。
By the way, if the variation in thermal resistance is small as shown in FIGS. 6a and 6b, if the thermal resistance is small, it is defective due to reasons such as too thick solder.

一方熱抵抗が小のときは、半田の片寄シや半田のとび出
し等のため半田厚が非常に薄すぎる構造となり、ペレッ
ト及びペレットマウント基板(通常鋼)の間の熱膨張係
数が大幅に異なるのを吸収する緩衝層としての半田が薄
すぎる結果となり、ペレットがはがれたり、こわれたり
する。
On the other hand, when the thermal resistance is small, the solder thickness is too thin due to uneven solder and solder protrusion, and the thermal expansion coefficient between the pellet and the pellet mount board (usually steel) differs significantly. The result is that the solder is too thin as a buffer layer to absorb the heat and the pellets peel off or break.

ちなみにイニシャル(信頼性試験前)熱抵抗の不良率は
5〜10チ発生し、信頼性試験後では5〜20チの不良
が発生した。
Incidentally, the initial (before reliability test) thermal resistance defect rate was 5 to 10 inches, and after the reliability test, 5 to 20 inches were defective.

これに対し本発明では半田厚が所定にでき第6図Cのよ
うに、イニシャルの熱抵抗のばらつきも非常に少なく、
不良率はイニシャル、信頼性試験後ともほとんど皆無に
することができた。
On the other hand, in the present invention, the solder thickness can be set to a predetermined value, and as shown in FIG. 6C, there is very little variation in the initial thermal resistance.
The defective rate was almost completely eliminated both initially and after the reliability test.

また、本発明においては、溶融したろう材の上に、ペレ
ットを振動させる部材を用いて振動させ充分にろう材を
広げて接着するので、ペレットマウント位置のばらつき
が非常に少なく、後工程でのボンディング等が容易にな
り、自動化しやすい利点があるものである。
In addition, in the present invention, a member that vibrates pellets is used to vibrate the pellets on top of the molten brazing material, and the brazing material is sufficiently spread and bonded, so there is very little variation in the pellet mounting position, and it is easy to use in the subsequent process. This has the advantage that bonding etc. are easy and can be easily automated.

なお上記実施例では基板3の最上めっき層としてニッケ
ルを用いたが、銀を用いた場合も、半田とのなじみが悪
い点はニッケルの場合と同様であるから、第2図a〜d
と同様の方法を実施することにより、同様の効果が得ら
れることは明らかである。
In the above embodiment, nickel was used as the top plating layer of the substrate 3, but even when silver is used, it has the same poor compatibility with solder as in the case of nickel.
It is clear that similar effects can be obtained by implementing a method similar to the above.

また実施例では表面が変質しやすいめっき層として、ニ
ッケルまたは銀を用いたが、めっき層の材質はこれのみ
に限られない。
Further, in the examples, nickel or silver was used as the plating layer whose surface is likely to change in quality, but the material of the plating layer is not limited to these.

またろう材としての半田は、第4図の如くペレット4の
両側にはみ出す半田1□1を用いたり、第5図の如く対
角線状にはみ出す半田12□を用いてもよい等、種々の
応用が可能である。
Furthermore, solder as a brazing material can be used in various applications, such as using solder 1□1 that protrudes from both sides of the pellet 4 as shown in Fig. 4, or using solder 12□ that protrudes diagonally as shown in Fig. 5. It is possible.

以上説明した如く本発明によれば、ペレットマウント時
のろう材の大幅な片寄り及び飛び出しが防止できるため
、ろう材になじみのわるいめっき層を用いた場合におい
ても、ペレットを基板に確実にマウントでき、製品の信
頼性の向上がはかれるものである。
As explained above, according to the present invention, it is possible to prevent the brazing filler metal from shifting significantly and popping out when mounting the pellets, so even when a plating layer that is not compatible with the brazing filler metal is used, the pellets can be reliably mounted on the substrate. This will improve the reliability of the product.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜Cは従来装置の製造工程説明図、第2図a〜
dは同工程の改良例、第3図a〜Cは本発明の一実施例
の工程説明図、第4図、第5図は本発明の他の実施例を
説明するためのペレットマウント部の平面図、第6図a
ないしCは本発明の効果を示すための熱抵抗値の分布図
である。 16・・・・・・半田、2・・・・・・めっき層、3・
・・・・・導電性基板、4・・・・・・ペレット。
Figures 1 a to C are explanatory diagrams of the manufacturing process of the conventional device, and Figures 2 a to
d is an improved example of the same process, Figures 3a to 3C are process explanatory diagrams of one embodiment of the present invention, and Figures 4 and 5 are illustrations of pellet mount parts for explaining other embodiments of the present invention. Plan view, Figure 6a
1 to 2 are distribution diagrams of thermal resistance values to show the effects of the present invention. 16...Solder, 2...Plating layer, 3.
... Conductive substrate, 4... Pellets.

Claims (1)

【特許請求の範囲】[Claims] 1 ろう材とのなじみが悪いめっき層を表面に有する基
体上に、平面的に見た幅が半導体ペレットの幅よりも狭
いろう材をペレットマウント予定領域よりはみ出すよう
に配置する工程と、前記ろう材を溶融する工程と、前記
ろう材に半導体ペレットを接触させ該ペレットを振動さ
せることにより前記ペレットマウント予定領域に前記ペ
レットを固着する工程とを具備したことを特徴とする半
導体装置の製造方法。
1. A step of arranging a brazing material whose width in plan view is narrower than the width of the semiconductor pellet on a substrate having a plating layer on its surface that is poorly compatible with the brazing material so as to protrude from the area where the pellet is to be mounted, and A method for manufacturing a semiconductor device, comprising the steps of: melting the brazing material; and fixing the pellet in the area where the pellet is to be mounted by bringing a semiconductor pellet into contact with the brazing material and vibrating the pellet.
JP54052325A 1979-04-27 1979-04-27 Manufacturing method of semiconductor device Expired JPS5816617B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54052325A JPS5816617B2 (en) 1979-04-27 1979-04-27 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54052325A JPS5816617B2 (en) 1979-04-27 1979-04-27 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS55145349A JPS55145349A (en) 1980-11-12
JPS5816617B2 true JPS5816617B2 (en) 1983-04-01

Family

ID=12911632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54052325A Expired JPS5816617B2 (en) 1979-04-27 1979-04-27 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5816617B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0217713U (en) * 1988-07-19 1990-02-06

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60210844A (en) * 1984-04-05 1985-10-23 Sanken Electric Co Ltd Method of soldering
JP2006114649A (en) * 2004-10-14 2006-04-27 Fuji Electric Device Technology Co Ltd Method and apparatus for manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4949577A (en) * 1972-09-14 1974-05-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4949577A (en) * 1972-09-14 1974-05-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0217713U (en) * 1988-07-19 1990-02-06

Also Published As

Publication number Publication date
JPS55145349A (en) 1980-11-12

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