JPS5816616B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5816616B2
JPS5816616B2 JP53149287A JP14928778A JPS5816616B2 JP S5816616 B2 JPS5816616 B2 JP S5816616B2 JP 53149287 A JP53149287 A JP 53149287A JP 14928778 A JP14928778 A JP 14928778A JP S5816616 B2 JPS5816616 B2 JP S5816616B2
Authority
JP
Japan
Prior art keywords
thermal expansion
coefficient
semiconductor substrate
electrode
synthetic resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53149287A
Other languages
Japanese (ja)
Other versions
JPS5575249A (en
Inventor
国谷啓一
守田啓一
鶴岡征男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53149287A priority Critical patent/JPS5816616B2/en
Priority to DE7979302729T priority patent/DE2966314D1/en
Priority to EP19790302729 priority patent/EP0012019B1/en
Publication of JPS5575249A publication Critical patent/JPS5575249A/en
Publication of JPS5816616B2 publication Critical patent/JPS5816616B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • H01L23/4924Bases or plates or solder therefor characterised by the materials
    • H01L23/4928Bases or plates or solder therefor characterised by the materials the materials containing carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

A supporting electrode (16,18) is mounted on at least one surface of a semiconductor substrate (11). The sides of the substrate (11) and the electrode are covered by epoxy resin (43). In order to avoid problems arising from the different thermal expansion coefficients of the various materials, the electrode is formed of a copper-carbon fiber composition metal in which carbon fibers are embedded in a spiral and lie parallel to the major surface of the substrate, so that the electrode exhibits anisotropic thermal expansion properties. Its coefficient of expansion parallel to the major surface of the substrate is lower than its coefficient in the direction perpendicular to this surface, since the expansion coefficient of the substrate (e.g. silicon) is lower than that of the resin (43).

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に合成樹脂にて外被を施
す半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an outer covering made of synthetic resin.

半導体装置では、半導体素子を外部雰囲気の影響及び外
力から保護するため、及び沿面距離を長く確保して高い
絶縁電圧を得るために、半導体素子を金属−セラミック
複合ケースに収納したり、合成樹脂或いはガラス等の絶
縁性物質で包囲外被したりしている。
In semiconductor devices, semiconductor devices are housed in metal-ceramic composite cases, or in synthetic resin or synthetic resin cases, in order to protect semiconductor devices from the influence of the external atmosphere and external forces, and to ensure long creepage distances and obtain high insulation voltage. It is surrounded by an insulating material such as glass.

その中でも合成樹脂で外被する方法は比較的簡単にでき
るため、低価格の半導体装置に向いている。
Among these methods, the method of enveloping with synthetic resin is relatively simple and is suitable for low-cost semiconductor devices.

と如わけ小面積の半導体素子の両面にS字形のリード線
を半田付けし、半導体素子とリード線を合成樹脂で包囲
した装置は安価な装置の代表例である。
A device in which S-shaped lead wires are soldered to both sides of a small-area semiconductor element and the semiconductor element and lead wires are surrounded by synthetic resin is a typical example of an inexpensive device.

しかしながら、電流容量の大きい半導体装置を合成樹脂
で包囲外被した装置は工業ベースで実現していない。
However, a device in which a semiconductor device with a large current capacity is surrounded and coated with synthetic resin has not been realized on an industrial basis.

その理由のひとつは、半導体基板、電極材料および合成
樹脂の熱膨張特性がうまく噛み合わないことにある。
One reason for this is that the thermal expansion characteristics of the semiconductor substrate, electrode material, and synthetic resin do not mesh well.

大面積牛導体素子に対する電極片は、熱膨張量の差異が
無視できないことから、熱膨張係数が半導体基板の熱膨
張係数に合致していることを必要とする。
Since the difference in the amount of thermal expansion of an electrode piece for a large-area conductor element cannot be ignored, the coefficient of thermal expansion must match that of the semiconductor substrate.

そこで熱膨張係数が半導体基板に近似した材料、例えば
シリコンに対してならタングステンを用いることになる
Therefore, for example, tungsten is used for silicon, which has a coefficient of thermal expansion similar to that of the semiconductor substrate.

合成樹脂の熱膨張係数はタングステンに比べて約10倍
大きいので、シリコン−タングステン組み立て物を合成
樹脂で包囲すると、合成樹脂の硬化加熱冷却後ではシリ
コン−タングステン組み立て物には合成樹脂で締めつけ
られるような力が働く。
The coefficient of thermal expansion of synthetic resin is approximately 10 times larger than that of tungsten, so if a silicone-tungsten assembly is surrounded by synthetic resin, the silicone-tungsten assembly will be able to be tightened with the synthetic resin after the synthetic resin has hardened, heated, and cooled. A force is at work.

この場合、タングステンと合成樹脂の間に隙間はできな
いが、シリコン−タングステン複合物の軸方向で見るな
ら、タングステンと合成樹脂の熱膨張量の差異により、
タングステンと合成樹脂の間に滑りがおき、両者の間の
密着性が妨げられる。
In this case, there is no gap between the tungsten and the synthetic resin, but when viewed in the axial direction of the silicone-tungsten composite, due to the difference in thermal expansion between the tungsten and the synthetic resin,
Slippage occurs between the tungsten and the synthetic resin, impeding the adhesion between them.

本発明の目的は、上記の不都合を解決して合成樹脂で包
囲外被した半導体装置、特に大型の半導体装置を提供す
るにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned disadvantages and provide a semiconductor device, particularly a large-sized semiconductor device, which is covered with a synthetic resin.

本発明による半導体装置の特徴とするところは、電極片
の熱膨張係数を、半導体基板と接着する面に平行な方向
では半導体基板と合致させ、上記と垂直な方向では合成
樹脂と合致させた点にあり、斯様な性質の電極片は銅−
炭素繊維複合材で製造することができる。
The semiconductor device according to the present invention is characterized in that the coefficient of thermal expansion of the electrode piece is made to match that of the semiconductor substrate in the direction parallel to the surface to be bonded to the semiconductor substrate, and to match that of the synthetic resin in the direction perpendicular to the above. The electrode piece with such properties is made of copper.
Can be manufactured from carbon fiber composite material.

以下、図面を参照し、実施例により本発明の詳細な説明
する。
Hereinafter, the present invention will be described in detail by way of examples with reference to the drawings.

第1図は、半導体基板と電極片の組み立て前の状況を説
明する分解断面図である。
FIG. 1 is an exploded sectional view illustrating the state of the semiconductor substrate and the electrode piece before they are assembled.

1はシリコンで、周辺部に整流接合端を内壁面に現わす
モート2を有し、前記モート2の中にはパッシベーショ
ン用ガラス3を焼結しである。
Reference numeral 1 is made of silicon and has a moat 2 at its periphery with a rectifying joint end appearing on the inner wall surface, and a passivation glass 3 is sintered inside the moat 2.

4と5はオーミックコンタクトで、本例ではニッケル膜
である。
4 and 5 are ohmic contacts, which in this example are nickel films.

6は上部電極片、8は下部電極片で、夫々銀メッキ7及
び9を有し、後述するような熱膨張異方性をもった材料
で構成される。
6 is an upper electrode piece, and 8 is a lower electrode piece, which has silver plating 7 and 9, respectively, and is made of a material having thermal expansion anisotropy as described later.

上部電極片6及び下部電極片8の矢印B方向−すなわち
シリコン1の面方向での熱膨張係数は4X10 ’/
’Cであり、矢印A方向での熱膨張係数は18X10−
6/℃である。
The coefficient of thermal expansion of the upper electrode piece 6 and the lower electrode piece 8 in the direction of arrow B - that is, in the plane direction of the silicon 1 is 4X10'/
'C, and the coefficient of thermal expansion in the direction of arrow A is 18X10-
6/℃.

このような異方性を有する電極片の材料としては、第2
図に示すような銅−炭素繊維複合材が適している。
As the material of the electrode piece having such anisotropy, the second
A copper-carbon fiber composite material as shown in the figure is suitable.

これは直径数ミクロンの黒鉛繊維を同心円状または中央
にうず巻中心を持つうす巻き状に配置し、黒鉛繊維間は
銅で充填した構造で、本例では黒鉛と銅の容量比は30
(黒鉛): 70(銅)である。
This is a structure in which graphite fibers with a diameter of several microns are arranged concentrically or in a thinly wound shape with a spiral center in the center, and the spaces between the graphite fibers are filled with copper. In this example, the capacity ratio of graphite and copper is 30.
(Graphite): 70 (copper).

その製造は、銅メッキを施した黒鉛繊維を巻いた巻糸状
物に所要量の銅粉を含浸させ、ホットプレス装置で、熱
間加圧して固め、その後所要形状に機械加工して行なう
ことができる。
It can be manufactured by impregnating a spool of copper-plated graphite fiber with the required amount of copper powder, hardening it by hot pressing in a hot press machine, and then machining it into the desired shape. can.

かかる構造の電極片は同心円状またはうす巻き状に配置
した熱膨張係数の小さな黒鉛繊維の束縛のために主面と
平行な方向(B方向)の熱膨張係数は小さく、黒鉛繊維
の束縛の少ない厚さ方向(A方向)の熱膨張係数はB方
向より大きくなる。
Electrode pieces with such a structure have a small coefficient of thermal expansion in the direction parallel to the main surface (direction B) due to the binding of graphite fibers with a small coefficient of thermal expansion arranged in concentric circles or thinly wound shapes, and the binding of the graphite fibers is small. The coefficient of thermal expansion in the thickness direction (A direction) is larger than that in the B direction.

なお、前記炭素繊維の代シにタングステンやアンバーな
どの繊維を用いることもできる。
Note that fibers such as tungsten and amber can also be used in place of the carbon fibers.

第1図に戻り、10及び11は半田である。Returning to FIG. 1, 10 and 11 are solder.

第1図に示す諸材料を上下の順序を変えずに積み重ね、
加熱することによりシリコン1を電極片6及び8に接着
挾持した半組立品ができる。
Stack the materials shown in Figure 1 without changing the order of the top and bottom,
By heating, a semi-assembly product in which the silicon 1 is adhesively sandwiched between the electrode pieces 6 and 8 is produced.

第3図は前述のようにして作られた半組立品の周囲に樹
脂を包囲外被した構造を示す断面図である。
FIG. 3 is a sectional view showing a structure in which a resin is encased around the subassembly made as described above.

12はシリコン1のモート2に焼結したガラス3の上に
焼き付けたシリコーンゴムである。
12 is a silicone rubber baked onto a glass 3 sintered to a moat 2 of silicon 1.

13はエポキシ樹脂で、鋳型(図示せず)を用いて注入
成型したもので、180℃の加熱を施して硬化しである
Reference numeral 13 is an epoxy resin, which is injection molded using a mold (not shown), and is cured by heating at 180°C.

そして、このエポキシ樹脂の熱膨張係数は25 X 1
0−6/’Cである。
The coefficient of thermal expansion of this epoxy resin is 25 x 1
It is 0-6/'C.

シリコーンゴム12はクッション材硬化したエポキシ樹
脂13がガラス3に直接触れてガラス3を損傷しないよ
うにするためのバッファの働きをする。
The silicone rubber 12 functions as a buffer to prevent the hardened epoxy resin 13 of the cushioning material from directly touching the glass 3 and damaging the glass 3.

尚、半導体基板にガラスを焼結していなくとも、半導体
の周辺の電極を接着されない部分にシリコーンゴムの被
覆を施しておけば、シリコンゴムがクッションの役目を
果すことになるので、半導体基板材料とエポキシ樹脂の
熱膨張係数差による引張力を緩和することができるとい
う効果がある。
Even if glass is not sintered on the semiconductor substrate, if the parts around the semiconductor where the electrodes are not bonded are coated with silicone rubber, the silicone rubber will act as a cushion, so the semiconductor substrate material This has the effect of being able to alleviate the tensile force caused by the difference in thermal expansion coefficient between the epoxy resin and the epoxy resin.

かかる構造装置では、半導体基板と電極片の主面方向で
の熱膨張係数が近似なため、半導体基板と電極片の熱膨
張量の差異による半導体基板の損傷、ガラスの損傷、そ
して半導体基板−電極片間接着材層の熱疲労が起こらな
い。
In such a structural device, since the thermal expansion coefficients of the semiconductor substrate and the electrode piece in the main surface direction are similar, damage to the semiconductor substrate, damage to the glass, and damage to the semiconductor substrate and the electrode due to the difference in the amount of thermal expansion between the semiconductor substrate and the electrode piece can occur. Thermal fatigue of the adhesive layer between the pieces does not occur.

また同じ方向で電極片と外被合成樹脂の間の熱膨張係数
に注目すると、電極片側面は常に合成樹脂13によって
径方向に締めつけられているため、いわゆる焼きばめの
状態となり、電極片側面と合成樹脂間の密着性は非常に
良好になる。
Also, if we pay attention to the coefficient of thermal expansion between the electrode piece and the outer synthetic resin in the same direction, one side of the electrode is always tightened in the radial direction by the synthetic resin 13, resulting in a so-called shrink fit state, and one side of the electrode The adhesion between the resin and the synthetic resin is very good.

次にシリコンの厚さ方向で電極片と合成樹脂の熱膨張係
数に注目すると、両者の熱膨張係数が近似であるため、
両者の間に熱膨張量の差異が殆んど無<、シたがって滑
りが起らず、上記綿めつけによる密着性と相まって、電
極片と外被合成樹脂の密着が良好に得られる。
Next, if we look at the thermal expansion coefficients of the electrode piece and the synthetic resin in the thickness direction of the silicone, we can see that the thermal expansion coefficients of both are approximate.
There is almost no difference in the amount of thermal expansion between the two, so no slipping occurs, and in combination with the adhesion achieved by the cotton plating, good adhesion between the electrode piece and the synthetic resin jacket can be achieved.

よって、これら境界を経て外周から湿気などが浸入する
のを防止することができる。
Therefore, it is possible to prevent moisture from entering from the outer periphery through these boundaries.

第4図は本発明をいわゆるボタン型ダイオードに適用し
た他の実施例である。
FIG. 4 shows another embodiment in which the present invention is applied to a so-called button type diode.

21はシリコン半導体基板であり、半田30及び31を
介して上部電極片26及び下部電極片28で接着挾持さ
れている。
A silicon semiconductor substrate 21 is adhesively sandwiched between an upper electrode piece 26 and a lower electrode piece 28 via solders 30 and 31.

32はシリコン半導体基板21の端部に付けたシリコー
ンゴムである。
32 is silicone rubber attached to the edge of the silicon semiconductor substrate 21.

33は上部電極片26から下部電極片28に亘って側面
を包囲外被するエポキシ樹脂である。
Reference numeral 33 denotes an epoxy resin that surrounds and covers the side surfaces of the upper electrode piece 26 and the lower electrode piece 28.

本例における、電極片及びエポキシの熱膨張係数と、電
極片の熱膨張係数のA方向とB方向の異方性は先の実施
例と同一である。
In this example, the thermal expansion coefficients of the electrode piece and epoxy, and the anisotropy of the thermal expansion coefficient of the electrode piece in the A direction and the B direction are the same as in the previous example.

そして、同じように電極片と外被合成樹脂の密着が良好
に得られるので、境界を経て外周から湿気などが浸入す
るのを無くすることができる。
In the same way, good adhesion between the electrode piece and the outer covering synthetic resin can be obtained, so that it is possible to prevent moisture from entering from the outer periphery through the boundary.

尚、以上においては2端子半導体装置を実施例として、
掲げたが、本発明はこれに限るものではなく、サイリス
クの如き3端子装置に対しても、何ら制限することもな
く実施できることは勿論である。
In addition, in the above, a two-terminal semiconductor device is taken as an example,
However, the present invention is not limited to this, and it goes without saying that the present invention can be implemented without any limitation on a three-terminal device such as Cyrisk.

以上から明らかなように、本発明によれば、半導体基板
、電極片、合成樹脂の熱膨張係数が機能的に良く合って
いるため特に大型の、合成樹脂で包囲外被した半導体装
置が得られるのである。
As is clear from the above, according to the present invention, the coefficients of thermal expansion of the semiconductor substrate, the electrode piece, and the synthetic resin are functionally well matched, so that a particularly large semiconductor device surrounded by a synthetic resin can be obtained. It is.

本発明に用いられる銅と炭素、タングステンまたは/お
よびアンバー繊維などの複合材よりなる電極片の面方向
および厚み方向の熱膨張係数はその配合比と繊維の形状
、寸法、混合の仕方などによって、ある範囲内で適当に
選択することができる。
The coefficient of thermal expansion in the plane direction and the thickness direction of the electrode piece made of a composite material such as copper and carbon, tungsten or/and amber fiber used in the present invention depends on the blending ratio, the shape and size of the fibers, the method of mixing, etc. It can be selected appropriately within a certain range.

面方向の熱膨張係数はシリコンのそれ(3,5X10−
6/’C)と適合するように3.5〜5X10−7’C
の範囲が好ましい。
The coefficient of thermal expansion in the plane direction is that of silicon (3.5X10-
6/'C) to match 3.5~5X10-7'C
A range of is preferred.

この場合、これ以下にしようとすると、銅に対する炭素
等の比率が大きくなり、熱伝導特性が劣化するので実用
的でなくなる。
In this case, if it is attempted to be lower than this, the ratio of carbon, etc. to copper will increase, and the thermal conductivity will deteriorate, making it impractical.

厚み方向の複合材の熱膨張係数は、電極片側壁と会合樹
脂(膨張係数25 X 10”−6/’C) (!:の
境界面における両者のずれ量が炭素等の繊維(通常は半
径約5μm程度)の1本分以内に納めるのが望ましいの
で、20〜30 X 10−6/’Cの範囲にあるのが
望ましい。
The coefficient of thermal expansion of the composite material in the thickness direction is that of the one side wall of the electrode and the associated resin (coefficient of expansion 25 It is desirable that the temperature be within the range of 20 to 30 x 10-6/'C.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の1実施例の分解断面図、第2図は第
1図における電極片の斜視図、第3図は本発明の1実施
例の断面図、第4図は本発明の他の実施例の断面図であ
る。 1.21・・・・・・半導体基板、6,8,26.28
・・・・・・電極片、13.33・・・・・・合成樹脂
、12.32・・・・・・クッション材。
FIG. 1 is an exploded sectional view of one embodiment of the present invention, FIG. 2 is a perspective view of the electrode piece in FIG. 1, FIG. 3 is a sectional view of one embodiment of the present invention, and FIG. FIG. 3 is a sectional view of another embodiment of the invention. 1.21... Semiconductor substrate, 6, 8, 26.28
... Electrode piece, 13.33 ... Synthetic resin, 12.32 ... Cushion material.

Claims (1)

【特許請求の範囲】 1 #−導体基板の両生面に一対の電極片を接着し、半
導体基板及it極片の側面の少なくとも半導体基板に近
い側を鍔状に合成樹脂で囲繞した半導体装置において、
電極片の熱膨張係数が半導体基板との接着面と平行な方
向では半導体基板の熱膨張係数と等しいか略々等しく、
上記方向と垂直方向では該合成樹脂の熱膨張係数と等し
いか略々等しいことを特徴とする半導体装置。 2 電極片が、炭素、タングステンおよびアンバー繊維
のうちの少なくとも1つと銅との複合材であることを特
徴とする第1項記載の半導体装置。 3 半導体基板の主面周辺部の、電極片で覆われない部
分の少なくとも1部にクッション材を配置したことを特
徴とする第1または第2項記載の半導体装置。
[Scope of Claims] 1. In a semiconductor device in which a pair of electrode pieces are bonded to the bidirectional surfaces of a conductor substrate, and at least the sides of the semiconductor substrate and the IT electrode pieces, at least the side closer to the semiconductor substrate, are surrounded by a brim-like synthetic resin. ,
The coefficient of thermal expansion of the electrode piece is equal to or approximately equal to the coefficient of thermal expansion of the semiconductor substrate in the direction parallel to the adhesive surface with the semiconductor substrate;
A semiconductor device characterized in that the coefficient of thermal expansion in a direction perpendicular to the above direction is equal to or substantially equal to that of the synthetic resin. 2. The semiconductor device according to item 1, wherein the electrode piece is a composite material of copper and at least one of carbon, tungsten, and amber fibers. 3. The semiconductor device according to item 1 or 2, characterized in that a cushioning material is disposed in at least a portion of the peripheral portion of the main surface of the semiconductor substrate that is not covered with the electrode piece.
JP53149287A 1978-12-01 1978-12-01 semiconductor equipment Expired JPS5816616B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP53149287A JPS5816616B2 (en) 1978-12-01 1978-12-01 semiconductor equipment
DE7979302729T DE2966314D1 (en) 1978-12-01 1979-11-29 An electrode for a semiconductor device and method of making such an electrode
EP19790302729 EP0012019B1 (en) 1978-12-01 1979-11-29 An electrode for a semiconductor device and method of making such an electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53149287A JPS5816616B2 (en) 1978-12-01 1978-12-01 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5575249A JPS5575249A (en) 1980-06-06
JPS5816616B2 true JPS5816616B2 (en) 1983-04-01

Family

ID=15471885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53149287A Expired JPS5816616B2 (en) 1978-12-01 1978-12-01 semiconductor equipment

Country Status (3)

Country Link
EP (1) EP0012019B1 (en)
JP (1) JPS5816616B2 (en)
DE (1) DE2966314D1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137285A (en) * 1982-02-10 1983-08-15 株式会社日立製作所 Ceramic board with metal plate and method of producing same
JPS6060172U (en) * 1983-09-13 1985-04-26 本田技研工業株式会社 Transformer device with rectifier
DE19726534A1 (en) * 1997-06-23 1998-12-24 Asea Brown Boveri Power semiconductor module with closed submodules
EP1403923A1 (en) * 2002-09-27 2004-03-31 Abb Research Ltd. Press pack power semiconductor module
DE102005046710B4 (en) * 2005-09-29 2012-12-06 Infineon Technologies Ag Method for producing a component arrangement with a carrier and a semiconductor chip mounted thereon

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1213484A (en) * 1958-08-04 1960-04-01 Thomson Houston Comp Francaise Non-isotropic conductive medium for intense heat flow
JPS5116302B2 (en) * 1973-10-22 1976-05-22
JPS5846059B2 (en) * 1977-04-15 1983-10-14 株式会社日立製作所 semiconductor equipment
JPS603776B2 (en) * 1977-06-03 1985-01-30 株式会社日立製作所 semiconductor element

Also Published As

Publication number Publication date
DE2966314D1 (en) 1983-11-17
EP0012019A1 (en) 1980-06-11
JPS5575249A (en) 1980-06-06
EP0012019B1 (en) 1983-10-12

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