JPS58165342A - Semiconductor ic and programing method thereof - Google Patents

Semiconductor ic and programing method thereof

Info

Publication number
JPS58165342A
JPS58165342A JP57047161A JP4716182A JPS58165342A JP S58165342 A JPS58165342 A JP S58165342A JP 57047161 A JP57047161 A JP 57047161A JP 4716182 A JP4716182 A JP 4716182A JP S58165342 A JPS58165342 A JP S58165342A
Authority
JP
Japan
Prior art keywords
wiring
circuit
programing
laser
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57047161A
Other languages
Japanese (ja)
Inventor
Takeoki Miyauchi
宮内 建興
Mikio Hongo
幹雄 本郷
Hiroshi Yamaguchi
博司 山口
Katsuro Mizukoshi
克郎 水越
Takao Kawanabe
川那部 隆夫
Osamu Minato
湊 修
Kotaro Nishimura
光太郎 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57047161A priority Critical patent/JPS58165342A/en
Publication of JPS58165342A publication Critical patent/JPS58165342A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To perform a laser diffusion program having no thermal influence upon the same by a method wherein a programing circuit for power supply and two power supply pads are provided in addition to a programing circuit to perform the final diffusion of P utilizing the Joule heat of power supply. CONSTITUTION:Circuit programing elements 2a-2z and wirings are provided on an insulative film while another wirings common to elements 2a-2z and pads 14, 15 are further provided to connect to the other ends of the wiring of said elements 2a-2z and the power supply programing elements 10a-10z, common wirings and pads are provided. When a programing high resistant poly Si wiring is irradiated by laser, the wiring is preliminarily made low resistant by a laser power much lower than the damage threshold value then the poly Si wiring is supplied with minute current to accelerate diffusion by the self heating of the high resistant section attaining to satisfactorily low resistant value.

Description

【発明の詳細な説明】 本発明は、半導体集積回路のプログラミングに関するも
のである。特に、回路プログラムにおいて、レーザ照射
に電気抵抗加熱を併用するととにより、高精度なレーザ
照射を必要とせず高い生産性を実現するプログラミング
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to programming of semiconductor integrated circuits. In particular, the present invention relates to a programming method that achieves high productivity without requiring highly accurate laser irradiation by using electric resistance heating in combination with laser irradiation in circuit programming.

集積回路の配線の一部を切断または短絡することにより
、製作済の回路チップにプログラムを行うことができる
。従来、とのプログラム方法は、例えば、読み出し専用
メモ9(ROM)のプログラム等に用いられてきた他、
最近ではメモリ素子の欠陥上ルの救済に利用されている
Fabricated circuit chips can be programmed by cutting or shorting some of the integrated circuit wiring. Conventionally, the programming method has been used, for example, to program read-only memo 9 (ROM), etc.
Recently, it has been used to repair defects in memory devices.

これらの従来法はつぎのような方法を用いるのが通例で
ある。
These conventional methods usually use the following method.

+1)  電流により、ヒユーズを溶断せしめ、配線の
切断を行なう。
+1) The current blows out the fuse and cuts the wiring.

(2)  レーザパルスにより、外部から光学的にエネ
ルギを与え、配線の切断、接続を行なう。
(2) Optical energy is applied externally using laser pulses to cut and connect wiring.

第1図はこの従来技術の回路構成を示したもので、正規
のメモリセル列1a〜1zはプログラミング素子2a〜
2tを介して正規回路につながっている。予備メモリセ
ル列3はこのプログラミング素子2a〜22に並列に接
続されており、正規メモリセル列1α〜1zのうちの一
つ、例えば1yのメモリセル列に欠陥が発見されたら、
プログラミング素子2yを使用して17 K接続されて
いる配線を予備メモリセル列3に切換える。
FIG. 1 shows the circuit configuration of this prior art, in which regular memory cell rows 1a-1z are connected to programming elements 2a-2a.
It is connected to the regular circuit via 2t. The spare memory cell column 3 is connected in parallel to the programming elements 2a to 22, and if a defect is found in one of the regular memory cell columns 1α to 1z, for example, memory cell column 1y,
The 17K connected wiring is switched to the spare memory cell column 3 using the programming element 2y.

第2図(α) # (b)はこの切換えに配線切断を行
う従来技術の一例である。Si基板4からSin、膜5
によって電気的に絶縁された多結晶SiまたはMの配線
6に、上にかぶせられたパシベーション膜7を通してレ
ーザ光8を照射し、これを切断してプログラミングを行
なう方法である。この−例トシテ、R,p、Canke
rら(19791SSCCDiggst of Tec
hnical pap、art )により、MOSメ、
1′ そりのデコーダの配線の変11.更を行ない、メモリの
欠陥セルに接続されたて、:コーグを切り離し、ダミレ
・−ダに接続され痘ニー欠陥のないセルと取り換えると
いう実験結果が示されている。然しなから、このように
素子を切断する方法は以下の欠点を有する。
FIG. 2(α) #(b) is an example of a conventional technique in which wiring is cut for this switching. From Si substrate 4 to Si film 5
In this method, a laser beam 8 is irradiated onto a polycrystalline Si or M wiring 6 electrically insulated by a polycrystalline Si or M wiring 6 through a passivation film 7 placed thereon, and the wiring is cut to perform programming. This - Example Toshite, R,p, Canke
r et al. (19791SSCCDiggst of Tec
hnical pap, art), MOS me,
1' Change in the wiring of the warp decoder 11. Experimental results have been shown in which a cell connected to a defective memory cell is disconnected and replaced with a non-defective cell connected to a memory card. However, this method of cutting elements has the following drawbacks.

(1;  レーザのエネルギとして大きなものが必要で
あり、しかも切断時に第2図(α)K示すように溶融飛
散する配線部分と周辺の材料9が近傍のパシベーション
膜7を損傷したり、レーザビーム8が付近の基板に損傷
を与えやすい。
(1; A large amount of laser energy is required, and in addition, as shown in FIG. 2 (α) K, the wiring portion and surrounding material 9 that melt and scatter during cutting may damage the nearby passivation film 7, and the laser beam 8 tends to damage nearby boards.

このため、レイアウトに十分余裕が必要で、大面積とな
る。
Therefore, a sufficient margin is required in the layout, resulting in a large area.

(2)  また、大面積としても切断部へのレーザ照射
に際しては、周辺に影響を与えないためKは例えば5μ
罵パターンに対しては±1μ屏というよ5に十分高い位
置精度が必要となり、量産に際し、高速処理するためk
は、装置に対し、高速高精度という相反する要求を同時
に満足させるζ・とを要求することとなり、実現し得て
も大変高価なものとなる。また、切断:′:・ 部周辺に機能素子をおくことも信頼性の上が□・:l”
”””jlll:j ら離しい。  )。
(2) In addition, even if the area is large, when laser irradiation is performed on the cut section, K should be set at 5μ, for example, so as not to affect the surrounding area.
For abusive patterns, a sufficiently high positional accuracy of ±1μ is required, and in order to perform high-speed processing during mass production,
This requires the device to satisfy the contradictory demands of high speed and high precision at the same time, and even if it can be realized, it will be very expensive. In addition, placing functional elements around the cutting area also improves reliability.
"""jllll: away from j.).

(3)  切断という手段だけでは不足でありて、短絡
を用いるとチップの占有面積上有利となる場合がある。
(3) Cutting alone may not be sufficient, and shorting may be advantageous in terms of the area occupied by the chip.

第3図は従来技術の他の一例で、Si基板4からSL 
Ot膜5によって電気的に絶縁され、低抵抗多結晶Si
配@6αにはさまれた高抵抗多結晶Si配線6b (抵
抗値夕1010Ω)に、上にかぶせられたパシベーショ
ン膜7を通してレーザ8を照射し、高抵抗多結晶Si配
@6hを低抵抗化して接続させるという技術が提案され
ている。然しながう、このように配線接続する方法は、
以下の欠点を有する。
FIG. 3 shows another example of the prior art.
Electrically insulated by Ot film 5, low resistance polycrystalline Si
The high-resistance polycrystalline Si wiring 6b (resistance value 1010Ω) sandwiched between the wires @6α is irradiated with a laser 8 through the passivation film 7 overlaid on it to lower the resistance of the high-resistance polycrystalline Si wires @6h. A technology has been proposed that connects the However, this method of wiring connection is
It has the following drawbacks.

(11十分抵抗値を下げるためには、レーザ照射パワー
密度をダメージ閾値近くまで上げなければならないた′
め、レーザ照射によりて基板周辺に損傷を与えやすい。
(11) In order to sufficiently lower the resistance value, the laser irradiation power density must be increased to near the damage threshold.
Therefore, laser irradiation is likely to cause damage to the periphery of the substrate.

このため、レイアウトに十分の余裕が必要で、大面積と
なる。
Therefore, a sufficient margin is required in the layout, resulting in a large area.

(2)  また大面積としても、接続部へのレーザ照射
に際しては周辺への影響をおさえるためには十分高い位
置精度が必要となり、量産時、高速で処理するためには
、装置がかなり高価となる。また接続部周辺に機能素子
をおくことも信頼性の上から難かしい。
(2) Also, even if the area is large, sufficiently high positional accuracy is required to suppress the influence on the surrounding area when irradiating the laser to the connection part, and the equipment is quite expensive to process at high speed during mass production. Become. Furthermore, it is difficult to place functional elements around the connection portion from the viewpoint of reliability.

(3)  接続という手続だけでは不足であって、切断
も併用するとチップの占有面積上有利となる場合がある
(3) There are cases where the procedure of connection alone is insufficient, and combining disconnection may be advantageous in terms of the area occupied by the chip.

第4図乃至第6図は従来技術で切断、または接続をする
ための配線の周辺部に機能素子が配された場合の問題点
を示す図セある。第4図が平面図、第5図と第6図はそ
れぞれ、纂4図における一−B断面図とC−D断面図で
ある。Si基板4上からSi0.@5を隔てて設けられ
たpoly −SiまたはM配線6dKレーザ8が照射
されPo1y −SiまたはMの配@6dの切断、また
はpolySi配線6dの接続が行われる。しかし、2
〜3μmの配線部分に高精度で位置決めができ、しかも
高速で処理するKは装置に大きな負担となるため、実用
上は配@6dに照射するレーザ8のサイズは配1lA6
dのサイイに比べかなり大きなものと存らざるを得ない
。すると、本従来例の場合配@6dの両側に設けられた
機能部分14の中に熱影響の恐れのある機能部分15が
存在するととKなる。このため、ある程度精度を犠牲に
して処埋の高速性を実現するためには、機能部分はレー
ザ照射部からできるだけ離す必要があり、チップの大面
積化はさけられない。
FIGS. 4 to 6 are diagrams showing problems when functional elements are disposed around wiring for cutting or connecting in the prior art. FIG. 4 is a plan view, and FIGS. 5 and 6 are sectional views taken along line 1-B and line CD in FIG. 4, respectively. Si0. The poly-Si or M wiring 6dK laser 8 provided across @5 is irradiated to cut the poly-Si or M wiring @6d or connect the polySi wiring 6d. However, 2
The size of the laser 8 that irradiates the wiring @ 6d is 1lA6 in practice, because it is possible to position the wiring part of ~3 μm with high precision and to process it at high speed, which places a heavy burden on the equipment.
I can't help but think that it is considerably larger than the size of d. Then, in the case of this conventional example, if there is a functional part 15 that is likely to be affected by heat among the functional parts 14 provided on both sides of the wiring 6d, then K is obtained. Therefore, in order to achieve high processing speed at the expense of some degree of accuracy, it is necessary to place the functional part as far away from the laser irradiation part as possible, and an increase in the area of the chip is unavoidable.

なお、10は燐ガラス、11はSi、N4,12は第一
層M配線、13は第2層M配線である。
Note that 10 is phosphor glass, 11 is Si, N4, 12 is first layer M wiring, and 13 is second layer M wiring.

本発明の目的は上記した従来技術の欠点をなくし、高密
度集積回路のプログラミングを高速高信頼で行なうこと
のできる半導体集積回路とそのプログラム方法を提供す
るにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a semiconductor integrated circuit and a programming method for the same, which allow programming of a high-density integrated circuit at high speed and with high reliability.

即ち本発明は、半導体基体上に設けられた絶縁膜上に、
回路プログラム用素子と配線を設は該回路プログラム用
素子に共通する配線とパ。
That is, in the present invention, on an insulating film provided on a semiconductor substrate,
The circuit programming elements and wiring are set up using common wiring and paths for the circuit programming elements.

ドを設け、蚊回路プログラム用素子の他端の配線に接続
して通電用プログラム素子および共通する配線とパッド
を設けたことを特徴とする半′111 導体集積回路である。  k 、1.11.:l、l:
、II、II’。
This semi-conductor integrated circuit is characterized in that it is connected to the wiring at the other end of the mosquito circuit programming element, and is provided with an energizing programming element and a common wiring and pad. k, 1.11. :l,l:
, II, II'.

、、:・1品:、、′ また、本発明は、プロブレ・ム用高抵抗poly −5
i配線をレーザ照射する際、ダメージ閾値よりずっと低
いレーザパワーで予備的に低抵抗化し次にこのpoly
−5i配線に微細電流を流して高抵抗部の自己発熱によ
り拡散を促し、十分低い抵抗値を得るという方法である
,,:・1 item: ,,' The present invention also provides high resistance poly-5 for problem
When irradiating an i-wire with a laser, the resistance is preliminarily reduced using a laser power much lower than the damage threshold, and then this poly
In this method, a minute current is passed through the -5i wiring to promote diffusion through self-heating of the high-resistance portion, thereby obtaining a sufficiently low resistance value.

以下本発明を図に示す実施例にもとづいて具体的に説明
する。
The present invention will be specifically described below based on embodiments shown in the drawings.

第7図は本発明の一実施例を示す回路構成図である。正
規のメモリーセル列1α〜1zのうちの1yの列に欠陥
セルがある場合、この1yを予備のセル列3に切り換え
るとチップを不良とせずKすむ。そこで、予め設けられ
ているプログラム回路2a〜2zのうち2yの所定部分
にレーザ光を照射し、回路を1yから5に切換える。こ
のプログラム回路は第6図で示した如く、低抵抗ポ9S
iではさまれた高抵抗ボ9Si配線からなっており、こ
こに、周辺に熱影響を与えないような低いパワー密度、
、(5X10’〜2×107Ir/cd)のレーザ光を
照射し、1し、ログラム部の高抵抗ポリSiを、″・。
FIG. 7 is a circuit diagram showing an embodiment of the present invention. If there is a defective cell in column 1y of the regular memory cell columns 1α to 1z, switching 1y to spare cell column 3 will prevent the chip from becoming defective. Therefore, a laser beam is irradiated to a predetermined portion of 2y among the program circuits 2a to 2z provided in advance to switch the circuit from 1y to 5. As shown in Fig. 6, this program circuit has a low resistance point 9S.
It consists of high-resistance board 9Si wiring sandwiched between
, (5 x 10' to 2 x 107 Ir/cd) laser light is irradiated, and the high-resistance poly-Si in the programmable part is ''.

1MΩ前後に予備的°(低抵抗化する。同時に同様の構
造を持つ通電用プログラム回路104〜10zのうちt
oyの所定のプログラム部分にも同じ低パワー、密度の
レーザ光を照射し、1MΩ前後に整える。次にプログラ
ム回路2α〜2zおよび通電用プログラム回路10α〜
102に共通して接続されてい−る通電用パッド14.
15を用いて電圧を5〆印加する。パッド14のプログ
ラム回路11には1MΩの抵抗が挿入されている。
Preliminary degree (resistance is reduced to around 1 MΩ. At the same time, among the energizing program circuits 104 to 10z having a similar structure, t
A predetermined program portion of the oy is also irradiated with the same low power and density laser beam to adjust it to around 1MΩ. Next, program circuits 2α to 2z and energizing program circuits 10α to
A current-carrying pad 14 commonly connected to 102.
15 to apply a voltage of 5 times. A 1MΩ resistor is inserted into the program circuit 11 of the pad 14.

従って、メモリセル列1yを3に切換えるときには、2
y、10yiC弱いレーザ光を照射し、それぞれ1MΩ
前後としたのちパッド14,15を利用して5Vを印加
する。すると2yには約t7μAの電流が流れ、2.9
μWの発熱を生じる。1秒では2.9μ)に相当し10
−11−のポリSiを十分高温にできる、。
Therefore, when switching memory cell row 1y to 3, 2
y, 10yiC weak laser beam irradiation, each 1MΩ
After switching back and forth, 5V is applied using pads 14 and 15. Then, a current of about t7μA flows through 2y, and 2.9
Generates μW of heat. In 1 second, it corresponds to 2.9 μ), which is 10
-11- The poly-Si can be heated to a sufficiently high temperature.

プログラム素子の高抵抗ポリSiはSin、等の低熱伝
導性の絶縁体で囲まれているため、通電によって断熱加
熱に近い状態になり、十分Pの拡散の起る高温になる。
Since the high-resistance poly-Si of the program element is surrounded by an insulator with low thermal conductivity such as Sin, when electricity is applied, the state is close to adiabatic heating, and the temperature becomes high enough to cause P diffusion.

このため、レーザ照射により低抵抗ポ9Si側から拡散
してきたPの拡散が一段と進み、1MΩ程度であったプ
ログラム部のポリSiが108〜104Ωの抵抗値に低
下し、必要な低抵抗化のプロセスが完了−1゜ 以上説明したように本発明は、プログラム回路の他に、
通電用プログラム回路および2つの通電用パッドを設け
ておき、通電によるジュール熱でPの最終拡散を行うよ
うにしたから、レーザ照射時のレーザパワー密度を十分
低くおさえ、熱影響の恐れの残らないレーザ拡散プログ
ラミングを実施できるようkなる効1果を奏する。
For this reason, the diffusion of P that has diffused from the low-resistance poly-9Si side due to laser irradiation further progresses, and the resistance value of the poly-Si in the program area, which was about 1 MΩ, decreases to 108-104 Ω, which is necessary for the process of lowering the resistance. is completed -1° As explained above, the present invention, in addition to the program circuit,
A program circuit for energization and two energization pads are provided, and the final diffusion of P is performed using Joule heat due to energization, so the laser power density during laser irradiation is kept sufficiently low, and there is no fear of thermal effects. This has the advantage of allowing laser diffusion programming to be performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のビット救済プログツム素子の配置とその
欠点を示す説明図、第2図←) 、 (A)は配線切断
を行う従来技術の一例を示した図、第3図は他の従来の
プルグラミング法の一例を示す図、第4図、第5図、第
6図は第3図に示す方式における問題点を示す図、第7
図は本発明の一実施例を示す図である。 1α〜1z・・・・・・・・・正規のメモリーセル列3
・・・・・・・・・・・・・・・・・−・・予備セル列
2α〜2z・・・・・−・・プログラム回路10a〜1
0Z・・・通電用プログラム回路14.15・・・・・
・・・・・・・パッド代理人弁理士 薄 1)利、−2
申 jil!1図 第 2図 <a> 一ノー〜4 (1)) ρ4 第 3 図 第 4 閃 、4        A 給 5 図 第 7 図 第1頁の続き 0発 明 者 湊修 国分寺市東恋ケ窪−丁目280番 地株式会社日立製作所中央研究 所内 0発 明 者 西村光太部 小平市上水本町1450番地株式会 社日立製作所武蔵工場内
Fig. 1 is an explanatory diagram showing the arrangement of a conventional bit relief program element and its drawbacks, Fig. 2 (←), (A) is a diagram showing an example of a conventional technique for cutting wiring, and Fig. 3 is an explanatory diagram showing the arrangement of a conventional bit relief program element and its drawbacks. Figures 4, 5, and 6 are diagrams showing problems in the method shown in Figure 3.
The figure shows an embodiment of the present invention. 1α~1z・・・・・・Regular memory cell row 3
・・・・・・・・・・・・・・・・・・・・・・Spare cell rows 2α to 2z・・・・・・・・・・・・Program circuits 10a to 1
0Z...Program circuit for energization 14.15...
・・・・・・Patent attorney representing Pad Susuki 1) Interest, -2
Oh my god! Figure 1 Figure 2 <a> 1 no ~ 4 (1)) ρ4 Figure 3 Figure 4 Flash, 4 A Supply 5 Figure 7 Continuation of Figure 1 page 0 Inventor Osamu Minato 280 Higashi Koigakubo-chome, Kokubunji City Inside the Central Research Laboratory, Hitachi, Ltd. 0 Inventor: Kotabe Nishimura, 1450 Kamimizu Honmachi, Kodaira City, inside the Musashi Factory, Hitachi, Ltd.

Claims (1)

【特許請求の範囲】 1 半導体基板上に設けられた絶縁膜上に、回路プログ
ラム用素子と配線を設け、該回路プログラム用素子に共
通する配線とパッドを設け、核回路プログラム用素子の
他端の配IHK接続して通電用プログラム素子および共
通する配線とパッドを設けたことを特徴とする半導体集
積回路。 2、機能部分に照射しても熱影響を残さない低いレベル
のパワー密度で回路プログラム用素子を予備プログラム
し、次に、その抵抗値の変化を利用して通電を起させ、
この発熱で拡散を完了させることによりプログラミング
を完成させることを特徴とする半導体集積回路の回路プ
ログラム方法。
[Claims] 1. A circuit programming element and a wiring are provided on an insulating film provided on a semiconductor substrate, a wiring and a pad common to the circuit programming element are provided, and the other end of the nuclear circuit programming element is provided. What is claimed is: 1. A semiconductor integrated circuit characterized in that a programming element for energization and a common wiring and pad are provided by IHK connection. 2. Pre-program the circuit programming element with a low level of power density that does not leave a thermal effect even when irradiated to the functional part, and then use the change in resistance value to cause energization,
A circuit programming method for a semiconductor integrated circuit characterized in that programming is completed by completing diffusion using this heat generation.
JP57047161A 1982-03-26 1982-03-26 Semiconductor ic and programing method thereof Pending JPS58165342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57047161A JPS58165342A (en) 1982-03-26 1982-03-26 Semiconductor ic and programing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57047161A JPS58165342A (en) 1982-03-26 1982-03-26 Semiconductor ic and programing method thereof

Publications (1)

Publication Number Publication Date
JPS58165342A true JPS58165342A (en) 1983-09-30

Family

ID=12767350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57047161A Pending JPS58165342A (en) 1982-03-26 1982-03-26 Semiconductor ic and programing method thereof

Country Status (1)

Country Link
JP (1) JPS58165342A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245060A (en) * 1985-08-21 1987-02-27 Mitsubishi Electric Corp Semiconductor non-volatile memory device
JPH01125951A (en) * 1987-11-11 1989-05-18 Hitachi Ltd Transistor circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245060A (en) * 1985-08-21 1987-02-27 Mitsubishi Electric Corp Semiconductor non-volatile memory device
JPH01125951A (en) * 1987-11-11 1989-05-18 Hitachi Ltd Transistor circuit device

Similar Documents

Publication Publication Date Title
US7732892B2 (en) Fuse structures and integrated circuit devices
TW445590B (en) Semiconductor apparatus with multi-layer wiring structure
US4581628A (en) Circuit programming by use of an electrically conductive light shield
EP0078165B1 (en) A semiconductor device having a control wiring layer
US8421186B2 (en) Electrically programmable metal fuse
US4602420A (en) Method of manufacturing a semiconductor device
KR20030045603A (en) Programmable device programmed based on change in resistance values by phase transition
JP3689154B2 (en) Electronic circuit manufacturing method, semiconductor material wafer, and integrated circuit
US4404635A (en) Programmable integrated circuit and method of testing the circuit before it is programmed
JP2000091438A (en) Semiconductor device and its manufacture
CN101740543A (en) Fuse structure for intergrated circuit devices
JP2004214580A (en) Fuse layout and trimming method
US5827759A (en) Method of manufacturing a fuse structure
US5572050A (en) Fuse-triggered antifuse
JPH0773106B2 (en) Method for manufacturing semiconductor device
JPS58165342A (en) Semiconductor ic and programing method thereof
US3881175A (en) Integrated circuit SOS memory subsystem and method of making same
JPH0428249A (en) Semiconductor device
JPS5843907B2 (en) Semiconductor integrated circuit and its circuit programming method
JP3495835B2 (en) Semiconductor integrated circuit device and inspection method thereof
JPS5843906B2 (en) Semiconductor integrated circuit and its circuit programming method
JPH0412545A (en) Semiconductor device and fabrication method
JPS59229838A (en) Semiconductor integrated circuit
JPH0760853B2 (en) Laser beam programmable semiconductor device and manufacturing method of semiconductor device
KR101168395B1 (en) Fuse of semiconductor device and method for manufacturing the same