JPS58160984A - Display screen scroll system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [O technical field] This is a CR in character display silver content.
This is related to the method of scrolling the data of the T image K11I.

[Technical background of the invention]

In the character display system, store the refresh nose display data (lard), read it out using the signal output from the timing generation path, and then read out the display data from the internal display data. A display (character) pattern is generated by inputting the data to a generator, and the ζO display pattern is converted into a video signal and shown as CBT''e@.

In accordance with this type of display device, when the display screen is scrolled, the screen is scrolled one line at a time. If 4 strokes of characters are displayed on one screen, the display data of the fresh memory, for example, from address 0 to address 3, is displayed in the first display, and the second In the display, the display data from address 1 to address 4 of the refresh memory is displayed, thereby performing a one-line swallow-A- operation.

[Problems with background technology]

However, when scrolling one line at a time like this, lIi? Because the degree of change in kl is large, the viewer becomes tired, feels uncomfortable, and has difficulty viewing the first page continuously.

[Purpose of the invention]

The present invention has been developed in view of the drawbacks of the conventional method. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a display screen scrolling method in which the display orientation changes continuously and does not cause fatigue or discomfort to the viewer.

[Summary of the invention]

So ζ, expand with this book, CR from character generator
Rather than sequentially removing h pits of the display pattern in the route leading to T, it was decided to perform O star training for h bits at a time. As an example, at the stage of sending out the display pattern from the Hiro and Naka Yara Tata generators, the slice addresses of the Naka Yarakuta generator are sequentially slid by n bits F, so that a part of the IK display pattern is missing. Set K so that it is output as .

Another example is to output all display patterns from the character generator, but make the display patterns serial and set the l1% latch tie conductor by n bits at a time, so that part of one display pattern is Mourning as if missing.

[Threat-O collection example]

Below, I will explain in detail the implementation example of this project, with the help of La drawings.
ll@. Rattan 1 ■ line is a block diagram of a display silver amount that performs scrolling according to the O method of the present invention.

In the same figure, this main control I11 shows the 1st main control section.
according to their own programs.

This is a processor that controls each of the illustrated parts. and,
The main control unit 1 receives and receives display data (code) sent from a higher-level device (not shown), provides a write address from the address bus, outputs display data from the data bus 16, and displays the data. The data is stored in the 97-receiver memory 2.

The display data stored in this refresh memory 2 is
The read address generated by the read address generation circuit 7 is also read out via the address bus, and is introduced into the character generator 3 via the data bus 17. The character generator 3 generates a display (character) pattern based on the input nine display data, and this display pattern is read out in parallel every 471 slices according to the slice address given from the rotator 9 via the address bus 15.

The read display pattern is sent to the parallel-to-direct converter 4 via the data bus, and the signal 1m2 is sent from the tie-setting generation circuit 6.
It is latched by the tie-up of the latch signal applied through 1. The latched display pattern is converted from parallel data to serial data and displayed on the CRT 5KMD via a signal line 19 as a video signal.

The read address generation circuit 7 which supplies the read address to the above-mentioned glue 7 retrieval memory 2 updates the temporary address given by the incrementer 8 based on the address given from the rotator 9. Assuming that the display pattern consists of four slices (four bits in the vertical direction), the rotator 9 outputs four types of slice addresses (for example, address O to address 3) via the address bus 15. Every time this slice address goes around once, the read address generation circuit γ updates the nine temporary address given by the incrementer 8 by adding one. When the display of one frame is completed, the output address is set to the temporary address given by the incrementer 8 *L, and each time the slice address goes around once again, the temporary address is incremented by 1.

On the other hand, the low timer 9 includes a callan l, and the timing generation circuit 6 increments a counter based on the pulse output from the signal [13, and adds the preset temporary slice address and the value of the counter. Output. (However, if the addition result exceeds 4, the addition result is minus 4.) In this embodiment, the temporary slice address is initially address 0, and the timing generation circuit 6 The address is updated by the pulse given by the address, and the addresses from address 0 to address 3 are rotated.

Also, the incrementer 8 updates the temporary heeling address by the pulse given from the tying generation (9) path 6 via the signal @10. For example, if the address is initially O, then the pulse Address 1, address 2, etc. each time one is given. -m-.

The tie ink generation circuit 6 connects signal lines 10 , 13 , 13
'.

4 to output a pulse with a predetermined tie ink.

This controls the input/output tying of data in the route from the memory 2 to the CRT 5 for receiving data.The tying of each pulse will not be explained in detail here, but its function will be clarified by the operation described below. Make it.゛Hereinafter, the display operation will be explained with reference to Figures 1 to 3.

Now, when data is about to start being output from the 97 retrieval memory, the read address generator 7 is set to output address 0 as in 2am 0, and the incrementer 8 is set to output address 0. It is assumed that the rotator 9 is also set to output address 0.

Then, the address of memory 2 is OK because the 7th record is stored in the 9th sgm O.
110012348 ) is given to the character generator 3 via f-)/(x17).

At this time, Rotic 9 changes address 0 to 11/IIHI
Since it is output from the k intestine, character generator 3
1 slice 1! The OII indication pattern is output via the data bus, and the pulse of the latched note is given via the TK signal signal like the second WAM.
This l-th slice display data is latched, subjected to l[order parallel/direct conversion, and output as a video signal.

At the tie ink of the rising edge of the pulse of the signal *2io latch signal, the tie generation circuit 6 outputs a pulse from the signal line 13'. Then, the counter in Rohtik 9 becomes "l"
As a result, rotator 9 outputs address l. From this K, the display pattern of the second slice of the character generator 3 is output onto the data bus 18. Thereafter, by the same operation as described above, the display pattern of the second slice is converted into a video signal and reaches the CRT 5.

In this way, each time a pulse is output to the signal lines 13' and 21, the display pattern for one slice is made into a video signal, and the fourth pulse is the signal 4113'.

When the signal is output from the system, the counter in the rope iter 9 returns to zero. Therefore, the output of rotator 9 is address O, and the seven read address generation circuits that receive this output address lt-. As a result, the display data of the second line of memory 2 (6789 column B in FIG.
) is read out and converted into a p-video signal by the operation described above.

1.CRT! Assuming that 5KaA lines of characters are displayed, the counter in %--timer 9 rotates p13 times by the pulse given from signal -13', sets the count value to O, and returns the 8th WjABO to 9 and itself. Hiro is displayed on the KC 凰is.

ζ0I11!111mM leftmost) Tying generation - path 6 sends a pulse via signal -13. From this, since the count value of the company slice address IK kakunta is added and output in the fourth tick 9, the output end address of the rotator 9 becomes the company address l.

On the other hand, at the read address *44!1187, the display for one screen is completed and at 90 (4 addresses 0 are input and at 90), the temporary address output by the incrementer 8 is outputted as Oat. . *Refre V & Mekari 2 are also output, and the data shown in 1lIII is the display data of the 1st line in the 3rd Mum O Refresh 2, and the middle Yatsuta generator 3 is also output. The display pattern is
2 slices of Va data @ 6 for OW pattern.

Thereafter, the above-mentioned operation is repeated, and as shown in FIG.
The display will show that the slice has appeared.

By outputting pulses at predetermined timing from the timing generating circuit 6 as shown in FIG. In this embodiment, the timing generation circuit 6 outputs a pulse to the signal line 10 at the end of the display of every four screens. As a result, the temporary address when displaying the fifth screen becomes address 1.

In this embodiment, scrolling is performed vertically one bit at a time, but it is also possible to scroll vertically every n bits (n is an integer).

Also, if the rotator function is stopped using the circuit shown in Figure 1,
It is possible to scroll line by line. Ninth, when you stop the incrementer operation, the same screen will be displayed.

Next, another embodiment of the present invention will be described with reference to FIG. #I4 Figure 1 is a block diagram of the amount of display silver that scrolls the display screen in the horizontal direction.

In 11 i, the same components as in the iris 1 diagram are given the same reference numerals, so in order to omit the explanation, in this embodiment, the address output by the incrementer 8 is input by the address bus. The refresh function is given to the message 2 and the display data is read out.

First, the serial t* pattern output from the 311 direct conversion Iku 4 via the signal line 1v is the data latch am23.
It is latched, but the tying of the latch is 25
This makes the tie-on of the original latch signal far more difficult.

The tying signal line 5 outputs a latch signal given through the tying signal line % every time the display of one screen is completed.
For example, it is delayed one bit at a time and output to the signal line 22.

Now, it is assumed that the 7-receiver memory 2 is a horizontal memory as shown in No. 5811, and the addresses are from address 0 to address 3. Then, at the start of the operation, the length of the delay line 20 is 0, so for example, the display pattern of the first slice of the display pattern at address 0 is changed to the sixth slice by the pulse of the latch signal applied from the signal line n. As shown in the figure, from the rightmost column in the refresh memory 2 to the CRT
50 lateral capacitances are latched. Thereafter, slices 2 to 4 are latched in the same way. Further, at one timing, a pulse is given from the raw circuit 6 via the signal 4910, and address 1 is given to the refresher memory 2,
The display data on the second line is output, and the same processing is performed thereafter. In this manner, one screen's worth of display is displayed on the KCRT 5 as shown in FIG.

Next, for the display of the second car type, the timing generation circuit 6
When a pulse is sent to the incrementer 8 from the incrementer 8, the incrementer 8 outputs the address O.

After this, the display data corresponding to address 0 of the fresh memory 2 is input to the character generator 3, and the character generator 3 generates a corresponding display pattern. At the same time, the timing generation circuit 6 gives the address O via the address bus 15, and the character generator 3 outputs the display pattern of the first slice. Furthermore, the timing generation circuit 6 generates a pulse that provides latch timing via the signal line GA.
It is given to the direct conversion section 4. As a result, the display pattern of the first slice is converted into serial data and sent out via the signal 1!19'.
outputs a pulse that provides latch timing by one bit. Therefore, as shown in FIG. 6B, the right l bit in the rear leg memory 2 is missing and latched into the data latch circuit B.

Thereafter, 41 bits are latched from the 2nd slice to the 4th slice in the same way. Further, when a pulse is applied from the tying generation steel path 6 via the signal l1i10 and address 1 is output from the incrementer 8, the display data of the second line is output from the 7receiver memory 2. Ru. After this, the second row is also latched with a delay of one bit in the same manner as described above. Address 3 below
At t, the same #& place is '&, and in the display of s 2i@i face, some of the characters on the right side are missing, and part of the next character appears on the left side, as in 71EIB.

Similarly, each time the display for one screen is completed, the delay circuit 6
The amount of delay is large and scrolling is performed in the horizontal direction.

Incidentally, if the amount of delay is set to n bits at a time, then the negative crawl is performed by rr bits at a time.

Further, in this embodiment, vertical scrolling is possible by exchanging the positions of the parallel/direct converter 4 and the data latch circuit. Let fl, , and data latch circuit be a parallel data latch circuit. In this case, for example, the display pattern of the first slice outputted by the data latch circuit is not latched by the parallel/direct converter, but the display pattern of the second slice is latched. Therefore, one slice has been scrolled.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the amount of scrolling, so the viewer does not get tired, and it is also possible to view the screen continuously.

[Brief explanation of the drawing]

#I1 figure is the program aa of the display device that adopts the present invention-O method, iris 2WJ is a tying chart explaining the operation of figure 1, and 3rd wA is the correspondence between the message and the screen due to the operation of ill. 48 is a conceptual diagram of an example of a display device adopting the method of the present invention, and FIG. 5 is a conceptual diagram of the 411th reflex V & memory.
jlI6WjA is a nine-tying chart showing how the latch signal fluctuates, and FIG. 7 is a conceptual diagram of the display result according to No. 411. 1... Main control 2... 7 Reshi island memory 3... Intermediate player generator 4... Parallel/L direct converter 5... CRT6... Tying connection

Claims (1)

[Claims] (1) Nine display data stored in a memory for refreshing is read out using a signal output from a timing generation circuit, inputted to a character generator and converted into a display pattern, and a video signal is obtained from this and sent to a CRT. In the display screen scrolling method for scrolling display, the display-screen scrolling method is characterized in that scrolling is performed by 3211 minutes by sequentially removing the display pattern by 3211 minutes within the route from the character generator to the CRT. . (2) A display screen scrolling method according to claim (1), characterized in that the slice address given to the character generator is generated by sequentially sliding every 3211 minutes, and the display pattern is sequentially removed by 0 bits. . (8) After converting the display pattern into serial data,
Patent claim O characterized in that the display pattern is sequentially removed by 0 bits by extending the display pattern by 1 minute at a time.
＠OII display screen scrolling method described in Section (1) of I.