JPS58159669A - Rectifying circuit - Google Patents

Rectifying circuit

Info

Publication number
JPS58159669A
JPS58159669A JP4225082A JP4225082A JPS58159669A JP S58159669 A JPS58159669 A JP S58159669A JP 4225082 A JP4225082 A JP 4225082A JP 4225082 A JP4225082 A JP 4225082A JP S58159669 A JPS58159669 A JP S58159669A
Authority
JP
Japan
Prior art keywords
voltage
smoothing capacitor
input
capacitor
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4225082A
Other languages
Japanese (ja)
Inventor
Mitsutake Sato
佐藤 光勇
Michio Kono
河野 通男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4225082A priority Critical patent/JPS58159669A/en
Publication of JPS58159669A publication Critical patent/JPS58159669A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/14Arrangements for reducing ripples from dc input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

PURPOSE:To reduce the capacity of a smoothing condenser by maintaining the smoothing condenser at peak voltage for a while and discharging it in a short time. CONSTITUTION:When a thyristor SCR is OFF, a smoothing condenser C1' is charged until it becomes the peak value of the input peak voltage through a diode D1, and lowered after reaching the peak value. Then, the output voltage V0' is similarly lowered, and when the voltage difference between the output voltage V0' and the voltage VC1 across the condenser C1' exceeds the Zener voltage of a Zener diode DZ1, the diode ZD1 is conducted, a thyristor SCR1 is fired, and conducted. Accordingly, the condenser C1' is connected to the output terminal 2, and the output voltage V0' is maintained by the discharge of the condenser C1'.

Description

【発明の詳細な説明】 (al  発明の技術分野 不発明はコンテンサ入力形整流回路に係り、平滑コンデ
ンサの容量を小さく出来、かつ入力交流電流のピーク値
を不妊く出来る整流回路に関する0山)従来技術と問題
点 第1図は従来例のコンデンサ入力形整流回路の回路図、
第2図に第1図の場合の波形のタイムチャートで、囚は
出力電圧、@は整流回路への入力5emt訛である。
Detailed Description of the Invention (al) The technical field of the invention relates to a capacitor input type rectifier circuit, and relates to a rectifier circuit that can reduce the capacitance of a smoothing capacitor and suppress the peak value of input AC current. Technology and Problems Figure 1 is a circuit diagram of a conventional capacitor input type rectifier circuit.
FIG. 2 is a time chart of waveforms in the case of FIG. 1, where the symbol is the output voltage and @ is the 5emt input to the rectifier circuit.

図中Eに商用交流電源、RC,はプリタテ形整流器、C
Iは平滑コンデンサ、1は負荷、■、は出力電圧で負荷
10両−0電圧、Iinは整流回路への入力交流電流を
示す。
In the diagram, E is a commercial AC power supply, RC is a rectifier, and C is a rectifier.
I is a smoothing capacitor, 1 is a load, ■ is an output voltage, and Iin is an input alternating current to the rectifier circuit.

従来のコンデンサ入力形整流回路では、第2図に示す如
く、商用文流電@Eから整流回路に流丁電mu、a、a
から平滑コンデンサC0を充電しなから勇荷IKt流を
供給し、ブリッチ形整15を器RC。
In the conventional capacitor input type rectifier circuit, as shown in Fig. 2, the currents mu, a, a are transferred from the commercial commercial current @E to the rectifier circuit.
After charging the smoothing capacitor C0, the current IKt is supplied, and brittle shaping 15 is performed.

の出力電圧(■、)が最大値す点になると、次は平滑コ
ンデンサC,に貯えられた電荷により負荷1へ電流を供
給し、平滑コンデンサC1の両港の電圧が下り、プリッ
チ形JIR器RC,により整fltきれ次電圧が、平滑
コンデンサC1の両港の電圧より高くなる点Cになると
、再び商用交流電源Eより平滑コンデンサCIの充電電
流と負荷lに電流を供給−[る↓うになる。平滑コンデ
ンサC,より負荷1に電流を供給している関bc点間は
入力交流電流Iinに殆んど0であるが、平滑コンデン
サC,の充電電流を流す峙は大きなピーク電流となる。
When the output voltage (■, ) reaches its maximum value, the electric charge stored in the smoothing capacitor C, supplies current to the load 1, and the voltage at both ports of the smoothing capacitor C1 decreases, causing the prich type JIR device to When the voltage regulated by RC reaches point C, which is higher than the voltage at both ports of the smoothing capacitor C1, the commercial AC power supply E supplies the charging current of the smoothing capacitor CI and the current to the load l again. Become. The input AC current Iin between points bc and bc, which supplies current from the smoothing capacitor C to the load 1, is almost 0, but a large peak current occurs when the charging current of the smoothing capacitor C flows.

従って入力交流電RI i nは@2図@の如くで力率
は非常に悪い欠点がある。
Therefore, the input AC current RI i n is as shown in Figure 2, and has the disadvantage of a very poor power factor.

又負荷1(・こエネルギーを供給している時間の大部分
子x、=−嘴コンテンサC8である為、大きな容量のコ
ンデンサが必要となり、整R装置が大形になる欠点もあ
る。
In addition, since most of the time when the load 1 (·) energy is supplied to the molecule x, = -beak capacitor C8, a capacitor with a large capacity is required, and there is also the disadvantage that the R adjustment device becomes large.

(c)  発明の目的 本発明の目的は上記の欠点をなくシ、コンデンサ人力形
!I流回路の平滑コンデンサの小容量化及び入力交流電
流のピーク値を小はく出来る整流回路の提供にある。
(c) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks and create a human-powered capacitor! An object of the present invention is to provide a rectifier circuit that can reduce the capacity of a smoothing capacitor in an I-current circuit and reduce the peak value of input AC current.

(d)  発明の構成 本発明に上記の目的な達成するために、コンデンザ入力
形整流回路において、商用交流入力を両波Jl流した回
路に、ダイオードな介して平滑コンデンサを並列に接続
し、該平滑コンデンサと該ダイオードの接続点な、サイ
リスタを介し、出力端に接続し、該サイリスタのゲート
を咳平滑コンデンサの電圧と出力端の電圧との差によっ
て点弧させることにより、平滑コンデンサより、負荷に
エネルギーV供給開始時点を、整流電圧の鍛犬点工りで
なく、ある程f%圧が下り、該サイリスタの点弧時点か
らとすることを特徴とする。
(d) Structure of the Invention In order to achieve the above object of the present invention, in a capacitor input rectifier circuit, a smoothing capacitor is connected in parallel via a diode to a circuit in which a commercial AC input is passed in both waves. The connection point between the smoothing capacitor and the diode is connected to the output terminal via a thyristor, and the gate of the thyristor is fired by the difference between the voltage of the smoothing capacitor and the voltage of the output terminal, so that the smoothing capacitor can reduce the load. The present invention is characterized in that the point in time at which the energy V supply starts is not at the point where the rectified voltage is adjusted, but at the point at which the f% pressure has fallen to a certain extent and the thyristor is fired.

(e)  発明の実施り 以下本発明の実施真につき図に従って説明する。(e) Implementation of the invention The implementation of the present invention will be explained below with reference to the drawings.

第3図は本発明の実施例のコンテンサ入力形整流紹路の
回路図、[4図は第3図の場合の波形のタイムチャート
で、入出力電圧、@は整流回路への入力交流電流である
Figure 3 is a circuit diagram of a capacitor input type rectifier introduction path according to an embodiment of the present invention, [Figure 4 is a time chart of waveforms in the case of Figure 3, where the input/output voltage is input and @ is the input AC current to the rectifier circuit. be.

図中第1図と同一機能のものは一一記号で示−f0C1
′は平滑コンデンサ、■o′は出方i王で負荷1の両港
の電圧、Ii口′に整流回路−\の入力交流電流、D、
fiダイオード、ZD、はツェナダイオード、SCa、
はサイリスタ、R,、R,、R,は抵抗で、R8は電流
抑制用であり、R8はツェナダイオード保護用であり、
R1はツェナダイオード漏れ電流対策用である。2 、
2’i−を出力端子、V”(lfl平滑コンテンサの両
港の電圧を示す。
Items with the same functions as those in Figure 1 are indicated by the symbol -f0C1.
' is the smoothing capacitor, ■o' is the voltage at both ports of load 1 at the output I, the input AC current of the rectifier circuit -\ is at the Ii port, D,
fi diode, ZD, is Zener diode, SCa,
is a thyristor, R,, R,, R, is a resistor, R8 is for current suppression, R8 is for Zener diode protection,
R1 is for countermeasure against Zener diode leakage current. 2,
2'i- is the output terminal, and V'' (lfl indicates the voltage at both ports of the smoothing capacitor.

入力される交流はブリッチ形整i器RC1にて両am流
され、次段の回路に供給ばれる。サイリスタSCR,が
オフの時には、平滑コンデンサC,/はダイオードDI
を通してa′点から入力電圧のピーク1通になる迄光t
される。商用交流電源Eはサイン波である〃、ら、ピー
ク値に達した後低下していく。
The input alternating current is passed through the bridge shape rectifier RC1 and supplied to the next stage circuit. When the thyristor SCR, is off, the smoothing capacitor C,/ is the diode DI.
light t until one peak of input voltage is reached from point a' through
be done. The commercial AC power source E is a sine wave, which decreases after reaching its peak value.

それにつれて出力電圧V、/も同様に低下してゆくが、
出力電圧■、′と平滑コンデンサの両港の電圧VC+と
の電位差が、ツェナダイオードZD、のツェナ電圧を越
えると(b/点)、ツェナダイオードZD。
As the output voltage V, / also decreases,
When the potential difference between the output voltages ``,'' and the voltage VC+ at both ports of the smoothing capacitor exceeds the zener voltage of the zener diode ZD (point b), the zener diode ZD.

が導通し5、サイリスタSCR,が点弧し、オンとなる
。このため−+嘴コンデンサC1′が出力端子2に接続
はね、出力電圧v、′は平滑コンデンサC1′の放電に
より維持される。入力電圧が再び上昇して、平滑コンデ
ンサC1′の放電している電圧より萬くなると(01′
声)、ツイリスタSCR,は逆バイアスでれて、消弧し
てオフとなる。
becomes conductive 5, and the thyristor SCR is fired and turned on. Therefore, the -+beak capacitor C1' is not connected to the output terminal 2, and the output voltage v,' is maintained by discharging the smoothing capacitor C1'. When the input voltage rises again and becomes lower than the voltage at which the smoothing capacitor C1' is being discharged (01'
The Twiristor SCR is reverse biased, extinguished and turned off.

このようK 本発明の回路では、平滑コンデンサC,l
を、Lj−t’らく、ピーク電圧のままにしておき、短
い時間放電場せるため、従来の回路に比べ、PIじリン
プル電圧にし次場合、平滑コンデンサC,1の容量を減
らすことが出来る。(50サイクルの場合で約1/2位
に出来る。)従って整流装置としては、容量が大きい場
合は、他の素子を追加(7ても小形化することが出来る
。又交流人力電[Iin’ば、平滑コンデンサC1′を
充電するピーク値は、はぼ平滑コンデンサの容量比で小
さくなるので、大巾に小場くなる。電流がほぼOVCな
る期間(第2図b′C′間)ill平滑コンデンサC8
′の放電区間であるので翅くなり、力率を従来のものエ
リよくすることが出来る。
In the circuit of the present invention, the smoothing capacitors C, l
Since Lj-t' is easily left at the peak voltage and discharged for a short time, the capacitance of the smoothing capacitor C,1 can be reduced compared to the conventional circuit when the ripple voltage is set to the same value as PI. (In the case of 50 cycles, it can be reduced to about 1/2.) Therefore, if the rectifier has a large capacity, other elements can be added (even 7 can be made smaller. For example, the peak value for charging the smoothing capacitor C1' becomes smaller due to the capacitance ratio of the smoothing capacitor, so it becomes much smaller. Smoothing capacitor C8
Since it is a discharge section of

第5図に本発明の別の実施例のコンデンサ入力形11回
路で、センタタッグ形の場合の回路図である。
FIG. 5 is a circuit diagram of a center tag type 11 capacitor input type circuit according to another embodiment of the present invention.

図中第3図と同一機能のものは同一記号で示す。Components in the figure that have the same functions as those in FIG. 3 are indicated by the same symbols.

Tは変圧器、D、、D、は歪流器、D1′はダイオード
、Lはチョーク、C、rは平滑コンデンサ、5CFtf
fiはサイリスタ、R4,R,ば抵抗である。
T is a transformer, D, , D are distortion current devices, D1' is a diode, L is a choke, C and r are smoothing capacitors, 5CFtf
fi is a thyristor, and R4, R, is a resistor.

第5図の回路に戻圧器Tを用い、センタタッグ形Ift
とじ念場合である。又第3図の場合のツェナダイオード
ZD、のかわりに抵抗R,、R,の分圧でサイリスタ8
(JL、を点弧させるようにしている3、又抵抗R1の
がわりにチョークLを用いている告でチョークにしても
差支えない。主の動作は第3図の場1と同様である。尚
このチョークL及び第39の抵抗R,は、サイリスタS
CR,SC電がサージを流に対する耐量が充分ある状態
では必要としない。
Using the pressure return device T in the circuit shown in Fig. 5, the center tag type Ift
This is a serious matter. Also, instead of the Zener diode ZD in the case of Fig. 3, the thyristor 8 is
(JL is used to ignite 3, or a choke L is used instead of resistor R1. The main operation is the same as in case 1 of Fig. 3.) This choke L and the 39th resistor R, are the thyristor S
CR and SC electric currents do not require surges when they have sufficient resistance to current.

このツェナダイオードを用いず抵抗で分圧すること及び
チョークLを用いることは第3図のブリソチ形整流形の
場合にも勿論適用出来る。
Of course, dividing the voltage using resistors without using a Zener diode and using a choke L can also be applied to the Brissoti rectification type shown in FIG.

(f)  発明の効果 以上鮮細に説明し念如く、本発明によれば、平滑コンデ
ンサを犬山に小さく出来、整流装置の移置が大きい場合
に装置の小形化が可能となり、又力率を同上出来る効果
がある。
(f) Effects of the Invention To explain more clearly, according to the present invention, the smoothing capacitor can be made extremely small, the rectifier can be downsized even if the rectifier has to be moved a lot, and the power factor can be reduced. It has the same effect as above.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図に従来伯」のコンデンサ入力形整流回路の回路図
、第2図は第1図の場合の波形のタイムチャート、第3
図に本発明の実施例のコンデンサ入力形整流回路の回路
図、第4図に第3図の場合の波形のタイムチャート、第
5図に本発明の実施例のコンテンサ入力形J1流回路で
、センタタップ形の一合の回路図である。 図中Eta商用交流IM、RC,にブリノナ形整流器、
D、、 D、il整流器、C+ 、C、’ 、 c、 
y n平滑コンデンサ、1は負荷、2,2′は出方端子
、D、、D、’はダイオード、R,〜R,U抵抗、SC
R,、SCR,iJサイリスタ、zDIはツェナダイオ
ード、V、、V。′に出力電圧、Iin、Iin’は人
力交流電流を示す。 代理人 弁理士  松 岡 宏四部゛ソ1−1  、”
−j 彎鴎; 晃1 図 第2図 層間 晃5図 亮4図 口1間
Figure 1 is a circuit diagram of a conventional capacitor input type rectifier circuit, Figure 2 is a time chart of waveforms in the case of Figure 1, and Figure 3 is a circuit diagram of a conventional capacitor input type rectifier circuit.
Figure 4 shows a circuit diagram of a capacitor input type rectifier circuit according to an embodiment of the present invention, Figure 4 shows a time chart of waveforms in the case of Figure 3, and Figure 5 shows a capacitor input type J1 flow circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a center-tap type unit. In the figure, Eta commercial AC IM, RC, Brinona type rectifier,
D,, D,il rectifier,C+,C,',c,
y n smoothing capacitor, 1 is load, 2, 2' are output terminals, D,, D,' are diodes, R, ~R, U resistance, SC
R,,SCR,iJ thyristor,zDI is Zener diode,V,,V. ' indicates the output voltage, and Iin and Iin' indicate the human-powered alternating current. Agent: Patent Attorney Hiroshi Matsuoka 1-1
-j Kōō; Akira 1 Figure 2 Hirama Akira 5 Figure Ryo 4 Figure 1 mouth

Claims (1)

【特許請求の範囲】[Claims] コンデンサ入力形整流回路において、商用交流入力を両
af波した回路に、ダイオードを介して平滑コンデンサ
を並列に接続し、該平滑コンデンサと該ダイオードの接
続点を、サイリスタを介し出力増に接続し、該サイリス
タのゲートを該平滑コンデンサの電圧と出力端の電圧と
の差によって点孤させることを特徴とする整流回路。
In a capacitor input type rectifier circuit, a smoothing capacitor is connected in parallel via a diode to a circuit that receives both AF waves from a commercial AC input, and a connection point between the smoothing capacitor and the diode is connected to an output increaser via a thyristor. A rectifier circuit characterized in that the gate of the thyristor is ignited by the difference between the voltage of the smoothing capacitor and the voltage of the output terminal.
JP4225082A 1982-03-17 1982-03-17 Rectifying circuit Pending JPS58159669A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4225082A JPS58159669A (en) 1982-03-17 1982-03-17 Rectifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4225082A JPS58159669A (en) 1982-03-17 1982-03-17 Rectifying circuit

Publications (1)

Publication Number Publication Date
JPS58159669A true JPS58159669A (en) 1983-09-22

Family

ID=12630774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4225082A Pending JPS58159669A (en) 1982-03-17 1982-03-17 Rectifying circuit

Country Status (1)

Country Link
JP (1) JPS58159669A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118358A (en) * 1984-07-05 1986-01-27 Matsushita Electric Ind Co Ltd Dc power source

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118358A (en) * 1984-07-05 1986-01-27 Matsushita Electric Ind Co Ltd Dc power source

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