JPS58159284A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To improve the hit rate of a buffer memory, by suppressing the algorithm of block replacement according to the specified system of the buffer memory to information having low locality and taking the specific block only for the replacement. CONSTITUTION:The specific mode is set in response to a program having low locality and an FF404 of an access control circuit 4 is set. When a -Q output goes to a low level, an AND gate 408 is closed and the output is always 0. This output accesses a specific block of a buffer memory 7, and a designation instruction of a block by an LRU algorithm makng a block not referenced for the longest time from a replacement bit section 203 via the gate 408 as an objective, is not impressed to a memory 7, the block replacement by the LRU algorithm is suppressed and the specific block only is an objective to the replacement. As a result, the hit rate of the buffer memory is improved.

Description

[Detailed Description of the Invention] +The invention relates to a buffer memo IJfcooke/)i'1JII system of an IS information processing device, and more specifically, a system for controlling the suppression of registration in a buffer memory. Regarding T6゜1H information processing device 1, the central processing unit has 16 KB ~
Compared to the 321J Stock Counterfeit King memory device, the small d-year has a buffer memory with multiple 0's (cage memory and ('
By preparing L 6 ), effectively
I know that the reaccess time can be made faster.

This takes advantage of the fact that programs executed in the information processing device fl 114 generally have a property called locality of memory access.

That is, over a relatively short period of time, there is a tendency for a specific limited area of the program to be accessed intensively, and furthermore, addresses in the vicinity of once accessed ζ
There is a strong tendency for this access to be concentrated at T6.

Therefore, prepare a relatively small capacity buffer and use it as main A.
Accessing the memory - At this time, the program of multiple swords including the accessed data is taken into the buffer memory.

At this time, if the panfame is already at least 7 full, leave the professional who has been accessing for the longest time, leave the buffer, 0), and request a request here. Control is performed to capture ivy. As a result, for subsequent accesses, it is possible to reduce the probability that the necessary information (or buffer memory) exists, and most of the accesses to the memory can be done by accessing this buffer, which is slow. This reduces the number of times the TD information processing device accesses the above 7. and general programs that are not referenced for the longest time. It is known that the so-called LRU method, in which blocks that have been stored are removed from the buffer memory card, is effective, and the LHtJ method is usually used in general t# information processing devices.

However, in certain programs.

As mentioned above, there are programs with extremely low locality, and when a program like this is executed, accesses are made over a wide range of addresses, and the same address is repeatedly accessed. , J.C.! : Or less. If you run such a program and use buffer memory, the blocks loaded onto the buffer memory will rarely be used.71>7
1) Regardless, many t4-minutes of the buffer ameri are in this block's i! Due to the information on the e river, the substitutes are in trouble, and the P3 valley of 7 years ago is destroyed, and when another program opens P+ - c, etf, this is the case. It has been concluded that it is necessary to import information into the Noγ Mesori,
This causes the performance of the information processing device to decrease (V).

The present invention provides a buffer for information with low ptlJ compatibility.

L) LU method of buffer memory Suppresses the algorithm of block replacement caused by block replacement, and prevents the internal use of many parts of buffer memory so that only specific professionals and people are concerned about it. This is an attempt to preserve the .

In contrast to the program with low local unidirectionality,
Even with a platform that targets a specific block 0)^ for replacement,
Bakufame seven days in this program.

(Well, compared to the case where LLEU method C is used for all blocks, the rate is 0.7j higher.

On the other hand, as mentioned in s t311, the other parts of 1 koba 7 fame 7 ri have been preserved, and h6PA
What is the problem with low quality programs?
The probability that the information for other programs that are opened is saved is also increased, since the buffer memory as a body is less likely to be saved (which also reduces the rate of failure), and therefore the child's head of household.
The jt value access time is also linked to the information processing device (/J
Same as above.

The present invention (with regard to the replacement control of blocks in the buffer memory, a limited mode in which replacement is performed only for the block position of the replacement, and a normal mode in which replacement is performed using the LRtl method, and the buffer memory control mode is set to the limited mode. - a means to release from the buffer memory and a means to update and manage the replacement information according to the usage situation, When replacing a block, if the s R'l is not in the limited mode, it should be replaced. Pro, interpret the evening, separate buff memory 7M1J both modes or limited mode 1, P) If (well, the said replacement information is suppressed, unique)
J Place the block L, select I and select 'Cs % main memory block
C and Mekomari 1st station 19r sex υ) The low program's ★ stroke is divided by 1. Well, this fire--2 t stands,
By setting the specific code and canceling this mode when execution is completed, it is possible to prevent a specific block of buffer memory from being used when executing a process with low locality. This makes it possible to prevent the information on the buffer memory from being destroyed by processing with low locality without significantly lowering the hit rate on the buffer memory. Therefore,
This can reduce the hit rate in the buffer memory as a whole.

Therefore, the object of the invention is to provide a buffer memory method that can achieve a high hit rate as a whole, and to provide a buffer memory method that correlates effective main memory access time. The purpose of the present invention is to provide a buffer memory control method that realizes an information processing device with high performance.

FIG. 1 is a block diagram showing an embodiment of a device embodying the inventive buffer memory system.

Originally, nine examples were given.
The buffer memory is assumed to consist of M words (IM=2"), and the main memory address is 24 bits. The buffer memory has a capacity of 4 words, 1 block is 8 words, and has a configuration of 256 sets x 2 compartments.

Correspondingly, the 24-bit main memory address register l consists of 24 bits, including an in-block word address of 3 bits from the lowest, a set address of 101.8 bits, and a block address part 10 of 13 bits.
There are three powers and one power.

Baranoa memory 8E search table 2 has 256 entries, corresponding to 256 sets of BA, FAME, 7,
The bone entry has two corresponding compartments, first and second block address fields 201 and 202J, and a replacement bit 203 for indicating information regarding the number of accesses of the valley compartment.

The outputs of the first and second block address sections 201 and 202 (are marked 0 in the first and second comparison circuits 301 and 302. The main memory address register l
The first and second block addresses $201.2021 of the block address section 103 are applied to the first and second comparator circuits 301.302 and 5t42, respectively.
The input of the pond also has +4J, Utl. Coincidence detection signals 303 and 304 of the first and second comparison circuits are applied to the access control unit 4, and depending on the output of this comparison circuit, access to appropriate blocks of the buffer and access from the main memory are controlled. Transferring blocks to the buffer, updating replacement bits, etc. will be performed.

The output of the replacement bit capital 203 of the buffer memory search table 2 is output to the access city IJ9i 41 section as 0.
In addition, the replacement information 409 generated in the access city 111141 and the city 4 is applied to the times bit 203i of the buffer memory search table 2.

The upper memory scissors 5 uses the 24-bit address of the main memory address register l according to the command in the 7' access control part L6, or uses the upper 21 bits of the main memory address and the γ access 'rblJ m m 4 generated by 2, accessed using the Rinouchi wordat[/s402,
Data output and oath 6 are performed via the customary data register 6.

The buffer memory 7 has a word valley t at 4, and the replacement information 401 . 1st shift of main memory address register set address @102 and access control unit 4
In response to the command in the 3-bit main address register, the word address field 101 of the 3-bit main address register 1fL/: or the value 4 (12) generated by the access control unit 4 is applied.

The value of the main 6 self-memory theme register 6 is applied as the manual data of the buffer T-mechanical register 7, and the output j-e is applied to the memory data register 8. 1 completed,
Memo IJ 7'-tare register 8 contains the king device, M-f
The value of the '-data register 6 and the * data from the processor are also applied (not shown).

The access control unit 4 is provided with a mode flip-flop 104 for holding a control mote of a 6-buffer memory, and when it has [1, it indicates a traction mode. (not shown in Figure 7), it is possible to set, reset, and set/reset the microprogram for specific fields by No. 16-405°406 A reset is performed.

The auxiliary output of the 7-d flip 1 knob 404 is applied to one input of the AND gate 408LJJ, and the output of the replacement bit section 203 of the buffer memory search table 2 is applied to the other input of the AND gate 408. The output of the AND gate 408 is applied to the buffer memory 7 as part of the address (compartment address).

I will explain the action in Honkyousega to the arrow.

When a memory access request is made, the main memory address to be accessed is sectored into the memory address register l.

Next, the set address part of this address (from this, the Panzer memory weft table 2 is successively outputted. As a result, when either the first or second ratio soft circuit detects a match, the access control circuit 4 A match is made, apply this as the compartment address to the signal!!!401, and apply this and the memory address register's cell address 102%.
When the buffer memory is accessed using the word address 101 in the block, the comparison time 1NrI for which no match was detected at this time is generated as the corresponding 111'E replacement information, and the replacement bit 5203 of the buffer memory search table 2 is generated. Ends the end month commitment process corresponding to the set address.

This γ7. Therefore, if a match is found on the other hand (by the power of the comparator circuit), that is, if there is a corresponding TΦ front on the buffer memory, then access to the corresponding block on the buffer memory is performed. In addition, the replacement bit of the buffer memory search table 2 is set to ν1 so that it always specifies the compartment that has not been accessed for a long time.

If neither of the comparator circuits 301 and 302 of Mourning 1 stone Yohi porridge 2 detects a match, that is, if there is no block on the buffer memory that includes the word to which access is requested, then the necessary block is selected. The next operation is performed to fetch the buffer memo from the main memory.

That is, the compartment address for the buffer memory is 11 when the buffer memory control mode is the normal mode, the mode flip-flop 404 has the value 0, and the control signal 407 has the value 1, so it is applied to the buffer memory. As the compartment address 401, the first shift of the replacement part 203 successively retrieved from the buffer memory search table 2 is the AND time I4.
08 force) is output.

If the buffer memory control mode is limited mode,
Since the mode flip-flop 404ft (1 [1) is applied and the control signal 40 right side 1 or 1 right side 0 is applied, the AND circuit 408 selects ft1o regardless of the value of the replacement bit section of the buffer memory search table 2. The output of the AND circuit 408, which will be output from X, is applied to the buffer memory 7 as part of the address signal.

As a result, in the limited mode, the number is unconditionally set to 0 in the compartment address of the buffer memory, and in the normal mode, the number is set to 0 for replacement.

The buffer memory compartment specified by the default will be selected for replacement.

Main S [] 1 in block of unique device and buffer memory
The output 402 of the word counter of the access control unit 4 is used as the node address.
03's 1st shift from 0 to 7 for 11 days.
However, I created the main memory 5 about Tani I, and a series of data appeared.
The value is then set in the self-memory data register 6, and this value is written into the buffer memory 7#. After this process is completed, the buffer memory search table 2 is searched.

The block address field k of the upper storage address register l is assigned to the block address field specified by the value successively output from the block address field 2o1 of the l-th or wJ2, or the replacement bit of 202 (203). Thereafter, the matching detection process is performed by the comparison circuit described above. In this case, since the corresponding block f has already been stored in the compartment iL specified by the replacement bit, the comparison circuit detects a match and accesses the buffer memory.

Next, the second real m-reli of the present invention will be explained.

In this embodiment, a mechanical candy command for music is provided at 6f to set or release the buffer *1 Jo141 mode to the limited mode, and when this particular line segment is lit, the access control unit mode is set. When this mode is set to limited mode, the operation when set to normal mode is the same as in the first embodiment.

I have explained the present invention in detail above, but
As described in Moku Nariaki and Akira ρ), the gist of the present invention is to create a creation mode (Kumaashi Mort') in which only a specific block position of the buffer memory is targeted for replacement. : Setting, canceling, and replacement depending on how the buffer memory is accessed. (In normal mode 3, the block belonging to the compartment that is designated as having not been accessed for the longest time in the replacement information 1) is replaced; in limited mode ζ, the block is replaced. By providing a control means for replacing blocks belonging to a specific compartment, regardless of the information, it is possible to replace only a specific block location in the buffer memory in the limited mode. This makes it possible to prevent many parts of the buffer from being replaced when programs with low locality are executed. .

Therefore, some modifications are possible as long as they do not violate the spirit of non-invention as stated above, for example, Honmeishi 171J
It is obvious that the number of buffer memories, number of compartments, block size, etc., or main memory size, etc., can be set to other arbitrary values; for example, if the number of compartments is large, At the field batting,
As a replacement ↑pt@ requires multiple bits, the logic for tracking replacement information or detecting a compartment that has not been accessed for a long time is also complicated depending on the number of compartments. It will become something.

In addition, in this embodiment: Well, buffer memory search l
Although the above description assumes that a virtual address is used, it is also possible to perform a search using a virtual address, as is known in the art.

In addition, in this embodiment, a specific method for realizing the access control unit will be described except for a part that is strongly related to the gist of the present invention. It goes without saying that the characteristics of the self-storage device and buffer memory are easily created based on the conventionally known IL technology.

First, explanation of this embodiment will be given regarding the timing of setting the buffer control mode to the limited mode (although it is not mentioned here, for example, when a specific regulation such as a regulation for transferring large amounts of data) is set. T controls what happens to this instruction except for execution.
This field can be used to set or release a limited rectangle code in a micro sequence, or to write a dllil structure (this is called a procedure descriptor) that describes a 1% fixed procedure. , when executing this procedure, the buffer memory should be controlled in limited mode. 8 - Provide an unspecified field to execute the procedure's call instruction. procedure n
If you refer to this field of the self-link and want to use the limited mode, set the access control mode to the limited mode and return to the limited mode. The setting of this mode will be set in the micro-instruction when the B1 call instruction is sent to the platform where the hardware is used to perform the Glossary era.

Also, if you are using an information processing device that does not check the procedure descriptor by hardware (or check the above-mentioned panzer memory control mode field of the procedure descriptor by software).

If you are in a state of limited mode, you can use Baranoa memory in limited mode when a special procedure person comes to the company by executing a special command to meditate in limited mode. It is possible to do so.

[Brief explanation of the drawing]

The figure is a block diagram showing a concrete version of the buffer memory system of the present invention. In the figure, 1 is a memory address register, 2 is a buffer memory woof thread, and 301 and 302 are first and second comparison circuits. 4 (access IIyIJ-house, 5 is the upper memory, 6 is the main memory data register, 7 is the buffer memory, 8 is the lower memory data register.

Claims (1)

[Claims] 1. In a buffer memory of an information processing device, a means for setting and canceling a specific mode related to replacement control of the software on the computer, and an exception for accessing information in the buffer memory. A means for managing replacement information according to how access is performed in C1 Pro, β checking whether the specific 9 mode is set when running a race in a buffer anomaly, If a specific mode is not set, ^US
Based on the replacement information stored in the self-update management program, the block to be replaced is determined, and if the previous ml specific mode is set, regardless of the replacement information that is buried, 1. A buffer memory control method, comprising a control means for next resuming a specific block as a block to be replaced and fetching the block from the main memory. 2. 14+1 The buffer memory control system according to claim 1, wherein the means for setting and canceling a specific mode for controlling blocks on the distributed buffer memory has a machine language instruction.