JPS58158936A - External lead detector of semiconductor device - Google Patents

External lead detector of semiconductor device

Info

Publication number
JPS58158936A
JPS58158936A JP57041070A JP4107082A JPS58158936A JP S58158936 A JPS58158936 A JP S58158936A JP 57041070 A JP57041070 A JP 57041070A JP 4107082 A JP4107082 A JP 4107082A JP S58158936 A JPS58158936 A JP S58158936A
Authority
JP
Japan
Prior art keywords
lead
reference mark
semiconductor device
leads
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57041070A
Other languages
Japanese (ja)
Inventor
Kenichi Igarashi
賢一 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57041070A priority Critical patent/JPS58158936A/en
Publication of JPS58158936A publication Critical patent/JPS58158936A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1016Shape being a cuboid
    • H01L2924/10162Shape being a cuboid with a square active surface

Abstract

PURPOSE:To perform automatic wire connection of multiple external lead terminals by a method wherein the position of individual external lead patterns is detected as a relative position to a reference mark. CONSTITUTION:A device 5 is scanned by a TV camera 8 on table 6 for making into specimens the image elements of N-N and converting them into binary values 9 for memory 10. Firstly, the regions 160, 161 are scanned to detect 12 the central position of the reference marks 150, 151, further scanning the lead position based upon the coordinates system in the order of the sections 162, 163... slightly overlapped one upon another. When the memory 10 is read out by the address control unit 11, the read out direction is selected in accordance with the array of leads to detect 13 all leads by means of repeating the same process. That is, the data in the image memory 10 are read out by raster scanning process determining the center coordinates of the leads from the center of transient position to decide the firstly vanishing position as the lead terminal. Then the detected position is memorized 14. Through this constitution, the automatic wire connection may be performed very accurately by means of adding lead terminals to a wire connecting device with multiple pins.

Description

【発明の詳細な説明】 本発明は、半導体装置例えばセラミックケースに搭載さ
れ友超高集積回路(以下VL8 Iと記す)の組立に関
するものであり、4IK多数の外部リード端子を備えた
VLSIのワイヤボンディングを自動化する装置Kmす
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the assembly of semiconductor devices, such as ultra-high integrated circuits (hereinafter referred to as VL8 I) mounted in a ceramic case, and includes VLSI wires equipped with a large number of 4IK external lead terminals. This is a device that automates bonding.

半導体装置の中で4hVL8Iと称される集積回路(以
下率KICと記す)は、メモリなど一部のものを除き外
部リード端子の数が大4Iに増加する傾向、すなわち多
ビン化の傾向にある。
Among semiconductor devices, integrated circuits called 4hVL8I (hereinafter referred to as KIC) have a tendency to increase the number of external lead terminals to 4I, that is, to increase the number of bins, except for some devices such as memory. .

これは1個のIC当りに集積されるゲート数が増加する
ことから必然的に導出されるものであP m 3.5 
X G”’ ここでPはピン数すなわち外部リード端子数、Gはダー
ト数を表わす。このよ51CVL81は高集積化される
に伴って、外部端子となるリード数も犬−に増加してく
る。
This is inevitably derived from the increase in the number of gates integrated into one IC, and P m 3.5
X G"' Here, P represents the number of pins, that is, the number of external lead terminals, and G represents the number of darts.As the 51CVL81 becomes more highly integrated, the number of leads that serve as external terminals also increases exponentially. .

ところが電子回路の遅延時間増加な招くため、単にケー
スを大型化することは望ましくなく、半導体装置のケー
スに形成されるワイヤ汐ボンディング用のリード幅とそ
の配列間隔は小さくならざるを得ない。
However, simply increasing the size of the case is not desirable because it increases the delay time of the electronic circuit, and the width of the leads for wire bonding formed in the case of the semiconductor device and the arrangement interval thereof have to be reduced.

半導体装置に使用されるケース、例えばセラミックケー
スなとでは焼成時の収縮率の微妙な差異などKより、最
終的に形成された個々の外部リードパターンの1位置は
設計上の位置と異なってくる。
In cases used for semiconductor devices, such as ceramic cases, the position of each external lead pattern ultimately formed differs from the designed position due to subtle differences in shrinkage rate during firing. .

さらに、リード幅がj−さくなり、従来の300〜従米
使用されている自動ワイヤボンディング装【6寡、ペレ
ットならびに外部リード上の代表点を各々lないしは2
箇所検出し、自動的に位置ずれを補正しつつボンディン
グな行うものである。
In addition, the lead width has become smaller, and the typical point on the pellet and external lead can be reduced to 1 or 2 liters, respectively.
The bonding method detects the location and automatically corrects the positional deviation while bonding.

この場合、IC上に形成された電極配列パター/のよう
にワイヤボンディング工程時にも正確に相互関係の出て
いるものおよび外部リード幅に余裕のあるものは十分実
用的である。
In this case, it is sufficiently practical to have an electrode array pattern formed on an IC that has accurate mutual relationships during the wire bonding process and has a sufficient external lead width.

しかし、先に述べたよ5にこうした多ビンの半導体装置
では、外部リードパターン相互間の位置にばらつきが生
じ、かつリード幅が小さいため、上記の装置および方法
で自動ボンディングを行うことは極めて困−であり、歩
留りの大幅な低下を招く。
However, as mentioned above, in such a multi-bin semiconductor device, the positions of external lead patterns vary and the lead width is small, so it is extremely difficult to perform automatic bonding using the above-mentioned apparatus and method. This results in a significant decrease in yield.

本発明による半導体装置の外部リード検出装置は、かか
る欠点な補う丸め、個々の外部リードパターンの位置を
基準マークとの相対位置として検出するものであり、ワ
イヤボンディング工程においてリード側検出としてこの
基準マークを用いることKより、従来の自動ワイヤボン
ディング装置においても、充分kIIii+精度なボン
ディング作業を行うことを可能とするものである。ここ
で本発明による半導体装置の外部リード検出装置は、従
来のワイヤボンディング装置においてボンディング用ス
テージの前段に付加することも可能であり、またワイヤ
ボンディング装置とは別の単独装置として構成し、リー
ド位置のみ記憶媒体を用いて供給することも可能である
The external lead detection device for a semiconductor device according to the present invention compensates for such drawbacks by rounding and detects the position of each external lead pattern as a relative position with respect to a reference mark. By using K, it is possible to perform bonding work with sufficient kIII+ precision even in a conventional automatic wire bonding apparatus. Here, the external lead detection device for a semiconductor device according to the present invention can be added to the front stage of the bonding stage in a conventional wire bonding device, or can be configured as an independent device separate from the wire bonding device to detect the lead position. It is also possible to supply only the information using a storage medium.

以下図面を用いて本発明による半導体装置の外部リード
検員振紘の実施例を詳MK説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an external lead inspector for a semiconductor device according to the present invention will be described in detail below with reference to the drawings.

第1図は本発明の対象となる半導体装置のセラミックケ
ースの外観図の一例であり、半導体装置ケース1に半導
体素子4IkVLS I 2が固着されている。半導体
装置のケースIKは、外部リード3および基準マーク4
が形成されている。一般にVLSIj裏多ビン化すると
ケースの大きさも太きディングKIj!P賛とされる部
分の大きさだけでも約10m角になる。このため全リー
ドの画像を一括入力し必要な精度を確保するためkは1
0000 X 10000以上の橡本化点′にもつ画像
として入力する必要があり、実用上かなり困難である。
FIG. 1 is an example of an external view of a ceramic case of a semiconductor device to which the present invention is applied, and a semiconductor element 4IkVLS I 2 is fixed to the semiconductor device case 1. The case IK of the semiconductor device has external leads 3 and reference marks 4.
is formed. In general, when VLSIj has multiple bins on the back, the case size also becomes thicker! The size of the portion designated as P-san is approximately 10 meters square. For this reason, in order to input images of all leads at once and ensure the necessary accuracy, k is 1.
It is necessary to input the image as an image having a 0,000 x 10,000 or more Emoto conversion point, which is quite difficult in practice.

従って、充電変換用のTVカメラ#txyテーブルに搭
載し、小領域に分割して順次走査していき各^の小領域
すなわち一画面に含まれるリードを検出することが実用
上有効な方法となる。
Therefore, a practically effective method is to install the TV camera #txy table for charging conversion, divide it into small areas, sequentially scan them, and detect the leads included in each small area, that is, one screen. .

第2WJは本発明による半導体装置の外部リード検出装
置の構成例を示す図で、ケース外形を用いて概略の位置
決めがなされ九牛導体装@Sのij歇をXYテーブル6
に搭載されたTVカメラ8を用いて順次走査して行く。
The second WJ is a diagram showing a configuration example of an external lead detection device for a semiconductor device according to the present invention.
The images are sequentially scanned using a TV camera 8 mounted on the camera.

TVカメ?8により入力されたー葎値号はNXN10画
素に標本化され2値化囲路9を用いて白黒すなわち“1
′と0”の2値−像に変換される。この2値傷楯像は、
NXNの大きさをもつ一儂メモリ10′に格納される。
TV camera? 8 is sampled into NXN10 pixels and converted into black and white, that is, "1" using the binarization circuit 9.
It is converted into a binary image of ' and 0''. This binary scratch image is
It is stored in a one-time memory 10' having a size of NXN.

一画面分のデータがij像メモ910に格納されると、
XYテーブル制御部7により次の走査位置が指令されX
Yテーブル6すなわちTVカメラ8は移動を開始する。
When one screen worth of data is stored in the ij image memo 910,
The next scanning position is commanded by the XY table control unit 7 and
The Y table 6, that is, the TV camera 8 starts moving.

ml像メモ’jlOK格納された2値画像データは、ま
ず菖3図の走査手順K(t−)て基準マーク検出111
2へ転送され、基準マークの中心位置な絖み取る。リー
ド検出のときはアドレス制御mttKよりlli像デー
タの読み出し方向が制御され、リード検出部13により
単一の地理で全リードの検出な行うことが出来る。検出
されたリード位置は基準マークとの相対座IIK変換さ
れ、メモリやカセットテープなどの記憶媒体14へ格納
される。
ml image memo
2, and the center position of the reference mark is removed. At the time of lead detection, the reading direction of the lli image data is controlled by the address control mttK, and the lead detection section 13 can detect all the leads in a single geographical area. The detected lead position is converted into a relative position IIK with respect to the reference mark, and is stored in a storage medium 14 such as a memory or a cassette tape.

ji3#Aは、基準マークおよびリード検出時の走査手
順の一例を示すものであり、まず、基準マーク150.
151の2ケ所の領域160.161を走査して基準マ
ーク150.151の中心位Mk第2図に示す基準マー
ク検出部12により検出する。しかる後、基準マークの
座標系に基づい【リード位置を反時針方向k 162.
16Bのように多少オーバラップさせながらリード存奔
領域全体を職次走査して行く。このオーバラップは一面
縁にかかるリードを誤りなく判定するためのものである
ji3#A shows an example of a scanning procedure when detecting a reference mark and a lead. First, the reference mark 150.
Two areas 160 and 161 of reference mark 151 are scanned to detect the center position Mk of reference mark 150 and 151 by reference mark detection unit 12 shown in FIG. After that, based on the coordinate system of the reference mark, change the read position in the counterclockwise direction k162.
As shown in 16B, the entire lead existing area is sequentially scanned with some overlap. This overlap is for determining a lead that spans one edge without error.

第3図に示される基準マーク150.151は、ワイヤ
ポンディング工程においてリード側の基準となるもので
あり、形状は特徴的であれば任意で良い。
The reference marks 150 and 151 shown in FIG. 3 serve as references on the lead side in the wire bonding process, and may have any shape as long as they are characteristic.

第4図では、十形状を例にとり、基準マークの検出方法
の一例を示す。すなわち十形基準マーク15に対し【、
これ19着干小さいレチクル11発生させ、レチクル1
7を一定幅のパターンが4方向とも横断し、かつ鵬中町
、町s”ap町で示される4つの量が一敦するレチクル
の中心位置な基準マークの中心位置とするものであり、
こ5した錫層な実現する回路は現状の技術で容易に鯛達
できるためここでは詳述しない。
FIG. 4 shows an example of a method for detecting a reference mark, taking a ten-shape as an example. In other words, for the ten-shaped reference mark 15 [,
This generates 19 small reticle 11, reticle 1
7 is the center position of the reference mark, which is the center position of the reticle where a pattern of a constant width crosses all four directions, and where the four quantities indicated by Hōnaka-machi and Machi s”ap-machi are the same,
The circuit for realizing this tin layer can be easily achieved using the current technology, so it will not be described in detail here.

第5図は、リード検出時[111’となるアドレス制n
il m 11の機能を示す図であり、2値#轍データ
な第2図に示す検出部1341C転送するのに4つのモ
ードを実現する。すなわちNXN画素をもつ第21dK
示す画像メモリlOのデータを読み出す場合、上側リー
ド加を走査中は$S図邊)に示すごとく、−像データの
左から右かつ上から下の順序で、すなわち181.18
2.183の順序で第2図に示すリード検出部13へ転
送する。flil様に、第5図(blは左側リードムの
場合に用いられ、184.185.186の順序で転送
することを示し、第5図101は下側リード四の場合で
187.188.189の順序、第5図(旬は右側リー
ドnの場合で190.191.192の験序でリード検
出部13へ転送することを示す。
Figure 5 shows the address system n that becomes [111' when a read is detected.
2 is a diagram showing the functions of the il m 11, which realizes four modes for transferring binary #rut data to the detection unit 1341C shown in FIG. 2. That is, the 21st dK with NXN pixels
When reading the data of the image memory IO shown in FIG.
2. It is transferred to the lead detection unit 13 shown in FIG. 2 in the order of 183. flil, Fig. 5 (bl is used in the case of the left lead dome and indicates that it is transferred in the order of 184.185.186, and Fig. 5 101 is used in the case of the lower lead 4 and indicates the order of 187.188.189. Order, FIG. 5 shows that in the case of right lead n, the order is transferred to the lead detection unit 13 with the order of 190.191.192.

上記rドレス制御811により、リード検出11113
では悪す図四の場合と全く同一の処理で半導体装置ケー
スの全ての方向に関してリードの検出が可能である。ま
た、この場合機械的KTVカメ2を回転するのと異なり
、これに伴5M度の劣化は見られない。
Lead detection 11113 is performed by the above r address control 811.
In this case, it is possible to detect leads in all directions of the semiconductor device case using exactly the same process as in the case of FIG. Further, in this case, unlike rotating the mechanical KTV camera 2, no deterioration of 5M degrees is observed.

第6図はリード検出部13におけるリーf検出の方法を
示す図で、画像メモリlOのデータを2スタ一スキヤン
方式で読み出すと、第6図t&l k示す241、24
2.24:l)位数テノ信号は各’l 1161Etb
lK示す251.252.253 K示す如く現われる
。リード位置検出では、vlからへへ変わる点、並びK
 VMから■、へ変わる点すなわちトランジェント位置
の中心を求めることにより、リードの中心座標を求め、
端点は連続するシスターのうち最初に上記トランジェン
トの無くなる位置を求めれば良い。
FIG. 6 is a diagram showing a method of detecting the read f in the read detecting section 13. When data in the image memory IO is read out using the two-star scan method, 241, 24 as shown in FIG.
2.24:l) The order teno signal is each 'l 1161Etb
lK shows 251.252.253 K appears as shown. In lead position detection, the point where vl changes to, the sequence K
By finding the point where VM changes to ■, that is, the center of the transient position, find the center coordinates of the lead,
The end point can be determined by finding the position where the above-mentioned transient disappears first among consecutive sisters.

以上のようにすれば、端点から一定距離すなわちボンデ
ィング位置にあるリードの中心位置を容Jl!に検出す
ることがてきる。
By doing the above, the center position of the lead at a certain distance from the end point, that is, the bonding position, can be adjusted to Jl! can be detected.

以上述べたよ5IIc1本発明による半導体装置の外f
li9−ド検出級置を用いれば、多ビン化する■LSI
の組立作業JICワイヤポンディング作業において、従
来のボンディング装wLK付加的に接続するだけで、充
分必l!槓度な満足する自動化装置が容易に実現できる
As mentioned above, 5IIc1 outside f of the semiconductor device according to the present invention
If you use the li9-code detection class, you can create multi-bin LSI
In assembly work JIC wire bonding work, simply connecting the conventional bonding equipment WLK additionally is sufficient! A highly satisfactory automation device can be easily realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の対象となる半導体装置の外観図、第2
図は本発明による半導体装置の外部リード検出装置の実
施例を示す図、1iia図は走査手順の一例を示す図、
94図は基準V−りの検出方法を説明するための図、#
15図はアドレス制御部の磯膨を説明するための図、第
6図はリード検出方法を説明するための図であり、図中
1は半導体装置のセラミックケース、2は半導体素子、
3゜20 、21 、22 、23は外部リード、4 
、15 、150.151は基準マーク、5は概略の位
置決めがなされた半導体装置、6はXYテーブル、7は
XYテーブル制御部、8はTV右カメラ9は2値化回路
、 l(Jはlii像メモリ、11はアドレス制#部、
校は基準マーク検出部、13はリード検出部、 14は
記憶媒体、160゜161、162.163は走査位置
、17は暴者マーク検出用L/?り4.181.182
.183.184.185.186.187. IW。 189、190.191.192は画像デーpaみ出し
順序、241゜242、243は読み出しラスターおよ
び251.252.253は各々241.242.24
3に対応した銃み出し信号を示している。 t 1図 第3図 第3図 第L−紀 準5図 )9I
FIG. 1 is an external view of a semiconductor device to which the present invention is applied, and FIG.
1 is a diagram showing an embodiment of the external lead detection device for a semiconductor device according to the present invention, FIG. 1iia is a diagram showing an example of a scanning procedure,
Figure 94 is a diagram for explaining the method of detecting the reference voltage, #
FIG. 15 is a diagram for explaining the expansion of the address control section, and FIG. 6 is a diagram for explaining the lead detection method. In the figure, 1 is a ceramic case of a semiconductor device, 2 is a semiconductor element,
3゜20, 21, 22, 23 are external leads, 4
, 15, 150.151 are reference marks, 5 is a semiconductor device roughly positioned, 6 is an XY table, 7 is an XY table control unit, 8 is a TV right camera 9 is a binarization circuit, l (J is lii image memory, 11 is address system # section,
13 is a reference mark detection section, 13 is a lead detection section, 14 is a storage medium, 160° 161, 162.163 are scanning positions, and 17 is a gang mark detection L/? ri4.181.182
.. 183.184.185.186.187. IW. 189, 190.191.192 are the image data pa extraction order, 241°242, 243 are the read raster, and 251.252.253 are each 241.242.24
3 shows a gun ejection signal corresponding to No. 3. t 1 Figure 3 Figure 3 Figure L-Normative Figure 5) 9I

Claims (1)

【特許請求の範囲】 半導体装置の外部リード画像を充電変換するためのTV
右カメラ前記TV右カメラXY平面上に移動させるため
のXYテーブルおよびXYテーブル制御部と、外部リー
ドl1iii像を白黒の2値に変換する2値化回路と、
上記2値ij鍵を記憶するためのlIjgIIメモリと
、2個画像データを走査位置に対応した方向から順次読
み出すためのアドレス制御部と、半導体装置のケースに
形成された基準マークを読み取る基準マーク検出Sおよ
び外部リードを読み堆る外部リード検出部とから構成さ
れ、あらかじめ概略の位置決めがなされた半導体装置の
ケースに形成されている外部リードを前記XYテーブル
に固定された光電変換用カメラで外部リードの存在する
全領域を分割し【順次走査し、各ij像データをアドレ
ス制御MIKよりリード配列に対応した、すなわちTV
右カメラ走査位置に対応した絖み出し方向を選択するこ
とにより同−錫層の繰り返しで各々の領域に存在する各
リード位置を基準マークに対する、相対位置で個々に検
出かつ記憶することを特徴とする半導体装置の外部リー
ド検出錬縦。
[Claims] TV for charging and converting external lead images of semiconductor devices
an XY table and an XY table control unit for moving the TV right camera on the XY plane; a binarization circuit for converting an external lead l1iii image into black and white binary;
An lIjgII memory for storing the above-mentioned binary ij key, an address control unit for sequentially reading out two pieces of image data from the direction corresponding to the scanning position, and a reference mark detection unit for reading the reference mark formed on the case of the semiconductor device. A photoelectric conversion camera fixed to the XY table detects the external leads formed on the case of the semiconductor device, which is roughly positioned in advance. Divide the entire area in which there exists [sequentially scan, and send each ij image data to address control MIK corresponding to the read arrangement, that is, TV
By selecting the lead-out direction corresponding to the right camera scanning position, each lead position existing in each area by repeating the same tin layer is individually detected and stored as a relative position with respect to the reference mark. Vertical detection of external leads of semiconductor devices.
JP57041070A 1982-03-16 1982-03-16 External lead detector of semiconductor device Pending JPS58158936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57041070A JPS58158936A (en) 1982-03-16 1982-03-16 External lead detector of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57041070A JPS58158936A (en) 1982-03-16 1982-03-16 External lead detector of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58158936A true JPS58158936A (en) 1983-09-21

Family

ID=12598181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57041070A Pending JPS58158936A (en) 1982-03-16 1982-03-16 External lead detector of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58158936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60107115A (en) * 1983-11-16 1985-06-12 Amada Co Ltd Control method of work feed device
JPH0642931A (en) * 1992-06-11 1994-02-18 Just:Kk Apparatus for inspecting shape of lead of electronic part

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60107115A (en) * 1983-11-16 1985-06-12 Amada Co Ltd Control method of work feed device
JPH0563806B2 (en) * 1983-11-16 1993-09-13 Amada Co Ltd
JPH0642931A (en) * 1992-06-11 1994-02-18 Just:Kk Apparatus for inspecting shape of lead of electronic part

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