JPS58158927A - Plasma etching method - Google Patents

Plasma etching method

Info

Publication number
JPS58158927A
JPS58158927A JP4105582A JP4105582A JPS58158927A JP S58158927 A JPS58158927 A JP S58158927A JP 4105582 A JP4105582 A JP 4105582A JP 4105582 A JP4105582 A JP 4105582A JP S58158927 A JPS58158927 A JP S58158927A
Authority
JP
Japan
Prior art keywords
etching
silicon film
film
gas
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4105582A
Other languages
Japanese (ja)
Inventor
Shigeki Kato
茂樹 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4105582A priority Critical patent/JPS58158927A/en
Publication of JPS58158927A publication Critical patent/JPS58158927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Abstract

PURPOSE:To enable to perform a microscopic patterning by a method wherein, after a reactive sputter etching has been performed on a P-added polycrystalline Si film in the midway of it by adding O2 in Cl2 gas, an etching is performed using Cl2 gas only. CONSTITUTION:A resist mask 1 is provided on the P-doped polycrystalline Si2 formed on the SiO2 film 3 located on an Si substrate 4, and a reactive ion etching or a paralleled flat plate plasma etching is performed. At this time, the film 2 is removed by etching using CCl4 gas wherein O2 is added, the film thickness of 5-50% or thereabout is obtained, and a film 2'' is obtained by performing an etching using CCl4 gas only. According to this constitution, very small undercuts are not generated on the polycrystalline Si film 2, and a microscopic work can be performed to obtain a desired pattern.

Description

【発明の詳細な説明】 本発明は選択ドライエツチング方法に関する。[Detailed description of the invention] The present invention relates to a selective dry etching method.

塩素系ガスを使用した反応性イオンエツチングまたは平
行平板プラズマエツチングによるシリコン膜たとえば多
結晶シリコン膜のエツチングでは工、アング中に前記多
結晶シリコン膜上に炭素および炭素の化合物およびポリ
マー等が堆積し前記多結晶シリコン族の工豐アングの進
行が阻害されるため、一般に塩素系ガスに酸素を添加し
たガスを工、アングガスに使用し、前記炭素および炭素
の化合物およびポリマー等の前記多結晶シリコン膜上へ
の堆積を防ぎエツチングを行なう。When etching a silicon film, such as a polycrystalline silicon film, by reactive ion etching or parallel plate plasma etching using chlorine-based gas, carbon, carbon compounds, polymers, etc. are deposited on the polycrystalline silicon film during etching. Since the progress of the polycrystalline silicon film is inhibited, a gas prepared by adding oxygen to a chlorine-based gas is generally used as the chemical reaction gas, and the carbon, carbon compounds, polymers, etc. are deposited on the polycrystalline silicon film. Perform etching to prevent deposition on the surface.

半導体基板上に形成した酸化膜上に形成されたＰドープ
多結晶シリプン膜ｔホトレジスト等をマスクとして反応
性イオンエツチングまたは平行平板プラズマエツチング
によ）前記Ｐドープ多結晶シリコンｌ１ｌＩを微細加工
する場合に、塩素系ガスに酸素全添加したガスをエツチ
ングガスとして使用しエツチングを行なうと第１図に示
すように前記Ｐドープ多結晶シリコン膜にアンダーカッ
ト、が生じる。特に前記半導体基板上の戚化嗅と前記Ｐ
ドープ多結晶シリコン膜との境界面におけるアンダーカ
ット量が多く、アンダーカッ−トの量はオーパエッチの
時間に依存して増加する。When microfabricating the P-doped polycrystalline silicon film (by reactive ion etching or parallel plate plasma etching) using a P-doped polycrystalline silicon film formed on an oxide film formed on a semiconductor substrate as a mask, When etching is performed using a chlorine-based gas with all oxygen added as an etching gas, undercuts occur in the P-doped polycrystalline silicon film as shown in FIG. In particular, the phosphor on the semiconductor substrate and the P
There is a large amount of undercut at the interface with the doped polycrystalline silicon film, and the amount of undercut increases depending on the over-etch time.

前記半導体基板上に形成された酸化膜上ＯＰドープ多多
結フシリーン膜管ホトレジスト等管マスク反応性イオン
エツチングまたは平行平板プラズマエツチングによ〕微
細加工する場合に１前記Ｐドープ多結晶シリコン膜のア
ンダーカットが生じると、前記Ｐドープ多結晶シリコン
ｌ１１ｔ−再現性良く做に加工することが難しくなる。OP-doped polycrystalline silicon film on the oxide film formed on the semiconductor substrate (op-doped polycrystalline silicon film tube photoresist etc. by mask reactive ion etching or parallel plate plasma etching) 1. Undercutting of the P-doped polycrystalline silicon film If this occurs, it becomes difficult to process the P-doped polycrystalline silicon with good reproducibility.

そのため、素子の電気的特性が設計通）にならず、素子
の特性管再現性良く得ることが困難となる。Therefore, the electrical characteristics of the device do not match the design, and it becomes difficult to obtain good reproducibility of the device's characteristics.

本発明は上述の従来の塩素系ガスにｒＲＸを添加したガ
スをエツチングとして使用する反応性イオンエツチング
ｔたは平行平板プラズマエツチングにょるＰドープ多結
晶シリコン膜を微細加工する技術の欠点を除去し、塩素
系ガスを使用する反応性イオンエツチングま友は平行平
板ブラズｉ工。The present invention eliminates the drawbacks of the above-mentioned conventional techniques for microfabrication of P-doped polycrystalline silicon films using reactive ion etching or parallel plate plasma etching, which uses a chlorine-based gas to which rRX is added. , Reactive ion etching using chlorine gas is best suited for parallel plate brazing.

アングによるＰドープ多結晶シリコン膜の微細加工に適
し次ドライエツチング方法を提供するものである。This invention provides a dry etching method suitable for microfabrication of P-doped polycrystalline silicon films using Ang.

本発明による方法は半導体基板上に形成された酸化膜上
のＰドープ多結晶シリコンＪｌ［ｆ：、選択的に形成さ
れたホトレジスト等をマスクとして塩素系ガスＫｒＩＩ
素を添加したガスを工、アングガスとして使用した反応
性イオンエツチングまたは平行平板プラズマ工、チング
によム前記Ｐドープ多結晶シリコン膜を途中までエツチ
ングする第１の工、アング処理を行なり几後、Ｉｒｌの
エツチング処理で残ってｂるＰドープ多結晶シリコン膜
を塩素系ガスを使用した反応性イオンエツチングまたは
平行平板プラズマエツチングにょクエッアング除去する
第２のエツチング処理を行なうことにょり、前記第４の
エツチング処理で途中までエツチングした前記Ｐドープ
多結晶シリコン膜をアンダーカットのない所望するパタ
ーンに微細加工するドライエ、アング方法である。The method according to the present invention uses P-doped polycrystalline silicon Jl [f:] on an oxide film formed on a semiconductor substrate, and chlorine-based gas KrII using selectively formed photoresist or the like as a mask.
The first step is to etch the P-doped polycrystalline silicon film halfway through reactive ion etching or parallel plate plasma etching using a gas added with an element as an Ang gas. By performing a second etching process in which the P-doped polycrystalline silicon film remaining after the Irl etching process is removed by reactive ion etching using a chlorine-based gas or parallel plate plasma etching, the fourth etching process is performed. This is a dry etching method in which the P-doped polycrystalline silicon film, which has been partially etched in the etching process described above, is microfabricated into a desired pattern without undercuts.

第１のエツチング処理でエツチングする前記Ｐドープ多
結晶シリコン膜の膜厚はエツチング前の前記Ｐドープ多
結晶クリーン膜厚の５（１〜９０％である。The thickness of the P-doped polycrystalline silicon film etched in the first etching process is 5% (1 to 90%) of the thickness of the P-doped polycrystalline clean film before etching.

本発明は反応性イオンエツチングまたは平行平板プラズ
マエッチングによ〕半導体基板上に形成した酸化膜上０
Ｐドープ多結晶シ１】コン膜をエツチング加工する方法
において、酸素を添加した塩素系ガスをエツチングガス
として使用した場合に生じる前記Ｐドープ多結晶シリコ
ン膜のアンダーカットと、塩素系ガスをエツチングガス
として使用した場合におきる前記Ｐドープ多結晶シリコ
ン膜上の炭素および炭素化合物およびポリマー等の堆積
によシエッアングの進行の阻害とによる工。The present invention is based on an oxide film formed on a semiconductor substrate by reactive ion etching or parallel plate plasma etching.
P-doped polycrystalline silicon 1] In the method of etching a silicon film, undercutting of the P-doped polycrystalline silicon film occurs when a chlorine-based gas to which oxygen is added is used as an etching gas, and When used as a polycrystalline silicon film, the deposition of carbon, carbon compounds, polymers, etc. on the P-doped polycrystalline silicon film inhibits the progress of etching.

アングの不安定性をなくす方法で、前述したように第１
の工、アング処理と第２の工、アング処理とからなるこ
とを特徴とするドライエ、アング方法である。As mentioned above, this is the first method to eliminate the instability of Aang.
This dryer and ang method is characterized by comprising a second step, an ang treatment, and a second step, an ang treatment.

次に図面を用いて本発明によるドライエツチング方法の
一実施例を説明する。Next, an embodiment of the dry etching method according to the present invention will be described with reference to the drawings.

第２図（ａ）［おいて用いる半導体４例えばＮｆｆ１シ
リコンク、ハの表面上に絶縁物層３として例えば酸化膜
を形成した後に、前記絶縁物層３上にＰドープ多結晶シ
リコン膜２ｔ−形成する。その後第２１ｅ　（ｂｌに示
すように前記Ｐドープ多結晶シリコン膜２上にポジタイ
プホトレジストを所望するパターンに形成する。FIG. 2(a) After forming, for example, an oxide film as an insulating layer 3 on the surface of a semiconductor 4, for example, Nff1 silicon, used in FIG. do. Thereafter, a positive type photoresist is formed in a desired pattern on the P-doped polycrystalline silicon film 2 as shown in step 21e (bl).

次に半導体基板４上の絶縁膜３上に形成したＰドープ多
結晶シリコン膜２を選択的にパターニングしたポジタイ
プホトレジスト１をマスクとして、塩素系ガス例えばＣ
Ｃ〕、にｅ素を添加したガスを工、アングガスとして使
用する平行平板プラズマエツチングまたは反応性イオン
千ツアング例えば為周波として３７０ＫＨｇを使用した
真空予備室付きの平行平板プラズマエツチングにより、
第２図（ＣＩＫ示す如く前記Ｐドープ多結晶シリコン膜
２を途中まで工、アングすゐ、前記途中まで工、アング
し［Ｐドープ多結晶シリョン膜２′の厚さは、工、アン
グ前の前記多結晶シリコン膜２の膜厚の５９６〜５０％
である。この時の工、アング条件の圧力は１０””Ｔ　
　　〜ＩＴ　　　程度である。Next, the P-doped polycrystalline silicon film 2 formed on the insulating film 3 on the semiconductor substrate 4 is selectively patterned using a positive type photoresist 1 as a mask, and a chlorine-based gas, such as carbon dioxide, is used as a mask.
C], by parallel plate plasma etching using a gas added with e element as an angular gas or by parallel plate plasma etching with a vacuum preparatory chamber using reactive ions, e.g. 370 KHg as a wave frequency.
As shown in FIG. 596 to 50% of the film thickness of the polycrystalline silicon film 2
It is. At this time, the pressure of the work and angle conditions is 10""T
~ IT level.

ｏｒｒ　　　　　ｏｒｒ 次に前記ホトレジス）１？マスクにして前記途中まで工
、アングし７１：、Ｐドープ多結晶シリコン膜２′會塩
素系ガス例えばＣＣ１４ｔ’工、アングガスとして使用
し次平行平板プラズマエツチングｔたは反応性イオンエ
ツチング例えば前記高周波として３７０ＫＨｇ　′ｔ−
使用した真空予備室付きの平行平板プラズマエツチング
により第２図（ｄ）に示す如く工、アングを行ない、ア
ンダーカットのないＰドープ多結晶シリコン膜２＃を所
望するパターンに形成する。この時のエツチング条件の
圧力は１Ｏ−２’ｒｏｒｒ〜１Ｔｏｒｒ程度である。orr orr Next, the photoregis) 1? Using a mask, process and etch the P-doped polycrystalline silicon film 2' to the middle of the process. Using a chlorine-based gas such as CC14' as an etch gas, perform parallel plate plasma etching or reactive ion etching, such as the high frequency 370KHg 't-
Using the parallel plate plasma etching equipped with a vacuum chamber, etching and etching are performed as shown in FIG. 2(d) to form a P-doped polycrystalline silicon film 2# without undercuts into a desired pattern. The pressure of the etching conditions at this time is about 10-2'rorr to 1 Torr.

以上述べ几如く本発明によると塩素系ガスを使用した反
応性イオンエツチングまたは平行平板プラズマエツチン
グにより半導体基板上の酸化膜上に形成しｆｉＰドープ
多結晶シリコン膜を選択的にパターニングする方法にお
いて、前記Ｐドープ多結晶シリコン膜に微小なアンダー
カットを生じることなく所望するパターンに微細加工で
きることが可能なことが明らかである。As described above, according to the present invention, in a method for selectively patterning a fiP-doped polycrystalline silicon film formed on an oxide film on a semiconductor substrate by reactive ion etching or parallel plate plasma etching using chlorine-based gas, It is clear that it is possible to microfabricate the P-doped polycrystalline silicon film into a desired pattern without causing minute undercuts.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の工、アング方法によりエツチングした後
のＰドープ多結晶シリコン膜のアンダーカッ）１−示す
断面図である。 第２図（ａ）乃至第２図（ｄ）Ｆｉ本発明の詳細な説明
するための断面図である。 図において、 １・・・・・・ポジタイプホトレジスト　ｇ　、　２／
　、　ｔ２Ｎ。 ２″′・・・・・・多結晶シリ；ン膜、３・・・・・・
絶縁面例えば酸化膜、４・・・・・・半導体基板である
。FIG. 1 is a sectional view showing an undercut of a P-doped polycrystalline silicon film after etching by a conventional etching method. FIG. 2(a) to FIG. 2(d) are sectional views for explaining the present invention in detail. In the figure, 1... Positive type photoresist g, 2/
, t2N. 2″′...Polycrystalline silicon film, 3...
The insulating surface is, for example, an oxide film, 4...a semiconductor substrate.

Claims (1)

【特許請求の範囲】[Claims] 塩素系ガスを使用した反応性スパッタエツチングｔたは
平行平板プラズマエツチングにより半導体基板上に形成
されたシリコン膜を微細パターニングする方法において
、前記塩素系ガスに酸素を添加したガスによシ前記シリ
コン膜を途中まで工、アンダする第１の工、チック処理
と、前記第１のエツチング処理で残したシリコン膜を酸
素ケ添加しなｉ塩素系ガスによ）工、アングする第２の
工、アング処理とを含むことを特徴とするプラズマエツ
チング方法。In a method for finely patterning a silicon film formed on a semiconductor substrate by reactive sputter etching or parallel plate plasma etching using a chlorine-based gas, the silicon film is etched by a gas in which oxygen is added to the chlorine-based gas. The first step is to process and undercut the silicon film halfway, and the second step is to remove the silicon film left by the first etching process using a chlorine-based gas without adding oxygen. A plasma etching method comprising:
JP4105582A 1982-03-16 1982-03-16 Plasma etching method Pending JPS58158927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4105582A JPS58158927A (en) 1982-03-16 1982-03-16 Plasma etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4105582A JPS58158927A (en) 1982-03-16 1982-03-16 Plasma etching method

Publications (1)

Publication Number Publication Date
JPS58158927A true JPS58158927A (en) 1983-09-21

Family

ID=12597719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4105582A Pending JPS58158927A (en) 1982-03-16 1982-03-16 Plasma etching method

Country Status (1)

Country Link
JP (1) JPS58158927A (en)

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