JPS5815730A - Speed controller for vehicle - Google Patents

Abstract

PURPOSE:To improve safety of operation for speed control, by providing a self holding circuit between an electric controller and operating mechanism, confirming the normal action of said self holding circuit and then performing the speed control. CONSTITUTION:A self holding circuit 60 is provided between a microcomputer 110 of a speed control circuit 1 and a throttle actuator 2, operating mechanism. This self holding circuit 60 is constituted as a bistable circuit by two input NAND elements 61, 62, and a reset input R' is connected to an output of a negative logic OR elemet 53 and an input 1 of a 3-input AND element 63. Further a set input S' is connected to an input 3 of the 3-input AND element 63 and the output of an inverter element 94, while an output Q' is connected to an input terminal P4 of the microcomputer and input of an inverter element 93.

Description

[Detailed description of the invention] related to control equipment.

Devices of this type are well known for displacing a speed regulating element such that the vehicle is maintained at a fixed target speed. An electric control device is used to generate a control output signal and control the speed regulating element by analog or digital electric calculations to reduce the difference between the measured actual vehicle travel speed and a stored or set target vehicle speed. and drives an actuating mechanism movably provided between.

This device basically operates to feedback control the speed of the vehicle.

Recently, various additional control functions have been required for such speed control devices. For example, in order to simplify the operation switch, one switch can be given two definitions to make it a dual-purpose type, or it can be used to diagnose equipment failures and output the results, or it can be used to change gears for cooperative control with an automatic transmission. The possibility of outputting a request signal is being considered.

In order to satisfy these various demands, the circuit scale becomes large, and an increase in the number of parts leads to a decrease in overall reliability.

For this reason, it is necessary to carefully develop and design the device so that failures and the like do not occur as much as possible, and to ensure that the speed adjustment element operates safely even if an unexpected problem occurs.

In view of the above requirements, the present invention provides a self-holding circuit between the electric control device and the operating mechanism, and performs speed control after confirming the normal operation of this self-holding circuit, thereby increasing safe operation. The object is to provide a speed control device.

In order to additionally provide various control functions, it is desirable to use a stored program computer with four microphones as the electrical control device.

In the present invention, the actuation mechanism includes a first member that is operatively coupled to and released from the speed regulating element by an electrical signal, and a first member that is operated to displace the regulating element in response to the electrical signal in the state of the operatively coupled state. and a second member.

When this operating mechanism is of the pneumatic type, the first member is an electromagnetically actuated release valve, and the second member is an electromagnetically actuated control valve (on-off valve). Further, when the actuation mechanism is an electric motor type, the first member is an electromagnetic clutch and the second member is a reversible motor.

According to the present invention, a self-holding device consisting of a bistable circuit is arranged between the electric control device and at least the first member of the actuation mechanism, and in the self-holding state, the first member is actuated in response to an electric signal. The mechanism is configured to provide operative coupling between the mechanism and the speed regulating element.

Then, before starting speed control, the digital computer checks the operating function of the self-holding device, and if it is normal, executes speed control.

This check may be performed at any time from the time the device is powered on until speed control is started, but it is easier to perform this check immediately after the power is turned on, when no switch operation has been performed by the occupant.

The embodiments of the invention described below have further features and advantages as described below.

(1) In the process of creating vehicle speed data from vehicle speed pulse signals, the number of pulses used for each measurement and the resolution of calculation are changed in stages according to the target vehicle speed. This makes the measurement time per measurement almost constant regardless of vehicle speed, and uses a low-processing-speed digital computer to ensure response performance at low vehicle speeds and at the same time ensure accuracy of vehicle speed values at high vehicle speeds. can do.

Furthermore, since the time required for each measurement is approximately constant, the vehicle speed calculation can be completed within the time interval for outputting the on/off control signal for the constant cycle duty ratio adjustment type operating mechanism.

This is useful for facilitating program design in stored program microcomputers. Additionally, vehicle speed calculation is performed distributed over the on-time or off-time depending on the duty ratio of the on-off control signal.

Furthermore, abnormal fluctuations in detected values are suppressed for vehicle speed data by calculating a weighted average value of old and new data.

(2) The vehicle speed after 1000s of milliseconds is predicted from the gradient of change in the created vehicle speed data, and the amount of adjustment of the operating mechanism is determined according to the difference between this predicted value and the target vehicle speed.

As a result, the response delay component of the adjustment system is compensated for by advance control, and stable vehicle speed control with hunting suppressed is executed. Note that this value is determined by the responsiveness of the regulatory system.

(3) The input/output logic of the semiconductor switch element for driving the operating mechanism is monitored, and in the event of an abnormality, the self-holding circuit is disabled and speed control is prohibited.

An embodiment of the present invention will be described below based on the drawings. #1
IIlvlJ shows the system configuration of the present invention. 1 is a speed control circuit which internally includes a microcomputer, an input signal processing section, an output signal driving section, etc. ! Hasaku 111
When released, the negative pressure diaphragm chamber is in communication with the atmosphere using a known vacuum actuator equipped with an electromagnetic release valve release pulp and an electromagnetic actuated valve control pulp that intermittently modulates atmospheric pressure and negative pressure using a throttle actuator as $1111. When the release pulp is driven, the negative chamber is shielded from the atmosphere. By driving the release pulp and increasing or decreasing the driving tune of the control pulp, which is a second member, the internal pressure of the negative pressure chamber is changed and the throttle valve of the automobile engine is operated to the opening side or the closing side, This structure increases or decreases vehicle speed. 3 is a car engine.

4 is an automatic transmission that transmits the driving force of the engine to the wheels, and this transmission is a so-called electric transmission that can change the gear position from the highest gear to the next lower gear by applying an electric signal and driving a diagonal solenoid. Control automatic transmission. Reference numeral 5 denotes a vehicle speed signal sensor, which is composed of a reed switch that is opened and closed by a magnet that rotates at the same speed as the speedometer cable of the automobile, and outputs four pulses per rotation of the meter cable. In this example, the meter cable is configured to rotate several hundred revolutions per minute when the car is traveling at 601 bl/h. 6 is a group of switches such as set, resume, and cancel.

FIG. 2 is an electrical wiring diagram of the embodiment, and 1 is the above-mentioned ? [In the control device, 2 indicates the throttle actuator, 4 indicates the electrically controlled automatic transmission, and 6 indicates the vehicle speed sensor.

Reference numeral 8 denotes an in-vehicle battery whose negative terminal is grounded to the body, and whose positive terminal is connected to a common terminal AM of an ignition key switch 9. The G terminal of the ignition key switch 9 is a so-called power supply line, and is connected to one end of the speed control device fuse 10, one end of the stop lamp/use 12, one end of the parking brake fuse 15, and the transmission control fuse 22. connected to one end of each.

The eight terminals of the ignition key switch 9 are connected to the a terminal of the speed control device 1 and one end of the neutral switch 18. The other end of the neutral switch 18 is connected to a starter motor 19 (9) whose one end is grounded to the body. The other end of the fuse 1o connected to the G terminal is connected to one end of the power switch 11 of the speed control device 1, and the other end of this power switch is connected to the +Bgs terminal of the speed control device 1.

The other end of the F tube fuse 12 is connected to the sty@ terminal of the speed control device 1 and -m of the stop switch 13, and the other end of this stop switch 13 is connected to the S? terminal of the speed control device 1. The P terminal is connected to a stop lamp 14 whose one end is grounded.

The other end of the parking brake fuse 15 is connected to one end of the parking brake lamp 16, and the other end of the parking brake lamp 16 is connected to the speed control device! ! Parking brake switch with one terminal and one end grounded to the body
? It is connected to the.

One end of the electrically controlled automatic transmission number is connected to the 8FT terminal of the speed control device, and the other end is connected to the other end of the transmission control fuse 2z.

One end of the control pulp drive coil 2N+ and the release pulp In coil 2αO) a of the negative pressure actuator ε is connected to l day, respectively, and the other end of the release pulp drive coil is connected to the RV terminal of the speed control bag N1. The other end is C of speed control device 1
Connected to V terminal.

One end of the speed sensor 5 is connected to the body, and the output end is connected to the 8FD terminal of the speed control device.

One end of the accelerator/coast switch 20 and the resume/accelerator switch z1 are each grounded to the body,
The other ends are the SET terminals of the speed controller t1, ! Connected to L and B terminals.

Next, the configuration of the speed control device 1 will be explained.

110 is vehicle speed calculation, control judgment, and duty calculation.

This is a microcomputer that controls the negative pressure actuator. A microcomputer has ROM, which is a program memory, in one package.

RAM, which is data memory, and various registers for calculations.

This is a well-known device that incorporates an 8-bit internal timer and has signal line terminals such as a power supply terminal, an initial start terminal, an external interrupt terminal, an input terminal, and an output terminal.

αυ Work H is connected to the power supply line +B of the speed control device 1, and the common end G
ND is connected to the ground wire 150, and the output terminal OUT is connected to the stabilized power supply line 130.

3F is a voltage comparator, and the power supply and ground terminals are connected to the stabilized power supply $11309 ground line 150.

44 is a semiconductor integrated circuit for detecting abnormalities in a microcomputer, and has a period Tp of pulses periodically input from the computer 110 to an input terminal T, and a time constant T of a capacitor 43 connected to a capacitor terminal C.

If Tp is smaller than TO, output q will be @L level, and if %TP is larger than TO, then tH force Q,
It repeatedly outputs "II" level and 1H level. This power supply and ground terminal is connected to a stabilized power supply line and ground line 150.

38 is a two-man OR element, which is shown in a logic diagram in the figure.
+$1. 69. F 6. 93.
94. 123°125 is an inverter element, 52
is a 1-man powered VOR element, 55 is a negative logic OR element (wired OR), 61.62 is a 2-man powered MAND element, 63 is a 3-man powered (12) ACIn element, M0 is a 2-man powered AND element, 120 is a Shunotsu )) It is a trigger element, and although not shown, the power and ground terminals of each element are a stabilized power supply line 130 and a ground line 1110.
are connected to each.

Reference numeral 111 denotes a vibrator, which is connected to external pin terminals 0801 and 08C2 of the microcomputer.

11fi-119 is a semi-fixed switch whose one end is connected to the input terminals Fil to P18 of the microcomputer, and the other end is all connected to the ground line 130.

30 is a reset circuit for the microcomputer, which is connected from the voltage dividing point of the power supply voltage dividing resistors 31 and 33 to the e terminal of the voltage comparator 3F, and is connected to the reference voltage generating resistor $3. Zener diode 34 is connected to e through hysteresis setting resistor 35.
A positive feedback resistor 36 is connected between the Φ terminal of the voltage comparator and the output terminal, and the output terminal is connected to the logic circuit 38.
It is connected to the input terminal (2) of the logic circuit B2, which will be described later.

α3) The output terminal q of the microcomputer abnormality detection integrated circuit 44 is connected to the input terminal ■ of the OR element 38 and the input terminal ■ of the 01 element 52, and the output terminal of the OR element 38 is connected to the resistor 3-
It is connected to the pace of the reset transistor 40 via. The emitter of transistor 40 is ground line 1! s0
A resistor 41 whose collector is pulled up to a stabilized power supply, and a signal delay capacitor 4 whose one end is grounded.
2 and is connected to the input terminal Rm81T of the microcomputer.

The P8 terminal of the microcomputer is a cancel signal input terminal for stopping, canceling, or inhibiting speed control, and when this level is b, a cancel signal is present. The cancellation signal 0AII given to this terminal is
011 is connected to the output of logic element s2. This one person power 1i
The input terminal of the on logic element 52 is connected to the output q of the integrated circuit 44, the input is connected to the output of the voltage comparator 37, the input is connected to the output of the inverter element 51, and the input is connected to the pull-down resistor s9 and the diode 115. ,104.89 Ka-''
4) Connected to the respective ports.

The input of the inverter element s1 is a diode 54°56
．． Connected to the 5th anode. The cathode of the diode 54 is the 8Tν terminal, and the cathode of the diode 56 is the PKI terminal.
I terminal, diode 5? are connected to the 1B terminal, respectively. The anode of the diode 55 is connected to the BT:P terminal.

60 is a self-holding circuit, which includes two 2-man power IA) iD elements 6
1 and 62 constitute a bistable circuit. The reset human power R of the self-holding circuit 60 is a negative logic OR element (101
1 element) 53 and the input l of the 3-person cam ID element 63
connected to. Furthermore, the input (2) of the 11-OR element 53 is connected to the output of the four-person MOR element 52 and the P2 terminal of the microcomputer, and the input (2) is connected to the output terminal P3 of the microcomputer. On the other hand, the set input 8 of the self-holding circuit 60 is connected to the input 3 of the three-person cam MD element 63 and the output of the inverter element 94, and this input is connected to the output terminal P15 of the microcomputer.

Next, the output q of the self-holding circuit 60 is connected to the input terminal P4 of the microcomputer (αb) and the input of the inverter element 93, and this output is connected to the input terminal (2) of the three-person cam ID element 63.

The three-man powered A11D element 63 is a circuit that determines the drive logic of the release pulp, and the output is connected to the input terminal of the two-man powered AND element FO and the transistor 65 via the pace resistor 64.
Connected to the pace of. The emitter of the transistor 65 is connected to the ground line 150, and the collector is connected to the anode of the drive abnormality detection diode 81 and the pace of the F transistor 8 for driving the release valve via the resistor 66.

The emitter of this transistor 68 is connected to the power supply line B, and a resistor 6F is connected between the emitter and the pace.

Further, the collector of the transistor 68 is connected to the anode of the drive abnormality detection diode 82 and to the release valve drive terminal RV.

F0 is the logic circuit for driving the control valve AII)
The input power is connected to the output of the A11D element for driving the release pulp, and the input is connected to the output of the inverter element 69.
The input of 9 is connected to the output terminal r6 of the microcomputer. On the other hand, the output of the MMD element 70 is connected to the base of the transistor F2 via the resistor T1. The emitter of this transistor 7B is grounded, the collector is connected to the anode of a drive abnormality detection diode 83, and further connected to the pace of a control valve driving transistor F5 via a resistor F3. A resistor 4 is connected between the pace emitters of this driving transistor 76, and the emitter is connected to the power supply line +1. On the other hand, the collector of the transistor F 5 is connected to the anode of the drive abnormality detection diode 84 and the F roll pulp drive terminal aV.

Reference numeral 80 is a drive abnormality detection circuit, and transistor 90 is a transistor for detecting drive abnormality of the release pulp and control pulp.

The emitter is connected to the power supply line +1, a resistor 91 is connected between the pace and the emitter, and diodes 86 and 8 are connected to the pace.
8 anodes are connected. The cathode of the diode 8 is connected to the cathodes of the diodes 81 and 88 for detecting an abnormality in the release pulp driving transistor 68, and is further pulled down by a resistor 8. On the other hand, the cathode of the diode 86 is connected to the cathodes of the abnormality detection diodes 83 and 84 of the control valve driving transistor 5, and is further pulled down by a resistor 85.

The collector of 90 is connected to the diode 8 through a resistor 92.
It is connected to the anode of 9.

F8 is a transistor for driving the automatic transmission. Inverter element 〒6. It is connected to the pace of transistor 'F8 via resistor 〒7. The emitter of transistor 78 is connected to ground line 15
0, the collector is connected to the electrically controlled automatic transmission drive end 8
Connected to one.

100 is an output duty abnormality detection circuit, with diode 1
The cathode of 01 is connected to the collector of the transistor 75, the node 7 is connected to the anode resistor 101 of the diode 104, one end of the capacitor log α8), the other end of the resistor 103 is connected to the power supply gate B, and the other end of the resistor 103 is connected to the power supply gate B,
The other end of 2 is connected to the ground wire 150.

The vehicle speed signal is input from the vehicle speed terminal 8PD, and is connected to one end of the chattering prevention capacitor 122 and the pull-up resistor 12.
1 and the input of the Schmitt trigger element 120, and its output is connected to the external interrupt input terminal IRQ of the microcomputer. The other end of the capacitor 122 is connected to the ground line 150, and the other end of the resistor 121 is connected to the stable power line 1.
It is connected to 30.

The input terminal 81T of the set switch has a pull-up resistor of 1B.
4 and the input of the inverter 123, and the output of 12B is connected to the input terminal P9 of the microcomputer. Note that the other end of the resistor 124 is a stabilized power supply! Connect to 1130.

The resume switch input terminal RNFi is connected to one end of the pull-up resistor 126 and the input of the inverter 125, and the output of the inverter 121 is connected to the input terminal PIO of the microcomputer. The other end of resistor 126 is a stabilized power supply! It is connected to 1130 (19).

A filter capacitor 24 is connected between the stabilized power supply $3130 and the connection line 150.

Next, regarding the operation of the constant speed cruise control device for automobiles with the above-mentioned configuration, the configuration diagram in Figure 2, Figure 3 showing the main free chart of the microcomputer, the internal timer interrupt routine of the microcomputer, and the external vehicle speed interrupt routine are shown. This will be explained with reference to the operation list shown in FIG. 4 and FIG. 5.

In FIG. 2, when the ignition switch 9 of the automobile and the power switch 11 of the speed control device 1 are turned on,
The voltage of the battery 8 (127) is changed by the switch 9,7 use 10. Terminal +1 of speed control device 1 via switch 11
supplied to Then, a stabilized voltage (+
5'i) to charge the power supply capacitor 24.

The operation of the reset circuit 30 of the microcomputer 110 will be explained. If the voltage of the constant voltage bus 130 is less than 1000 min for the microcomputer 110 to operate, the voltage comparator 37
The input terminal e has a value divided by the resistors 31 and 32. On the other hand, the input terminal e of the voltage comparator 37 is approximately equal to the voltage determined by the Zener diode 34, and this is set to be greater than the input terminal e, so the output of the voltage comparator 37 becomes H level, which is the zero logic The input ■ of the element 38 is set to H, its output becomes H level regardless of the input ■, and the transistor 40 is turned off through the resistor 39.
Let N. The delay capacitor 42 is in a discharged state, the input terminal R181T of the microcomputer is at L level, and the microcomputer is in a reset state. At this time, all output terminals PL, P of the microcomputer
3. P5. P6. Ptsu becomes H level.

Microcomputer output terminal p6. If p'y is at the H level, the release pulp and control pulp of the actuator 2 are in an open state, as will be described later.

Next, if the voltage of the stabilizing bus 130 reaches a voltage sufficient for the microcombi (21) to operate normally, for example SV, the voltage at the terminal e of the voltage comparator 130 does not change, but the voltage at the terminal e Since the resistor 31.3ffi is set so that the voltage is higher than the terminal Φ, the voltage comparator 3
The output of F is at L level.

This results in 0]! The input ■ of the logic element 38 is L, and the output terminal q of the integrated circuit 44 is @ if there is no change in the input terminal 〒.
Since the H″@TJIF level is repeated, the output of OR logic element 3♂ will repeat PL and L. Therefore, this turns the transistor ship on and off through resistor 39, and this is controlled by resistor 41 and delay capacitor No. 2. When the voltage bus reaches the input terminal R]C81CT■ a little later than the voltage at which the microprocessor can operate, the microcomputer starts from the beginning of the program.

On the other hand, the main point of the X-in 7o- of the microcomputer is programmed to change the output terminal P1 to the H1L level at a fixed period (several tens of 19 seconds).

This signal gives a trigger to the microcomputer abnormality detection integrated circuit 44, and the output i remains at Lrepair a2). However, if there is a problem with the microcomputer and it no longer processes the main points of the program, the output terminal P
Since 1 does not change, the output of integrated circuit No. 4 becomes H,
The input ■ of the OR logic element 38 becomes ■, turning on the transistor 40 through the resistor 39, so that the microcomputer starts the program from the beginning as described above.

When the power of this device is turned on as described above, the 'ptxsx'x terminal of the microcomputer temporarily becomes L.

At this time, the output ports PL and P of the microcomputer
3. P5. P6. P'7 is initialized to H level. Then, the release pulp drive logic output becomes the b level via the inverter 93, and the transistor 65 is turned off.

Since the resistor 8 has a higher resistance (10 times) than the resistor 66, the transistor 68 is in an off state and the release valve 2a is not driven. On the other hand, inverter logic element 6
The output of the control valve 9 is also L, and the output of the control valve driving wheel control element 70 is L, and the control valve 2b is not driven as described above. Furthermore, the inverter logic element connected to the P7 output of the microcontroller (23)? The output of transistor 6 also becomes L, and the pace of transistor 78 becomes L.
level, and this transistor off 8 is also OF? Then,
The shift output is in an open state.

Subsequently, when the RISET terminal becomes H level, the microcomputer starts the program from the beginning. When the microcomputer starts, it first executes the initial setting routine 210 shown in FIG. This routine 210 includes steps 211, glz, 213, 214.
It consists of each routine.

Step 211 is a self-holding circuit testing routine, the details of which will be explained with reference to FIG.

First, in step α), Pj! Determine whether the input is at the R level, and if it is H, there is a step (step), and if it is L, there is a manual cancellation due to the operation of the brake signal, etc., so wait until the input becomes H. Even if the input is 5. For example, since the self-holding circuit can be tested by a microcomputer, the following steps are executed.
The output and FB ratio output are set to H. Step (3) is to check whether the self-holding circuit 60 is in the set state. That is, if the 24 manpower is at L level, it is set normally and the process goes to step (4), and if the 24 manpower is at L level, the process returns to step (1). Step (4) is
Outputs a cancel signal.

In other words, the P3 output is set to L level. Step (5) is to determine the priority of the cancel signal and the set signal.
If the 24 man power is 5, the priority of the cancel signal is high,
Since it is normal, proceed to step (6) and the 24 manpower is L.
If so, proceed to step (1).

Step (6) is a routine that creates a state in which a cancel signal is present during constant speed driving control, and is achieved by setting the ps output to the L level. Step ()) checks whether the self-holding circuit has been reset in step (6). That is, if the 24-manpower is at the H level, the reset state is normal, and the process goes to step (8), and if the 24-manpower is at the L level, the process goes to step ψ5).

Step (8) initializes the self-holding circuit.

In other words? This is executed by setting the 3 output and the Phi output to H. The above completes the self-holding circuit 60 and its peripheral logic elements 5.
3,181. Check the functions of ax and 94, and proceed to the next routine only if everything is normal. Write the value 0 to 1 to all ilAMs. If it can be read, proceed to the next, if not, loop within this routine. .

213 is a RAM set routine that sets all reference data of the output boat to 1, sets the four vehicle speed interval values to the maximum value ('yyyu), sets the vehicle speed interrupt counter to the initial value of 1 pulse sampling (15), and sets the vehicle speed timer to the initial value of 1 pulse sampling (15). initial value(
13) Clear all other cars, memory speed, timer, etc. to 0.

Timer start 213. In the A/-chin, the value of the 8-bit binary counter is set to 0. When this timer counter overflows from the maximum value 111FB, an internal timer interrupt (26) is generated, allowing the interrupt processing routine to perform a drum beat, and restarting the timer.

In the interrupt permission routine 214, the microcomputer's I
When the falling edge of the vehicle speed pulse is input to the RQ input terminal, the interrupt processing routine for measuring the interval between vehicle speed pulses is permitted to be interrupted.

After executing the above initial setting routine 210, the microcomputer starts the main 70 during execution T1 (several tens of milliseconds).
Due to the occurrence of a timer counter overflow that occurs at intervals, execution of the main 70- is temporarily suspended for either the timer interrupt processing or the vehicle speed interrupt processing due to the fall of the vehicle speed pulse that occurs arbitrarily in relation to the vehicle speed. After the program is finished, the program returns to main 7p- again.

First, the timer interrupt processing flow will be explained based on FIG. 4 (&). At step 400, a timer overflow occurs and a timer interrupt processing routine starts. Step 401 is a routine for determining whether or not the soft timer increment process has been executed. (z7) If not, the main 70-execution register is saved in step 40B, and then, in the soft timer increment routine 403, Increase the 4-bit software timer in the RAM area by one.

Next, in an interrupt timer increment routine 404, a software timer in the RAM area is incremented by one to determine the time since the last vehicle speed interrupt, and in step 405, it is determined whether this timer has exceeded ya-. , If there is no overflow, proceed to step 4o. If overflow occurs, the vehicle speed pulse interval l1lG
is too long to be accurately measured by the software timer according to this program, so in step 406, a hex value of 11AH, which is the maximum value that can be set as the vehicle speed pulse interval, is set.

In the register restoration routine 40, the registers saved in step 402 are restored to the state in which the main 7o is being executed. Subsequently, in step 408 (2~), the process returns to the main 70-.

On the other hand, as shown in FIG. 4(b), if a vehicle speed interruption occurs in step 500, then in step 501 the main 7a-
The execution register is saved, a 4-bit interrupt counter provided in the RAM area is incremented in the staff 502, and it is determined in step 503 whether or not there is an overflow. When an overflow occurs, interrupt counter set routine 510, timer processing routine 520 . The vehicle speed pulse interval is measured by proceeding to the vehicle speed pulse interval measurement routine 530, but if there is no overflow, the number of vehicle speed pulses has not yet reached the number of measurement pulses, so STEP! Proceed to $31.

A routine for determining the stored vehicle speed in the interrupt counter set routine 510! ill, 513° 515, and an interrupt counter seven F routine that determines how many pulses the interval between vehicle speed pulses should be measured accordingly! 11. ! ,! 1
14,516,517 are used, and the memorized vehicle speed is 66 m.
If the value is lower than that, the interrupt counter is set to 1 in hexadecimal values, and over 74- occurs every vehicle speed pulse (29), that is, the measurement interval of vehicle speed pulses is the width of one pulse.

Similarly, as shown in FIG.
C, log ~ 1461; if 11/h.

When the speed is 146 ha/h or more, the vehicle speed pulse width is measured by setting a to measure intervals of 2 pulses, 3 pulses, and 4 pulses, respectively.

On the other hand, if the timer over 70- occurs after the vehicle speed interrupt process occurs, the microcomputer of this embodiment
Since soft timer processing is not possible, soft timer processing is performed in a soft timer processing routine 52o to reduce measurement errors in vehicle speed pulse width. In other words, the soft timer processing routine 520 executes the timer over 70-
It consists of a discrimination routine +521 and a soft timer increment routine 521, and increments the software timer by 4 bits when an over-7 bit occurs in the 8-bit internal timer. Accurate 12-bit tie above! is formed.

(30) The vehicle speed pulse interval measurement routine 530 executes the next step ■
It consists of ~■.

Step ■Calculate the interval between the current interrupt time and the previous interrupt time.

Step ■Storing the calculated value of ■ to the oldest vehicle speed pulse interval area.

Step ■Memorize the current interrupt time.

As a result of executing the process in step ■■, a pointer indicating the data area of the oldest vehicle speed pulse interval is processed.

The vehicle speed pulse width is measured as described above, and then step 53
1, the interrupt timer is set to a hex value of D, and the vehicle speed timer is initialized. At step 532, an interrupt flag is set to serve as a mark in case an interrupt occurs during vehicle speed preliminary calculation. Subsequently, in step 533, the saved register is restored, and in step 53, the process returns to the main 70-.

After processing the initial setting routine 210 in FIG. 3, the microprocessor executes the main 70-, timer interrupt 74-, and vehicle speed interrupt 7-ray. Immediately after the power is turned on, there is a 7 lag jO, Fl, ? at the RAM set route (31) chin. ! ! Since all are cleared to 0, speed control is not executed. In other words, it is in an uncontrolled state, and the steps are 216→21f→j!
18 → 2 Yen O → 226 → 227 → Lazy 28 → Lazy 29 → 23
It progresses in the order of 0 → 280 → 283 → 284 → (300) and repeats this process again.

Each step in this uncontrolled state will be explained below.

The main starship time determination routine 216 is a time waiting routine for operating the set switch, resume switch, cancel switch, and calculating the OJ vehicle speed of the control pulp at regular intervals, and the lower 1 bit of the software timer must be 0. At,! Proceed to step 21 every 2 (dozens of seconds, however, 2:?lX2) intervals,
The following main flow will be executed. Step 2
By setting the P1 output to H at step 17, a trigger is given to the abnormality detection integrated circuit 44.

Input signal processing routine 21B input port PO! 2) 2, P8. At P9, a cancel signal set switch signal and a resume switch signal are input, and the chattering is removed by the following procedure and the true switch state is stored in the RAM area.

Take the exclusive OR of the input data of the procedure and the switch status data, and use this as new exclusive OR data.O.2 Take the AND of the old exclusive OR data and the new exclusive OR data and use it as AND data.

(2) Perform the logical product of the logical product data and the input data to obtain A data.

(2) Perform the logical product of the bit-inverted logical product data and the switch state data, and logically OR this data with the mu data according to (2) to obtain the switch state.

Note that since the same process is performed in step 229, which will be described later, the process of capturing the switch signal is performed every 1 second.

That is, when the set switch 2o is turned on, the input of the 03) logic 123 becomes L, the manual power of P8 becomes H, and this is taken into the RAM area as switch data in the microcomputer 110 with chattering removed. Similarly, the strip switch, stop fuse blown, parking switch, and neutral start signal are canceled by the diode 54, 5 as the cancellation signal OAM.
5,56° through logic gate 5'L, 52, P2
input to the boat, and the resume switch signal is also [1
The signal is input manually to P9 Baud F through the gate 185 and stored in the RAM as switch state data with chattering removed.

Step! ! Reference numeral 20 indicates a control pulse 2 ffi operating routine, and the duty value is set to 0% in the non-control state, so after executing the routine to determine whether the duty is 0% in step 221,
Proceed to step 6.

Step 226 is 8 after the start of the main routine.
The process waits until 7m8·a has elapsed, and the time schedule for the subsequent flow is determined.

(34) In the vehicle speed preliminary calculation routine 227, the four vehicle speed pulse widths measured in the vehicle speed interrupt process 70- are added together. This addition procedure clears the interrupt flag to 0.

Add 04 doses.

- Check the interrupt flag; if it is 0, proceed to the next step; if it is 1, a multiple interruption occurs during calculation, the vehicle speed pulse data is rewritten during calculation, and a calculation error occurs, so return to step (2) again.

By calculating in this manner, vehicle speed data is captured at regular intervals.

Step 228 is the output of the microcomputer.
L is set to L level, and in response to step 217, a trigger is given to the abnormality detection integrated circuit 44.

Step 229 is a switch signal acquisition routine, and by performing the same processing as step 218, the switch signal is acquired as data excluding chattering every several tens of milliseconds ('l''). Accordingly, the following control processing will be executed.

(35) At step ago, determine whether the 7-lag FO is O or 1, and
When , it is in an uncontrolled state! , 1 indicates a control state, and the process then proceeds to 280.

In the vehicle speed calculation routine 280, the vehicle speed is calculated based on the result of the vehicle speed preliminary calculation, and this routine is executed in the following steps.

■Transfer the previously calculated vehicle speed value to the old military speed data area.

■The dividend number is shown in the gi diagram from 11 to 4 based on the stored vehicle speed data.
Set to ×x1.

■If the preliminary calculation result is 3000 or more in hexa value, set the calculated vehicle speed as Okn/h and proceed to ■. Otherwise, set the dividend to 16720°2x16? as shown in Figure 5. ! 0
．． 3XIF61120.4X767J! Set to 0.

■Execute the preliminary calculation results for several dozen plugs, and use the results as the calculated vehicle speed.

■If the calculated vehicle speed is greater than 111 in hexa value (vehicle speed 2
10b/h or more), the calculated vehicle speed is 11!1.

(S6) - Add the previous vehicle speed and the calculated vehicle speed, divide by 8 to average them, and store this as the current vehicle speed.

As a result of the above, calculation of the vehicle speed is completed in about 10 milliseconds.

Step 283 is a 7 lag 12 determination routine during cancellation. 7 lag during cancellation is a flag that is set to 1 when speed control is set and this speed control is cancelled. Then, the process proceeds to step 284.

In step 284, the actual vehicle speed is set to 301 for the speed control.
This is a routine that determines the safe vehicle speed, whether it is lower than bIl/h or too high than 11 (lb/h). In this case, the program proceeds to the beginning 216- of the main 70- again.

The operation detection routine 300 consists of a routine that checks the set operation using the set switch and the resume operation using the resume switch (37).
At step 306, the current vehicle speed is stored in the storage vehicle speed area, and the process proceeds to step 306. On the other hand, if there is no set operation, the process advances to a resume operation determination routine 303.

At steps 303, 30, and 3o5, the process proceeds to step 306 only when there is a resume operation, the resume enable flag 11 is 1, and there is a memorized vehicle speed that is the control target. Otherwise, the process proceeds to step 306, which is the first step of the main 70-time schedule jt1g. Return to

When step 3o6 is reached by the set operation or resume operation as described above, the Pb output of the microphone 4 computer is set to L in step 306, so that the input ■ of the release pulp driving logic gate element 63 becomes level 5, Since the output page of the self-holding circuit 60 was at the L level in the initial setting routine, the input (2) of the gate element 63 becomes the R level. Also, if there are no cancel inputs such as stop switch signals, the ■ input is also H (38
) Therefore, the output becomes H. Therefore, the transistor 6B is turned on through the resistor 64, and then the release pulp driving transistor 68 is also turned on through the resistor 66, the release pulp of the actuator 2 is driven, and the negative pressure diaphragm chamber of the actuator 2 is isolated from the atmosphere. That will happen.

Next, in step 307, the control 7 lag 10 is set to 1, and thereafter the microcomputer is in the control state, and step 3
At step 08, a value equivalent to one second (20) is set in the set counter, and the process returns to step 216 at the beginning of main 70-.

As described above, in the non-control state, in step 2B4, the speed control is not set or resumed until the vehicle speed reaches the safe speed, and the speed control is started only when the vehicle speed is within the safe speed.

Immediately after the power is turned on, the resume possible flag 11 is O, and the stored vehicle speed is also O due to the initial setting routine 210.
It will be bI/h, and the number Joume will not be accepted.

Next, when the microcomputer enters the speed control state by the set operation (39) or resume operation, the control 7 lag O becomes 1, and the main 70-
16 → 21fu → 218 → 220 → 226 → 22fu → 22
8→229→230→231→2504160→265
→(2)0) are executed in sequence. The same steps 216, 217, 218, . 226, 22f, 228
．． A detailed explanation of 1!29 and 2!30 will be omitted here. The main routine starts at regular intervals in step 216, executes the L, , Ill output calchin 217, switch signal capture routine 218, and executes the control pulp drive caloutine 2! ! Go to 0.

In step 221 in this routine 220, it is determined whether the duty value is 0, and if it is O, proceed to the next step, but if there is a duty value, P6 is determined in step 221L.
Set the output to L level.

As a result, the input ■ of the logic gate F element F-0 for driving the control valve in FIG. (40) It turns on through 71, and as a result, the control seal valve driving transistor PI5 has a base resistance. It turns on through 3. Therefore, the control pulp of the actuator 2 is energized and driven.

Subsequently, in step 223, the duty value is 5.
If it is less than 0%, according to the time schedule of the main 70-, it is necessary to set the P6 output executed in step 222 before the processing in step 226 (that is, before time T1 elapses) to the H level, so proceed to step 224. . However, if the duty value is more than so%, step 2
Since there is no need to set the P6 output to H level before 26,
mtr to step 226 without doing anything.

In step 224, the progress time is compared with the time corresponding to the duty value using the soft timer, the 8-bit timer hand, and the bit timer, and the process waits until the time corresponding to the duty value is reached. When the time reaches the time corresponding to the duty value, the P6 output is set to high. level. As a result, the input (1) of the control pulp drive logic gate element 70 becomes L, the output also becomes L, the drive transistor for the control valve (41) is turned off, and the negative pressure diaphragm chamber of the actuator is connected to the atmosphere. And step 22
Proceed to 6.

At step 230, the 7-lag FO under control is 1 (set to 1 at step 3o), so step 23
Branch to 1. Step 231 is a routine for checking the cause of speed control cancellation, which will be described later. Here, if there is no cancellation, that is, step 2
The case where the process proceeds to step 50 will be explained first.

The routine 250 is configured to perform Hund seal valve driving processing and vehicle speed calculation processing in a time-sharing manner. vinegar'
In steps 251 and 252, the time at which the P6 output is set to H level (control pulp is turned off) is determined, and the duty value is determined.

If it is less than the P6 output start-up routine 2,
Since it has already been processed in 20, step 2! Proceed to I6 vehicle speed calculation routine. When the duty value is less than 70 arcs and 50% or more, after this step 251 and step 255 processing,
Since it is necessary to bring the T6 (4) output to the H level within about 10 milliseconds, the process proceeds to the time waiting routine 25Is.

If the duty value is 70% or more, the process proceeds to the vehicle speed calculation routine 253, which can be executed in about 10 milliseconds.In other words, if the duty value is less than 50%, the process proceeds from steps 251 to 25 and 256 (step 256 is (This is the same as the vehicle speed calculation routine 280.) If the duty value is less than 70% and greater than or equal to 50%, the boat P6 output process (the same process as step 224) is executed in step 255, and the process proceeds to step 256. to calculate the vehicle speed (see 2 above).
80 routine). Duty value is 70
Step if more than %! Vehicle speed calculation routine at l$3 (
The same process as step 280) is executed, and in step 264, the P6 output process (the same process as step 224) is executed.

Step 2Is is a duty calculation routine, which is executed in the following steps.

■ Subtract the old vehicle speed from the current vehicle speed and change from the previous time C43) Find the vehicle speed.

■If the absolute value of the changing vehicle speed is greater than 5, set the series of changing vehicles as 5.

(2) Check the status of boats P11 to P13 and set the multiplier set in this device.

■ Multiply the changing vehicle speed by this predetermined multiplier, 0.5 to 2
The vehicle speed after 1.5 seconds, for example, is predicted, and this is set as the predicted vehicle speed.

■ Subtract the expected vehicle speed from the stored target vehicle speed to find the error vehicle speed.

(2) Check the status of boats P14 to P1g and set the multiplier set in this device.

■ Multiply the error vehicle speed by this multiplier to find the change in duty.

■Boat! 1F, the duty reference component set for this device is set to, for example, 50 to 4B according to the state of P18.

■Add the duty change and the reference output to find the calculated duty.

■If the calculated value is less than 0%, set it to 0%, 90% <44) If it is too large, limit it to 90%.

O Add it to the previously calculated duty, divide by 2, average it, and set it in the duty storage area.

With the above steps, the duty calculation is completed and the process proceeds to the next step.

Step 258 determines whether the set counter is 0;
If it is 0, the coast/acceleration routine 260 is executed, and if it is not 0, the contents of the set counter are incremented.
Main 70 - Return to first step 216. As a result, if the seven-cut counter value is not 0 (approximately 1.5 seconds) immediately after being controlled by the set or resume operation, the coast function by the set switch and the accelerator function by the resume switch will not be processed. Shift control processing will not be performed.

The coast/accelerator routine 260 determines whether the set switch and resume switch are pressed! 61, 263, a coast processing routine 262 and an accelerator processing routine 264 when this switch is pressed. If both switches are not pressed (45), the process advances to the next shift control routine 21FO.

The course processing involves rewriting the duty value calculated in step 215'F to 0% and rewriting the stored vehicle speed with the vehicle speed determined at that time. Acceleration processing means similarly rewriting the duty to 90%, rewriting the stored vehicle speed to the vehicle speed at that time, and setting the shift control output P to level b. If you output P7, is it a logic element? The output of 6 is H
, the transistor 8 turns on through the pace resistor 7, drives the shift solenoid, changes gear,
Sufficient acceleration is possible.

In the shift control routine 270, first, in step 271, the current vehicle speed is subtracted from the stored vehicle speed, and in step 2, if this difference is 8 h/h or more, it is determined that the speed is uneven due to an uphill slope, etc. In step 273, the P output is set to L level, the shift solenoid is driven as described above, and the vehicle speed is increased to reduce the error from the target vehicle speed. If it is determined in step 2'F4 that the difference as a result of the subtraction is less than 4 mm/h, the shift lever is released in step g'ys (46). After these processes, the first step 21 of the main 70-
Return to 6.

The control routine in which speed control is being executed has been described above. During execution of this speed control, step 231
If the next cancellation condition is given in , the program 70- under control is exited.

Cancellation conditions are: (&) When the current vehicle speed is below the low speed IJ mitter of 3 o & l I/h, (b) When the stop switch 13 is turned on, (Q)
When the parking brake is pressed, (d) When the gear position becomes neutral, (・) When the energization state of the control valve 2b is longer than a certain period of time (several hundred milliseconds) determined by the output abnormality detection circuit 100. (f) When the drive state of the transistors 68 and 75 becomes abnormal and a cancellation signal is generated from the drive abnormality detection circuit 80. (2) When the self-holding circuit 60 is in the reset state, (
6)) (b) This refers to either the case where the stabilized power supply voltage is low or (the case where the phantom microcomputer is in an abnormal state); in either case, the cancellation processing routine z
Execute 40.

In the cancel processing routine 240, first, in step 241, the output of P3 is set to L level, thereby resetting the self-holding circuit 6o. Also, at step 242, boats P5, P6. Each output of P
Release pulp to make it level! 11. Control pulp zb and shift solenoid 4 are stopped.

In addition, in step 243, the seven lags 1o under control are reset. Step! ! 7 lag 1t is set during cancellation at 44. Further, in step 24B, the duty is set to 0.
and ends the cancellation process.

After the cancellation process, the first step 216 of the main 74-
Returning to normal mode, the microcomputer is in the canceling state, and the main 70- is in step! ! 16→217→8
18→2204226→227→ 2 B 8 4
1 2 94 laziness 3042 8 042 8 3+(
48) It will be processed as 290.

Since the resume switch short determination routine 290 for 7-- during cancellation is different from that for 7-- during non-control, this routine 290 will be explained.

First, in step 291, the state of the resume switch is determined, and if it is on, the main 70-first j
! 16, if the resume switch is off, the canceling 7 lag y2 is cleared to 0 in step 92, the resumeable 7 lag 11 is set to 1 in step 293, and step j! At step 94, the reset of the self-holding circuit 60 is released by setting the output of P3 to H level. Here, first in step 242, the boat P
Since the output of No. 5 is at H level, the self-holding circuit is in a set state. As a result, if the resume switch is on when going through the routine 100, the routine goes through the routine 290, and when the resume switch is turned on and then released, it is possible to resume, and from step 283 to step 284.
Proceeding to the uncontrolled state (49), the next set and resume operations are accepted.

By the way, the condition for the cancellation signal 0Alf connected to Pl of the computer 110 to go to the L level is as follows: (&) By turning on the stop switch 13, S! Since the terminal rises to the battery voltage, the input (2) of the logic gate element 52 becomes the fifth level through the diode switch.

By turning on the stop switch 13 when the stop fuse 12 is blown, the 8'j'lF terminal is grounded through the lamp 14, so the input of the logic gauge element 51 goes to L level and the output goes to R level through the diode 54. Therefore, the input (2) of the logic gate element 52 becomes H level.

((1) Parking brake switch 1 is closed and P
The KII terminal is grounded, the input to the logic gate element B1 is at L level and the output is at H level through the diode 56, and therefore the input to the logic gate element 52 is at H level.

(50) (By setting the Q automatic transmission to neutral, the neutral start switch 18 is connected to the starter motor 1 with low resistance.
9 is grounded, the N8 terminal is at ground level, the input of logic gate element 51 is at L level and the output is at H level through diode 57, and the input (2) of logic gate element 52 is at level (2).

If the self-preservation circuit 60 is reset during speed control or if the current vehicle speed becomes lower than the low speed IJ mitter (30k11/h), the microcomputer performs the same processing as when the cancel signal CAM is received. do.

Next, the operation of the output abnormality circuit 100 will be explained. During speed control, the drive duty of the control pulp 2b is 90% from 0 arc, so the Ov terminal is turned on and off at the period T2 (several tens of milliseconds) of the main 70-.
I'm returning it. At this time, when the control pulp is off, the voltage level of the signal line 1ooa is higher than the level of the ground line 150 because the (51) impedance of the pull-up resistor 103 is sufficiently higher than the impedance of the control pulp. It's just that expensive.

Therefore, the potential of the cathode of the diode 104 is approximately the ground potential due to the pull-down resistor 59, so if the other inputs of the logic gate element 52, ■ and ■, are at L level, the output is O.
A4 is at H level and there is no cancel signal.

Subsequently, in the energized state of the control pulp, when the CV terminal reaches approximately 10B of power supply voltage, the potential of the signal line 100& becomes a voltage seen in a so-called CR transient phenomenon caused by the pull-up resistor 103 and the grounded capacitor. The on time of this control pulp is at most about 9/10 of T2, and if the time constant of the resistor 105 and capacitor 104 is about several hundred milliseconds (the middle of τ2), the potential of the cathode of the diode 104 and The input {circle around (2)} of the logic element 52 is a ripple waveform, which means that the logic element 52 is considered to be at L level, and the cancel signal OAN remains at H level and no cancel signal is generated.

(52) However, if there is an abnormality such as a calculation error in the microcomputer or the reference oscillation frequency is too low, and the control valve 21+ is energized for a long time, the signal 111ooa level will be changed by the resistance log pulled up to +B and the diode 104. It is determined by a resistor 59 pulled down to the ground line. In this case, the level of the input (2) of the logic element 52 is sufficient to be judged as an H level, so the logic element 52
The output becomes L level, a cancel signal is output to the microcomputer, and the speed control is canceled at step 231 in FIG.

Next, the drive abnormality circuit 80 will be explained. Now transistor 6B is off and release pulp drive transistor 6
8, the input side of the pace resistor 66, that is, the diode 81
When the potential of the anode of the transistor 68 is about +B, the transistor 68
is off, and the collector potential, ie, the anode of the diode 82, is at a low potential. On the other hand, when the transistor 5 is on and the potential of the anode of the diode 81 is low, the transistor 68 is on, and the anode of the diode 82 (S3
) The potential is approximately +1. In other words, when operating normally, either of the anodes of diodes 81 and 82 is at the high potential of hook B, so the current flowing through the pull-down resistors 8 hardly flows through the diode 88, and the anode of the diode 8
Flows to 1,8.1+. In addition, transistor 2. Resistance f3.74. ) Ranjstav 5. diode 83.84
Since the circuit constructed by
The current flowing through 5 does not flow through diode 86 but mostly flows through diodes 83 and 84. Therefore, transistor 90
Since the pace potential of resistor 91 is pulled up to 10B, the F run raster 90 is turned off, and the pace potential of resistor 92. The input of the logic element 52, which is pulled down by the resistor 59 through the diode 89, becomes the b level, and has no effect on the cancellation signal CIAII.1. No.

However, Release Pulp J! When a is connected to the ground line, the transistor 65 is turned on and the anode of the diode 81 is at the resistance level, and the anode of the diode 62 is also at the ground level CB4), so most of the current flowing to the ground 8 is connected to the diode 88. , the transistor 90 is turned on, and a high voltage of approximately +B is applied to this flipter, so that the resistor 92. The input (2) of the logic element 52 becomes H level through the diode 89, and the cancel signal CAN becomes L level, generating a cancel signal.

Similarly, even if the control valve 2b is short-circuited to ground, most of the current flowing through the resistor 85 flows through the diode 8.
6, transistor 90 is turned on, and a cancel signal is generated.

As described above, according to the present invention, the self-holding device is equipped with a bistable circuit that operates in reverse to limit the operation of the actuating mechanism in the event of a failure of the device, and the self-holding device itself is activated prior to the start of speed control. By checking this, you can reliably cancel the speed control.

[Brief explanation of the drawing]

The attached drawings show one embodiment of the present invention. Figure 1 is an overall block diagram of the speed control device, Figure 2 is a wiring diagram of the electrical control circuit, and Figure 3 is the main circuit of the computer (5!L). 70-, FIG. 4 is a flowchart showing interrupt processing free, FIG. B is an explanatory diagram of vehicle speed information processing, and FIG. 6 is a flowchart showing details of routine ALL in FIG. 3. 1...Speed control circuit, actuator forming the toe operating mechanism: L
:L-fi, 2 & +++Release valve constituting first member, 2b... Control valve/vehicle speed increase sensor constituting second member, 6... Operation switch,
30--Reset circuit, 50--Cancel signal processing section, 60--Self-holding circuit, 110--Mitary computer. Representative patent attorney Takashi Okabe (56)

Claims (1)

[Scope of Claims] (1) A first member that switches the operational connection and release of the speed adjustment element and the adjustment element of the vehicle according to an electric signal; an actuation mechanism including a second member that operates to displace the vehicle; a vehicle speed detection device that generates a vehicle speed pulse signal at a cycle corresponding to the actual traveling speed of the vehicle; and an operation signal for starting and canceling speed control. The start and release of speed control is defined in response to the switch group generated and the operation signal from the switch group, and the difference between the actual vehicle speed and the target speed is determined based on the vehicle speed pulse signal from the vehicle speed detection device. a digital computer that generates a control command signal for driving said actuating mechanism to
and a self-holding device consisting of a bistable circuit that is disposed between a member of A speed control device for a vehicle, characterized in that it monitors the operating function of the vehicle and prohibits the speed control in the event of an abnormality. (!ri) The speed control device for a vehicle according to claim 1, wherein the digital computer monitors the self-holding circuit immediately after the start of power supply to the device. 3. The vehicle speed control device according to claim 2, wherein the computer is a stored program type microcomputer, and the self-holding circuit is monitored in an initial set program after power-on start.