JPS58155756A - One-dimensional photosensor - Google Patents

Abstract

PURPOSE:To equalize the output levels of both channels by transferring output signals from the odd and even numbers elements of one-dimensional photodiode array by each CCD and forming MOSFETs with a common source at the output terminals. CONSTITUTION:Output signals from the odd and even numbers elements are each read in parallel with CCD analog shift registes 3a, 3b through transfer gates 2a, 2b. The transfer gates 2a, 2b represent the MOSFETs, and are controlled by a signal phiG. The registers 3a, 3b are subject to pulses phi1, phi2, transfer informations read in parallel in succession and output them in series. The MOSFETs Q1, Q2 using Si layers in the output terminals of the registers as drains are formed, sources are connected in common, and informations synthesized are amplified 4, and outputted. The impedance of the Q1, Q2 is adjusted by external control voltage OG1, OG2, and the variance of a signal level between both channels can be adjusted simply.

Description

[Detailed description of the invention] The present invention relates to a -dimensional photosensor #IC.

In a one-dimensional sensor using a photodiode array,
The area occupied by a CCD (charge transfer element) constituting the transfer section is larger than the area occupied by one photosensor. Therefore, in order to make the photodiode array small and compact, it is known that the photodiode is divided into odd-numbered photodiodes and even-numbered photodiodes, and respective transfer sections are arranged at the upper and lower parts of the photodiode array.

In this way, when the output signal from one photodiode array is divided into two channels and transferred, there is a drawback that the output signal becomes unbalanced mainly due to variations in COD transfer efficiency between the two channels.

SUMMARY OF THE INVENTION An object of the present invention is to provide a one-dimensional photosensor capable of correcting output signal imbalance between both channels.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail along with examples.

FIG. 1 shows a block diagram of one embodiment of the invention.

Each circuit block in this embodiment is formed on one semiconductor substrate using known semiconductor integrated circuit technology.

In the figure, photodiodes 1 are shown as a representative photodiode, and when arranged in columns, they form a one-dimensional photodiode array.

Output signals of odd-numbered photodiodes in this photodiode array are successively outputted in parallel to the COD analog shift register 38 through a transfer gate indicated by symbol 2a.

On the other hand, the output signals of the even-numbered photodiodes in the photodiode array are successively output in parallel to the CCD analog shift registers 3bK through the transfer gates indicated by symbol 2b.

The above transfer devices 2a and 2b are constituted by MOSFETs (insulated gate field effect transistors).

Timing pulse φ. is its control signal.

The above CCD analog shift register (hereinafter simply KCCL)
) 3a and 3b are called registers 3a and 3b, which receive two-phase clock pulses φ1. In response to φ, the parallel pixel data are sequentially transferred and output in series. In this case, for example, odd-numbered pixel data is output from the CCD register 3a in synchronization with the clock pulse φ, and the clock pulse φ,
Since even-numbered pixel data is output from the CD register 3b, pixel data can be obtained according to the permutation of the photodiodes in the photodiode array.

In this embodiment, the two CCD registers 3a.

In order to correct the unbalance of the output signal level in 3b, K and MOS F as variable impedance means.
E T Q + −Q t is provided.

Special K IIIJ including but not limited to the above MO8FETQ.

Q is used as a semiconductor region ketone constituting the output nodes of the CCD registers 3a and 3b, and its occupied area is smaller than K.

In addition, in order to synthesize the odd number pixel data and the even number data in the semiconductor integrated circuit, the MO8FETQ, , Q
The source side of , is shared.

The pixel data synthesized by the common source is amplified by the preamplifier 4 and output to an external circuit. Above MO8FET Q+
-Qt gate electrode is connected to external control voltage OG, OG,
The operation of the MO8FETs Q, , Q, which are connected to the external terminals to which the signals are supplied will be explained according to the waveform diagram in FIG.

When the level of the output signal C from the COD register 3b is higher than the level of the output signal a from the COD register 3J1 for the same amount of received light.

By increasing the impedance of MO8FETQ, and using its resistance value and preamplifier 40 input capacitance, IIC
@Adjust. This adjustment can be made very easily by, for example, reducing the control voltage OG.

In the one-dimensional photosensor of this embodiment, the above M08)"
Even if there is variation in the output level between the above two channels within the level adjustment range of E i' Q 1 and Qt, it can be treated as a good product, so the product yield can be greatly reduced.
& as a result, significantly lower cost eI1.4/
I'm poor at trying.

fLM, the variation in the signal level between the two channels is due to the clock pulse φ1. It also occurs due to an imbalance in the rise characteristics of φ. Therefore, even if there are variations in the characteristics of the drive circuit that forms the clock pulse φ1゜φ, the user II
Adjustment of control voltage OGi, OQ* to T Qt −Qt
It also has the advantage of being able to relieve this more than IK. This facilitates the design and adjustment of the drive circuit, and reduces the overall system cost.

Furthermore, even if level padding occurs between the two channels due to changes over time, it can be easily adjusted.

Note that this invention is not limited to the above embodiments.

A fixed bias voltage, such as an internal power supply voltage, is applied to the gate of one MO8FETQ, and the gate of the other MO8FETQ is
An external control voltage OG may be applied to the gate of FETQ. In this case, there is an advantage that the number of external terminals of the semiconductor integrated circuit can be reduced by one pin.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a waveform diagram showing an example of the operation. 1... Photodiode, 2a, 2b... Transfer gate, 3a, 3b,... CCD register, 4... Preamplifier.

Claims (1)

[Scope of Claims] 1. A first transfer section comprising a -dimensional photodiode array, a CCD that receives output signals from odd-numbered photodiodes of the -dimensional photodiode array and outputs them in series; a second transfer unit composed of a CCD that receives output signals from even-numbered photodiodes of the dimensional photodiode array and outputs them immediately; A one-dimensional photosensor, comprising: impedance means having an MO8 structure provided in series with the output terminals of the second transfer section, and at least one of the impedance means is used as a flexible impedance. 2. The impedance means is the same as the first impedance means. 2. The one-dimensional photosensor according to claim 1, wherein the output node of the second transfer section is a drain and the source is a common MO8FET.