JPS5815491U - power conversion circuit - Google Patents

power conversion circuit

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Publication number
JPS5815491U
JPS5815491U JP10537081U JP10537081U JPS5815491U JP S5815491 U JPS5815491 U JP S5815491U JP 10537081 U JP10537081 U JP 10537081U JP 10537081 U JP10537081 U JP 10537081U JP S5815491 U JPS5815491 U JP S5815491U
Authority
JP
Japan
Prior art keywords
transformer
transistor
main switching
power conversion
switching transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10537081U
Other languages
Japanese (ja)
Inventor
広瀬 勝久
Original Assignee
沖電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 沖電気工業株式会社 filed Critical 沖電気工業株式会社
Priority to JP10537081U priority Critical patent/JPS5815491U/en
Publication of JPS5815491U publication Critical patent/JPS5815491U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の他励発振によるリンギングチョークコン
バータ電源の構成と電力変換回路を示す回路図、第2図
、第3図は従来の電力変換回路の実施例、第4図a及び
b11b図a及びb、第6図a及すは、第1図、第2図
、第3図の電力変換回路における主スイツチングトラン
ジスタの動作波形、及び負荷曲線の特性図、第7図は本
考案の電力変換回路と周辺部の実施例を示す回路図、第
8図a、 b、  c、  d、  eは第7図の動作
タイムチャート図、第9図a、  bは、本考案の電力
変換回路のターンオン、ターンオフ時の等価回路図、第
10図は、本考案の電力変換回路のスイッチ損を示す負
荷曲線特性図である。 la、  lb・・・・・・入力端子、2・・・・・・
フィルタ、3・・・・・・過電流保護回路、4・・・・
・・発振回路、5・・・・・・パルス変調回路、6・・
・・・・ドライブ回路、7・・・・・・電力変換回路、
7a・・・・・・リンギングチョークコンバータ用トラ
ンス、7b・・・・・・主スイツチングトランジスタ、
7C・・・・・・整流ダイオード、7d・・・・・・整
流コンデンサ、7g・・・・・・トランス、7e・・・
・・・コンデンサ、7h・・・・・・ダイオード、71
・・・・・・トランジスタ、10・五・・第1波形整型
回路、11・・・・・・第2波形整型回路、8・・・・
・・誤差増幅回路、9a、  9b・・・・・・出力端
子。
Figure 1 is a circuit diagram showing the configuration and power conversion circuit of a conventional ringing choke converter power supply using separately excited oscillation, Figures 2 and 3 are examples of conventional power conversion circuits, Figures 4a and b11b, Figure a and b, Fig. 6a and the characteristic diagram of the operating waveform and load curve of the main switching transistor in the power conversion circuits of Figs. 1, 2, and 3; 8a, b, c, d, and e are operation time charts of FIG. 7, and FIGS. 9a and b are circuit diagrams showing an example of the conversion circuit and peripheral parts. FIG. 10, an equivalent circuit diagram at turn-on and turn-off, is a load curve characteristic diagram showing switch loss of the power conversion circuit of the present invention. la, lb...input terminal, 2...
Filter, 3... Overcurrent protection circuit, 4...
...Oscillation circuit, 5...Pulse modulation circuit, 6...
... Drive circuit, 7... Power conversion circuit,
7a...Transformer for ringing choke converter, 7b...Main switching transistor,
7C... Rectifier diode, 7d... Rectifier capacitor, 7g... Transformer, 7e...
...Capacitor, 7h...Diode, 71
...... Transistor, 10.5... First waveform shaping circuit, 11... Second waveform shaping circuit, 8...
...Error amplification circuit, 9a, 9b...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リンギングチョークコンバータ用トランス7aとその1
次電流路に挿入される主スイツチングトランジスタ7b
とを有する電力変換回路において、トランス7gがもう
けられ、前記主スイツチングトランジスタ7bのコレク
タとエミッタの間にトランス7gの1次コイルとコンデ
ンサ7eとの直列回路が接続され、トランス7gの2次
コイルの両端の間にトランス7gの逆起動力を阻止する
方向に接続されるダイオード7hとトランジスタ71の
コレクターエミッタ回路との直列回路が接続され、トラ
ンジスタ71のベースにはトランジスタ71が主スイツ
チングトランジスタ7bのほぼスイッチング時に導通ず
るごとくパルス電圧が印加され、前記トランジスタ71
のオン、オフ動作により、前記トランス7gの1次側リ
アクタンスを変化させ、前記主スイツチングトランジス
タ7bのターンオフ損失、及びり二ンオフ損失を減少す
べく、逆起電圧の立上りの遅延及び放電々流の抑制をす
ることを特徴とする電力変換回路。
Ringing choke converter transformer 7a and part 1
Main switching transistor 7b inserted into the next current path
In the power conversion circuit, a transformer 7g is provided, a series circuit of the primary coil of the transformer 7g and a capacitor 7e is connected between the collector and emitter of the main switching transistor 7b, and a secondary coil of the transformer 7g is connected between the collector and the emitter of the main switching transistor 7b. A series circuit consisting of a diode 7h connected in a direction to block the reverse activation force of the transformer 7g and a collector-emitter circuit of a transistor 71 is connected between both ends of the transistor 71, and the base of the transistor 71 is connected to the main switching transistor 7b. A pulse voltage is applied throughout the transistor 71 almost during switching, so that the transistor 71 becomes conductive.
The on/off operations of the transformer 7g change the primary side reactance of the transformer 7g, thereby delaying the rise of the back electromotive voltage and reducing the discharge current in order to reduce the turn-off loss and the second turn-off loss of the main switching transistor 7b. A power conversion circuit characterized by suppressing.
JP10537081U 1981-07-17 1981-07-17 power conversion circuit Pending JPS5815491U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10537081U JPS5815491U (en) 1981-07-17 1981-07-17 power conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10537081U JPS5815491U (en) 1981-07-17 1981-07-17 power conversion circuit

Publications (1)

Publication Number Publication Date
JPS5815491U true JPS5815491U (en) 1983-01-31

Family

ID=29899907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10537081U Pending JPS5815491U (en) 1981-07-17 1981-07-17 power conversion circuit

Country Status (1)

Country Link
JP (1) JPS5815491U (en)

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