JPS58154240A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPS58154240A
JPS58154240A JP57036429A JP3642982A JPS58154240A JP S58154240 A JPS58154240 A JP S58154240A JP 57036429 A JP57036429 A JP 57036429A JP 3642982 A JP3642982 A JP 3642982A JP S58154240 A JPS58154240 A JP S58154240A
Authority
JP
Japan
Prior art keywords
chip
center
resin
lead
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57036429A
Other languages
Japanese (ja)
Inventor
Kazumasa Yamamoto
山元　一正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57036429A priority Critical patent/JPS58154240A/en
Publication of JPS58154240A publication Critical patent/JPS58154240A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To keep constant the interval between electrodes provided in the periphery of chip by deviating the center of tap plate connected to semiconductor chip from the center of resin sealed package to the side of extended lead wire. CONSTITUTION:The periphery of a tab plate 2 mounting semiconductor chip 1 is surrounded by a plurality of leads 3 which are guided to the one side of the tap plate 2. The pads 4 in the periphery of chip 1 and the internal end of leads 3 are bonded by gold wires 5 and the chip 1 and inner lead 3a are sealed by a resin material 6. At this time, the center of tab plate 2 is deviated a little from the center or resin sealing material 6 to the side of extended lead wires. Thereby, more inner leads can be provided opposing to the extended lead wires and the lead wires 3 can be extended in the same interval while the interval of pads on the semiconductor chip 1 can be kept constant.

Description

【発明の詳細な説明】 本発明は樹脂封止半導体装置、特に多ピン・シングルイ
ンライン形パッケージ構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device, and particularly to a multi-pin single in-line package structure.

現在使用されているシングルインライン形パッケージ半
導体装置は、第１図に示すように半導体チップｌを取り
付けたタブ板２の周囲を複数のり一ド３で取り囲み、こ
れらのリード３をタブ板２の一側面方向（矢印Ｘ）に導
出し、チップの周辺に設けたパッド（電極端子）４と各
リードの内端とを金ワイヤ５によりワイヤボンディング
（接続）し、チップとインナーリード部分３ａを樹脂体
６で封止しアウターリード部分３ｂのみを霧出した構造
を有し、リード導出方向Ｘを下に縦向きにプリント基板
に実装した場合、実装面積が他のパッケージ方式（例え
ばデエアルインライン形パッケージ等）に比して小さく
なることが有利であるとされている。In the single in-line package semiconductor device currently in use, as shown in FIG. The pads (electrode terminals) 4 provided around the chip and the inner ends of each lead are wire-bonded (connected) in the side direction (arrow X) using a gold wire 5, and the chip and inner lead portion 3a are bonded to a resin body. 6 and has a structure in which only the outer lead portion 3b is atomized, and when mounted on a printed circuit board vertically with the lead leading direction etc.) is said to be advantageous.

本来、樹脂封止半導体装置にお（・ては、半導体チップ
は樹脂体の中心になるように封止してあり、したがって
チップの載置したタブ板も中心に位置するように設計さ
れる。すなわち、第１図において、パッケージの短手方
向でタブ板２の両側面から樹脂体６の外側面までの距離
ｄ、＝ｄ、となっている。このためこの種のパッケージ
では、リードの導出方向Ｘｋインナーリードが集中し易
く、一方、導出方向と反対側ではインナーリードが大き
く屈折するためリード数も多くどれな（・。したがって
半導体チップにおいてもインナーリードに合せて電極パ
ッドを配置しようとすると、リード導出方向側にパッド
が集中し、その反対側のパッド数が少なくなり、設計上
困難であり、パッド配置の均衡上も好ましくない。Originally, in a resin-sealed semiconductor device, the semiconductor chip is sealed so as to be located at the center of the resin body, and therefore the tab plate on which the chip is mounted is also designed to be located at the center. That is, in Fig. 1, the distance d from both side surfaces of the tab plate 2 to the outer surface of the resin body 6 in the transverse direction of the package is d.For this reason, in this type of package, it is difficult to lead out the leads. Direction , the pads are concentrated on the lead lead-out direction side, and the number of pads on the opposite side is reduced, which is difficult in terms of design and unfavorable in terms of balance in pad arrangement.

しかし、チップにおける電極パッドの配置をバランスよ
くするために、リード導出方向と反対側とにインナーリ
ードな平均して配置しようとすると、一部でリード間隔
が狭くなり、又ワイヤ相互間の接触がおこりやす（これ
を避けようとするとパッケージ全体の寸法が大きくなり
プリント基板への実装密度に影響するという問題があっ
た。However, in order to balance the arrangement of the electrode pads on the chip, if we try to arrange the inner leads on the opposite side of the lead lead-out direction, the lead spacing becomes narrow in some parts, and the contact between the wires becomes small. (Attempting to avoid this problem would increase the size of the entire package, which would affect the mounting density on the printed circuit board.)

本発明は上記した問題点を解決したものでありその目的
は、シングルインライン形パッケージに従来のデエアル
インライン形パッケージで使う半導体チップをそのまま
搭載でき、しかもワイヤ相互間の短絡もない半導体装置
の提供にある。以下本発明を実施例にそって具体的に説
明する。The present invention has solved the above-mentioned problems, and its purpose is to provide a semiconductor device in which a semiconductor chip used in a conventional distributed in-line package can be directly mounted on a single in-line package, and there is no short circuit between wires. It is in. The present invention will be specifically described below with reference to Examples.

鎮２図は本発明による多ビン・シングルインラ５　イン
形パッケージを用いた半導体装置の一実施例を示すもの
である。同図において第１図と共通の構成部分は第１図
と同じ記号番号を使用し【いる。Figure 2 shows an embodiment of a semiconductor device using a multi-bin, single-in-line package according to the present invention. In this figure, the same reference numbers as in FIG. 1 are used for the same components as in FIG. 1.

この例においては、半導体チップ１を接続したタブ板２
の中心を樹脂麺止体６の中心位置より、リード導出側（
Ｘ側）へ若干ずらせることにより、チップ周辺の電極（
パッド）配置を均一間隔化したものである。すなわち、
パッケージの短手方向でチップを接続したタブ板２のリ
ード導出方向（Ｘ）側から樹脂体６外側面までの距離ｄ
、よりも、タブ板の反対側から樹脂体の反対側面までの
距離ｄ。In this example, the tab plate 2 to which the semiconductor chip 1 is connected is
from the center position of the resin noodle stopper 6 to the lead-out side (
By slightly shifting it toward the X side), the electrodes around the chip (
Pads) are arranged at uniform intervals. That is,
Distance d from the lead lead-out direction (X) side of the tab plate 2 to which the chip is connected in the short direction of the package to the outer surface of the resin body 6
, the distance d from the opposite side of the tab plate to the opposite side of the resin body.

をｄ、（ｄ、なるようｋするととＫより、反対側面側に
インナーリードなより多く配置することができる。これ
によって半導体チップはそのパッドの配置が均一な在来
のチップをそのまま使用することができる。If k is set to d, (d), more inner leads can be placed on the opposite side than K. This allows the semiconductor chip to be used as a conventional chip with uniform pad placement. Can be done.

なお、一つの例として、樹脂体の短手方向の幅力ｆ７．
６２　ｍｍのパッケージにおいてｄｌ　：ａ、＝１：１
．５程度が望ましい。As an example, the width force f7 in the short direction of the resin body.
dl:a,=1:1 in 62 mm package
．． Approximately 5 is desirable.

以上実施例で述べた本発明によれば、シングルイン・ラ
イン・パッケージにおいて、リードのレイアウトを余裕
を４．って行なうことができ、対応するチップのパッド
配置が均衡しているから、ワイヤ相互間の短絡不良のお
それがなく、デエアルインラインパッケージで使用して
いた在米のチップを搭載することができ、しかもプリン
ト基板に実装する一際に実装面積を小さくしうるという
シングルインライン・パッケージの利点を生かすことが
できる等その効果は多大である。According to the present invention described in the embodiments above, in a single-in-line package, the lead layout has a margin of 4. Since the pad placement of the corresponding chip is balanced, there is no risk of short-circuiting between wires, and it is possible to mount American-based chips that were used in the air in-line package. Moreover, the advantages of the single-in-line package, which can reduce the mounting area when mounted on a printed circuit board, are significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこれまでのシングルインライン・パッケージ形
半導体装置の内部構造を示す平面図、第１Ａ図は第１図
におけるＡ−Ａ断面を示す断面図、ｗ４２図は本発明に
よるシングルインライン・パッケージ形半導体装置の一
例の内部構造を示す平面図、第２Ｂ図は第２図における
Ｂ−Ｂ断面を示す断面図である。 １・・・半導体チップ、２・・・タブ板、３・・・リー
ド、６・・・樹脂封止体。 第　　１　　図FIG. 1 is a plan view showing the internal structure of a conventional single-in-line package semiconductor device, FIG. 1A is a sectional view taken along the line A-A in FIG. 1, and FIG. FIG. 2B is a plan view showing the internal structure of an example of a semiconductor device, and FIG. 2B is a sectional view taken along the line BB in FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Tab board, 3... Lead, 6... Resin sealing body. Figure 1

Claims (1)

【特許請求の範囲】[Claims] １、複数のリードを一側面方向のみに導出する樹脂封止
形半導体装置であって、半導体チップを接続したタブ板
の中心を樹脂封止体の中心位置よりリード導出側へずら
せることによりチップ周辺の電極配置を均−間隔化して
成る樹脂封止形半導体装置。1. A resin-sealed semiconductor device in which a plurality of leads are led out only in one side direction, and the chip is removed by shifting the center of the tab plate to which the semiconductor chip is connected from the center position of the resin-sealed body to the lead-out side. A resin-sealed semiconductor device with uniformly spaced peripheral electrodes.
JP57036429A 1982-03-10 1982-03-10 Resin sealed type semiconductor device Pending JPS58154240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57036429A JPS58154240A (en) 1982-03-10 1982-03-10 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57036429A JPS58154240A (en) 1982-03-10 1982-03-10 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS58154240A true JPS58154240A (en) 1983-09-13

Family

ID=12469566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57036429A Pending JPS58154240A (en) 1982-03-10 1982-03-10 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS58154240A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473514A (en) * 1990-12-20 1995-12-05 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559749A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559749A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Lead frame

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473514A (en) * 1990-12-20 1995-12-05 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5613295A (en) * 1990-12-20 1997-03-25 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5646830A (en) * 1990-12-20 1997-07-08 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5715147A (en) * 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board

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