JPS58154061A - Multimaster processor pass - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on the invention that allows a large number of microprocessors to communicate with each other and with various system resources (By-8t6III
This relates to a multi-master glossary pass that makes it possible to freely and inexpensively communicate with other users. That is, the present invention provides functionality tl! without modifying individual processors. It is possible to scale up the AK and thus contemplate very large computer systems that can be built with a large number of microprocessors.According to the state of the art, only one or more microprocessors can be used at the same time. Six processors share a common system bus
bug)1! - Many of the bus structures in use today, sophisticated and expensive direct memory access (DM) controllers, bus multiplexers, and controller resolvers, can only be shared by two processors. Current microprocessor system paths are extremely uneconomical in terms of utilization of path bandwidth.

When a microprocessor accesses a typical system, it waits on the bus until it receives or sends the desired data. Most microprocessors have a bus cycle time of 500 It's a small amount and it takes 1000 seconds. The actual data transmission task could be performed within a fraction of that period or so. While a given processor is waiting for its data,
It effectively locks out other processors from using the bus.

The i multi-master processor bus of the present invention has multiple
allows multiple processors to share a common system bus without causing conflicts, and
Little or no hardware overhead is required, only very simple software embedded within each processor board. Each processor is identical to the other in all respects mechanically, electrically, and (if desired) in firmware.

As a practical guide for assembly and testing, a limit of 8 master processors is chosen, but the theoretical Kt
iMore processors could be added to this system.

According to the invention, a backplane (ba
ekplan - A simple, standard network of electrical wires that interconnects the various system modules. The system controller consists of only two standard medium scale integrated circuit chips (MB2) that can be integrated into the backplane.

The present multi-master processor bus a, time-v Lunaplex packet-driven architecture (archit
By employing ``Ecure'' f, the effective bandwidth of the system bus is significantly increased. This architecture allows for unlimited global system resources,
It allows unlimited dedicated resources for each master processor and allows multiple multi-master processor paths to be interconnected.

More specifically, the present invention interconnects a plurality of processors t' with a plurality of cables each having a plurality of connection wires to a plurality of sets of processor module terminals for attachment to a plurality of processor modules. This relates to a multi-master processor bus. Cable: shall serve at least the following purposes: That is, interrupt request (tnt・rrupt r@qu-
est), interrupt ackn
owle4ga), address and control, time slice vector and clock, and data (est turtle)
It is. The clock means supplies a periodic inno (lotus),
The capacitor means is connected to the clock to generate a polyphase clock by counting the impulses thereof and daisy-chaining the cables and each module in series.
and means for connecting to the interrupt request cable and the interrupt acknowledge cable in parallel. The present invention also contemplates a data management method using multiple master processors with parallel cable connections to the bus. According to this method, one of the master processors has a master processor for specifying which processor is activated to receive data or to output data to the other processor. The system according to the invention provides a master processor module in which the processor is arbitrarily selected as the processor, in which case a time slice signal is provided to sequentially allow access to the bus by each processor, one at a time, in a repeating sequence. The master processor module consists of a processor, a global resource module, a system timing controller, and a backplane.
)/Write memory, input/output devices, and some combination of control logic. These components are specific to the processor. This processor module includes an interface to the system bus. A global resource module, read-only memory (ROM), read/write random access, that only the processor module has access to on the system bus.・Memory (RAM), input and output devices,
It also includes an interface to the system bus, which may be any combination of processor subsystems and dedicated processor subsystems. Global resource modules cannot access the system bus unless specifically requested by the master processor.

The system timing controller consists of a master clock and logic that forms the N-phase system clock encoded in the 10fln bitfield. This logic is preferably integrated into the backplane bus circuit board. A simple linear array of sockets and interconnects for the system, this backplane contains various system modules, in the order i', e-r, Any number of plug-ins can be plugged in as long as the setter limit number Ml is not exceeded.

Another feature of multi-master processor bus systems is that each system module can operate asynchronously with respect to each other. However, the system bus cane synchronous bus is 0 multi! Starb p Setsabasu Ha, also called "Global Basuto".

Each master processor module may be a self-contained computer that can operate even when not plugged into a multi-master processor bus.

Referring to FIG. 1 in its entirety, there is shown a schematic representation of the Multimiscoop 47Tsabas system. In the same figure,
Processor module 10a.

10b and 10c are shown in the figure, but up to 10* modules are further provided. Similarly,
Although resource modules 12a and 12n are shown, 1. There may also be intermediate resource modules between them. As described above, it is connected to the multi-master processing bus 40 in response only to an action or a command from the processor module 10''+10%10c or the like.

The multi-master processor bus 40 consists of a plurality of i multi-wire cables.

One of these cables connects to the bus 14 for time slice vectors and clocks.
In contrast, connections are made from the various modules described above by means of connection lines. That is, processor module 10
1L is connected by a connection line 14a.0 resource module 12a is connected to a bus 14 by a connection lit 141).
connected to. The processor module 10b is connected to the line 14
The Setsuna module 10c is connected by a line 10 (1). The time slice vector and clock bus 14 is connected by a line 10 (1).
It receives input from a counter 16 triggered by a 6 MHz clock 18. Output of counter 16,
(buffers pin 18) (applied to pin 20).

This buffer 20 has a number of 2 buffers related to the number of master processor modules used in the system.
A count signal consisting of leading pulses is output onto the time slice vector and clock bus 14, thereby making it possible to apply the count signal to each of the modules. The above cuff/) (No. i a,
It is decoded by circuitry within each master processor module in a manner described below.

This multi-master processor bus a, an interrupt 4 affirmation bus 22, and an interrupt request bus 24 are also provided. The interrupt request signal can be generated by any of the modules mentioned above and connected to the connection buses 24a, 24b, 24c,
This interrupt request signal, which may be applied on the interrupt request bus 24 by interrupt request buses 24a and 24n, is provided by the interrupt request bus 24 to the input of the first processor module 10a via bus 24xf. Thereafter, this interrupt request signal line is sequentially transmitted in a daisy-chain manner between the master processor module and the resource module in a conventional manner as shown in the figure. The interrupt request signal is typically generated by the h resource module, but could also be generated by the master processor module.

An interrupt acknowledge signal, which can be generated by any master processor module, is connected to lines 22m, 22e,
22a, etc., onto the interrupt affirmation bus. The interrupt affirmation bus 22 is for input/< bus 221 K! It is connected to the star processor module 101, and this master processor t(J) Neil 10aQ, 9 source module 12aK! by bus 22xa! It is connected to other modules in a daisy chain.

The data bus 26 and the address and control node 2B constitute the essential bus Tov, each of which has bus connections to the modules described below. That is, both paths 26 and 2
8 are connected to the resource module 12a through the connection cables 26a and 28a K through the processor module 10a[, cable 261) and 2B'b, and to the processor module 1 through the cables 26c and 28C, respectively.
01), connection cables 26n and 2 are connected to the processor module 10c by cables 264 and 28+1.
8n to the processor module 12n. The multi-master processing bus architecture illustrated in FIG. 1 supports a very powerful operating system with extremely small dimensions and relatively simple overall configuration. The above-mentioned multi-master processor bus signals require various numbers of lines in the global bus. Typically, the following numbers of lines are required for the following signals. That is, 23 for address and 1 for data.
6, 3 for time slice vector, 1 for device busy, reader e-strobe (Up
er Byta Data 5 trobe), 1 for reset, 1 for crowbar master 16 megabyte look, and 1 for data, making a total of 56 group interrupt affirmation daiseach.

Each master processor module 10a, 10b,
IQc, iQna is a self-sufficient computer system.It is preferred, but not necessary, that each master processor module be identical to all other modules. Encoder means (not shown) in conjunction with the system of counter 16, clock 18 and buffer 20 for assigning the time slice to a given master processor.
is employed, thus each master processor module is given an individual time slice.

System initialization
At this time, each master processor module initializes its own system components. These system configurations may include a universal asynchronous transmitter/receiver (UART), a parallel input/output device (P/O), etc. At this stage, each master processor module then reads its time slice encoder and transfers the information and instructions to the other master processor module #Kjl at the relevant location (Jvr defined point) in the global memory. Determine if you can be treated as such. Each master processor module then clears the locks and global memory on its own instructions and sends the other processor modules a#! A flag that signals that the starp processor module is present and functioning properly.
Set k.

A master processor module that gives zero time slices by any selection is designated as a master processor module. This master processor module is responsible for the system superpipe and is responsible for initializing the global resource modules within the system. The master processor module also assigns various tasks to other master processor modules as needed. After each master processor module completes its assigned task, it enters a free loop, where a new task can perform the lock and global memory operations for 1 h.
A book to check as you get it. □This instruction block is a segment of memory set up by the master processor to allow communication between the various master processor modules, containing the instructions and program and data structures needed to accomplish a task. It contains a pointer that indicates the , and a status word.

The various master processor modules mentioned above are connected to other master processor modules in a so-called "daisy chain" 11K. Master Master Processor Modineal, if it interrupt request daisy chain 24x, 24za, 24xb, 24xc,
If it were the first master processor module in 24xd, -, 24xn, it would always enable interrupts to itself and prevent the interrupt request signal from propagating through the daisy chain to the other master processor modules. It can be used to handle all global interrupt requests by inhibiting them. The master master processor': the Samogener then performs the system functions required before assigning a master processor module to process the task generated by the interrupt.

A master master processor module is simply a supervisor by default and may transfer its system privileges to any other master processor module at any time and for any reason. For example, it can detect errors in internal hardware and trigger changes.

Each master processor module uses a "backdoor J" to enable the system to recover from catastrophic errors.
For example, it is possible for a master processor module to experience a severe failure. This capability allows the remaining nine master processor modules to issue a new master processor module and ignore a failed master processor module. Perhaps some master processor module will access a global resource module that was always busy. This condition could then lock the master processor module with no output available for timeout. Each master processor module is also configured to allow the master processor module to disconnect itself from global bus transactions (zrans*act, ton) in the event of a major failure on the bus. It should also have an internal timeout capability.

It should be noted that there are other ways of operating the system of the present invention, and therefore the above description is intended to be an example of what may be done. Processor module, HL F
i MOtOr-o1a6B,000 is an example of an interface with a master processor module using a microprocessor.

Referring to FIG. 2, the illustrated structure is one example of an interface between a multi-master processor bus and a master processor. As seen in FIG. buffers 3Qa, 30b and latches 52a, 52b
It is connected to the global bus 40 via f. Both buffers are conventional buffers used to connect and to some extent separate individual processors and four-way paths. Both latches are registers used to latch data from the global bus during each processor's time slice. An internal cable connects to the buffers and latches via the processor cable 54t, and a cable 36 connects the buffers and latches via the global data exchange cable 54t to the buffers and latches (multi-master processor bus or global bus 4).
Connected to 0.

In addition to the data exchange for the systems described above, a series of buffers 42a, 42b, 42c is provided between the address bus 44 common to this processor and the output cable 46 to the global bus system. . The group address contact is cable 4B to the multi-master processor bus or global bus 40.
It is through this system that global resources are addressed and selected. t+,
A global control module, which may be related to processing factors for other procedures handled via buffer 50vi, is associated with the multi-master processor bus via global control 52ts.

Global interrupt request daisy chain inputs and outputs are represented by lines 58 and 56, respectively. If this master processor::1° submodule does not support interrupts,
These lines will be connected, thus passing global interrupt requests to the next module. If this module is to support global interrupts, Figure 4 provides an appropriate circuit diagram.
The loop 60 is a 4hO that supplies the 16 mech clock from the global bus to the interface logic as needed, the global path t, and the 03-bit count signal (GT13V2. GT8V1. GTsvo) 1 is connected to a comparator 64 which compares it with the characteristic time number of the module encoded by the dip switch 72. Buffer 66t! , the processor in the Todoroki master processor module is set to DIP switch 7.
It is possible to read the numerical value 1m coded by 2. If said number of modules matches the count signal on said global bus, the output signal 78 will be low active (IOW active-e) and this master processor module will access the /a-pulse bus; For example, data (D8)'t
If it wishes to access or respond to a global interrupt (TAK Global Request), the processor will cause line 82 to become active. Thus, OR gate 80 has an output (when low) indicating that this master processor module wishes to access the global bus, and that the count signal is aligned with its own module number. - It corresponds to the level A11D gate. The output of OR gate 80 is latched by DW flip 70 knob 86. The presence of an output at the Q and ζ terminals of this free lag flop 86 indicates that this master processor module has requested and been granted a valid (Tall) global request (VGRi or VGR). .

If a modi master processor module is trying to write data to a resource module via the global bus, this master processor module
Read/Write to OR gate 88 *'i Low causes 0 Thus, if this master processor module is granted valid global requests,
And if the request was to write data, the output bus causes the signal BIN from OR gate 88 to be active low. The BIN signal enables data bus buffers 30a and 30b to pass data from the module's internal data bus 34 to global data bus 58. Further, the VGR signal from the 7 lip-flops is sent to the address buffers 42a, 42.
b, 42c and control buffer 50 allow address and control signals from address bus 44 and control bus 45 of the master processor module to pass to the global address control bus.

If the resource module addressed by this master processor module was capable of receiving data i on the global data bus, it would not send a signal to the GBUaY line 92. track 92
The above "not busy" signal is applied to the D-type flip-flop 960D input terminal and recorded in the 7-lip flop 96 by the VGR signal from the 7-lip flop 86. flip 70 knob 9
The output of 6 is the write non-read signal W from the processor.
/ Page OR after passing through AND gate 98 when there is R
100Th and generates a low active data transfer affirmation signal DTAOKi on the line 106.

This DTAOK signal is used to notify the processors in this module that a transaction on the global bus has completed. on the data bus.

If the data (to be read) and the data from that resource module is ready as indicated by the presence of a glow signal on line 94, then the module is read at the end of the current time slice. A positive going signal is generated on the output of the gamer 90. The output signal from AND gate 90 is used to record data from the global data bus into all latches 52a and 52b.

The global ready signal (GRDY) signal on line 94 is also recorded on DI17 lip-flop 102. The output of the flip 7 tab 102 is applied to one input of a mund gate 104. A read/write signal R/W from the processor is applied to the other input of MD gate 104 to produce an output signal.

Output signal light from MD gate, NOR gate 100
to generate a DTAOK signal that is used to indicate to the processor that the read from the global resource module has been successfully completed.

1Ii2 system design, associated with the system of FIG. It shows the logic circuit used to pass the line Ke below. This circuit is a relatively simple circuit consisting of a block flop 180 controlled by a processor to direct the global interrupt request G, R, and N signals. 7
Depending on whether the q output terminal of the lip-flop 180 is low active or the Q output terminal is 4-active,
OR gate 182 or 184 converts the groupal interrupt request daisy chain input signal (G RQ N) to the global interrupt request daisy chain output (GIRQ 0U
T) i-ha is to be passed to the interrupt request line (IRQ) of the module processor.

1/ES Figure B is an example of the interface logic required to create a global resource module. In this example, the butterfly module is a memory module that does not have the ability to request global interrupts. At this point, it should be noted that each module responds to an 8-bit address field, the most important 8-bit address being the module address. This logic includes a delay line that is used to match the bandwidth of the incoming request to the bandwidth of the memory device.

As in Figure 2, access in Figure 3 to global bus 40 is via global data line 38, or via global data and control line 48152K. Global data expansion is provided via buffers 112a and 112bt- or via registers 114a and 114t+t-. Data is sent from RAM array 120 via internal data bus line 54t-O11! Issue commands and write commands are provided via nine internal R/W lines 51 which are also connected to registers 114a and 114b. The address directed by the master processor is
Global address and control line 48A2
registers 116a,1
16b, and 116C. These φ registers store the address indicated by the master processor, whichever register is selected. Key data indicating the module number of the master processor module performing the read or write request is sent from register 116a to terminals BO, BL, and B2 of comparator 122. This comparator is
Mojico -k (Q Compares the number with the current count signal, and when the comparison result is positive, the line output signal (vector ox
) t- arise. At the same time, the continuous non-write signal R/W is inverted by the inverter 124 to become a write non-read signal vr7x, which is applied to one terminal of the OR gate 126. This OR game) 126, the above W/
This is for passing the R signal or the vector OK signal from the comparator 122 through NA.

Global address information module 0 comparator 11 sent from global path line 48 to comparator 11'j-
8 is 4 which also provides an output tube when the global address matches the fixed module address, i.e. the wired module working address. The low active output from comparator 118 is inverted by inverter 162 to three-person cam MD gate 134.
is sent to one input of The output a of this system ND gate 134 is sent to the clock terminal of the Dll block 70 block 156, and is also sent to the registers 114a, 116b, 11+6e, 114a as a strobe (87RB).
and 114b are sent to the µsock input. When the master clock signal (MCLK), the module select (output from 132), and the not-busy signal (BE)
56 with a clock. The non-busy signal (BU8Y) is a high active signal V which is driven by the ND gate 134 when the flip 70 knob 156 is fixed to the D terminal.
A busy signal BD8Y is generated at the q terminal of flip-flop 156 at the same time as the 0 generated at its Q output when x is present. This Bt18Y signal is
11D gate 128.

Bυ from delay line 138 and flip frog 156
8Y signal is received and this signal is sent to the 7 lip-flop 140.
delay by a fixed amount of time before applying it to the clock input of The Q output of flip 70 tube 140 is applied to the third input terminal of MD gate 128. When all S signals are present at the input of the MD gate 128, the MD gate output signal (DONIC) is generated. This output signal is applied to the D input terminal of the ti7 lip 130. Then, when the operation is completed, 7 rip 7
The clear signal from the Q output of 0 knob 130 is applied and 7
Clear lip 70 tubes 136 and 140t.

The output of flip-flop 130 provides a trip complete signal, which is applied to the 10,000 input of each of Num MD gates 144 and 146. These H
AND gates 144 and 146 generate output signals global data ready (GDRI)Y) and buffer enable (B[)FFN)), respectively. BT31
P11N allows buffers 112a and 112b to put data onto the global data bus.

1IN4 Zusha is an example of an interrupt request interface. This interface may exist in the global resource module or in the master global module. If a module requests an interrupt, it must have an interrupt vector ready signal on its internal data bus 34. Once an interrupt vector is requested, this interrupt vector is stored in buffers 112a and 1121).
and global data connection58 via the output cable.
and then the master processor bus 4OK. Low active tag - Valve vector request G engineering V
The RQ signal is inverted via an inverter 148t, and the H
BIIJ is applied to one terminal of AND gate 150.
t-formation (used to enable buffering),
,lt,,t, are applied to one terminal of NAMD gate 152 to form a low active global device ready signal ()I)R'DY_t- at its output. Each of these NAND gates also has a low active input signal AOK'i indicating an interrupt affirmation. The master clock provides an input to the clock terminal of the D-type flip-flop 154, and an IRQ signal is input to the terminal. If an interrupt request exists, Dm7'
An output is generated at each of the Q terminal and the Qj11 child of the Jpf μtub 154, and each of these outputs is connected to the OR gate 1.
56 is applied to one terminal of 160.

The signal from the OR gate 156 (low active) will clear the interrupt request slip 70 tab 158. The 7 rig 70 tube 158 receives an edge signal from a device installed in the module at its clock terminal, receives a constant voltage level Vxf at its D terminal, and issues an interrupt request to its Q child.
i - arise.

OR gate 160 also receives global affirmative act signal GI
KOUT'lj glow-24 transmits to the bus. When the interrupt request request RGL is generated in the interrupt request signal 70 and the interrupt request request RGL, the signal is sent to the inverting amplifier 1 which forms the low active global interrupt request signal G request RQt.
62 to the global bus.

Figure 115 shows a backplane mt showing some of the connection details of a multi-master processor bus, or so-called "global bus", which has been shown generally as member 40 in other figures. This backplane provides plug-in terminal connections for circuit cards, and a To9, typically 12 card backplane assembly will fit into a standard 19'' equipment rack. This backplane design allows for a full 2 inches of mechanical mounting overhead. The schematic diagram of FIG. 5 shows the connection to the chip side of the board connector. Connections only to the front side of the system, i.e. approximately 6 of the 5 circuit boards for each processor tK.
Only one part is shown. It should be understood that the other terminal arrays are also similar to the one shown in the figure and have a similar arrangement, but the connections are different. When removing some system boards, pull-up resistors are used only to round off some of the control signals generated by open collector gates, or to generate fault signals and inactive command signals. Ru. The lines between the terminal connections are shown in Figures 1 and 2.

The illustrated blocks 170, 172 and 174 represent the count signal generator or system controller. Reset in the system is controlled via a reset switch, which is connected to a voltage divider consisting of a resistor 166 connected to a 5 volt voltage source and a capacitor 168 connected to ground. This signal is applied to the inverting amplifier 164 to generate a signal GRI indicating that there is no global reset.
811iT t - 0 to generate, but usually GRIC
The 81CT signal is generated from the amplifier, but its compensation is also generated when the reset switch is used. If there is no reset signal, block 170.
A count signal generator consisting of 172 and 174 is activated. Multi-master processor bus, i.e. global 7'.

The Sessa Pass 400 backplane consists of five groups of circuits on each collar of the board. These circuits are represented by connections between the terminal points of the diagram in Figure 1M5 and represent one-third of the circuitry on the integrated circuit side of the board. this"
Using the ``daisy chain'' effect, you can
The boards of one row or column are connected to the boards of the next column to provide a sequential transfer effect. Board connectors are 176a, 176b, 176c, 176
They are arranged in rows or columns as indicated by a, 176e, through 176n. Inputs to the various boards have predetermined values that are transmitted directly or sequentially by the work activities displayed on the various cards! A fixed voltage source with a resistor 178 and a variable voltage source are included to apply voltage to the input of the first panel.

Operation jI [Il The present multi-master processor path system has 1) 500 MOs with a typical bus cycle time of 4 seconds.
It is based on a 68,000 microprocessor. The system timing controller is this soo 4! - Divide the second period into eight 62.51 second periods, each corresponding to one processor mino module. This time slice vector is generated by dividing the 16 MHz clock with a t-3 bit counter.

Therefore, the counter will produce a 3-bit number ranging from $0 to $7. Each state of the counter has a period of 62·5-seconds. This stnoicle is repeated every 500≠seconds.

Each master processor module will have a 5-bit dip switch that is continuously compared to the time slice vector or count signal. Key:
1. If the sum occurs, then its given procera? The main Joule is allowed access to the system if he so desires. This 3-bit encoder can be read by the processor and allows software embedded within the module to know whether the processor module is a master master processor module or just a master processor module. It is used to enable t. If it is a master processor module, it will be responsible for system responsibilities such as initialization until it decides to hand it over to another master processor module.

In this case, assume that the other master processor modules initialize their own subsystems and then silently wait for instructions from the master processor module.

data to global-resource module i.e. G
A master processor module desiring to write RMK will wait until its time slice occurs. When this time slice occurs, the master processor module will place the address and data on the bus. GRM compares the addresses with their own addresses. And if selected and the 90RM is not busy, this GRM latches the address and data from the path and begins processing requests. If the selected nine GRMs are already busy,
The processor must wait until the next time slice before it can issue its request again.

If a master processor module desires to read data from a GRM, it puts its line address on the bus. If that GRM is not busy and is 9, it will latch the @GRM wand, its address and the current timeslice vector or count value.

This GRM will then process the request.

If this GRM has a valid data ready, it will have a timeslice vector equal to the stored value. The GRM will then put the data on the bus and send a signal to the data ready line.

The master processor module then latches the data and continues its work. If the GRM is initially busy, it will wait until it is granted access to the master processor module bus.

There is no direct access to memory or DMA on this bus. It will be considered a DMA device line master processor. and will contain its own time slice.

All global requests are routed as a common interrupt request line.
"OR contact" will be made. This signal light is then daisy-chained through all processor modules. Each processor may accept or reject this request. If the request is accepted, this signal is not propagated through the chain. Otherwise, the request line continues through the chain.

Upon accepting the above request, the processor will generate an interrupt acknowledge that is "OR'ed" with the ACK signal from the other processor, and the signal is then sent via the interrupt requester. It is transmitted in a daisy chain. The first interrupt requester in the chain that requested an interrupt will accept the above IMM0Kt-, and the IA of
OKd is suppressed from persisting through the above daisy chain.

During the next bus cycle, the accepting processor will generate a vector request signal during that time slice. The module making the request then
It sends out a vector of bits on the path and also issues a data ready signal. The processor then connects the bus T
The vector of he will be latched.

If the module making the request does so on an interrupt request,
This module considers itself tL''- and will not accept any other requests until its requests are accepted and fulfilled.

Figure 6.7.8 is intended to illustrate the operating dimensions of the present global system.

FIG. 6 shows a write sequence for the fifth master processor module that embodies the following steps. Generate a global request. (Start); 2.5@th MPM a, wait until its time slice occurs; 5-5 u I) MPM Ia, sends address, data and control signals onto the global bus: 4.59th MPM encounters a busy signal generated by the addressed GRM; 5.5th MPM writes data into the addressed GRM, assuming the addressed GRM is no longer busy. Figure 7 shows that the second M must wait until its next time slice.
0 1. The second MPM internally generates (starts) a global request to read data from a particular GRM.
2. The second MPM waits until its time slice occurs; 6. The second MPMa sends address and control signals on the global bus; 4. If selected, a busy signal is sent by the GRM. If so, 2
The second MPM waits until the next time slice occurs; 5. If the data ready signal is sent out, the second MPM fetches the data from the global bus. 0 indicates a global interrupt sequence such that a system module (master or resource) generates an interrupt request signal (star);
4.2.0th MPM
responds with an interrupt acknowledge signal (MCK); 5.01i-th Q The MPM then waits until its next time slice occurs. After that, the side-in vector request signal (
data strobe (D
8) Disable the signal; 4. The module making the above request puts its interrupt vector on the global data bus and sends out a data ready signal; 5. The 0th MPM receives the interrupt vector from the global data bus. [Latch and invalidate the interrupt affirmation signal and vector request signal.

The systems illustrated in the above schematic drawings are intended to be representative only.

It will be apparent to those skilled in the art that many modifications may be made to the illustrated embodiments. All such modifications are intended to be within the scope and spirit of this publication.

[Brief explanation of drawings]

The attached drawings show preferred embodiments of the present invention.
, FIG. 1 is a schematic overall block diagram of a multi-master processor path in a connection system, showing the connection state of a plurality of processors, and FIG. The detailed schematic block diagram, FIG. 2A, is a block diagram illustrating the interrupt request enable (enabxe)/disable portion of the processor module, tIIL.
FIG. 5 is a similar block diagram of an example bus/resource module interface; FIG. 4 is a block diagram showing another example of a bus/resource interface; FIG. 6.7.8 is a schematic diagram illustrating a multi-master processor bus backplane illustrating certain block input elements; FIG. 6.7.8 is a diagram showing the relationship of various signals with time in each multi:: master processor path stem .

Claims (1)

[Scope of Claims] 1. A plurality of processor modules each having a processor and an interface circuit; connected in parallel to the interface circuit of each of the processor module and the resource module; a groupal bus system for communicating between a processor module and the resource module; and system timing means for dividing a predetermined pass cycle time period into N equal time slices. , a synchronization layer data processing system 02, wherein each of said processor modules is allowed access to said global hash system for one time slice leap during each bus cycle time period; The module numbers from module KO to summer-1 are assigned in order, and the numbers from KO to M-1 are assigned to each of the above-mentioned time slices in order, and each processor module is given the above-mentioned number in the time slice corresponding to its module number. Claim # consisting of allowing access to the global bus! 1. The data processing system according to claim 1, wherein the system timing means includes a rounding counter for generating a continuous repeating count signal up to O or 6M -1, and the counter transfers the count signal to the global path system. and receiving the count signal in the interface circuit of each of the processor modules, and when a count signal corresponds to the module number of a particular processor, the global
Claim #! comprising a decoder circuit for allowing access to the path system. Data processing system O according to item 2 Naf 4, said predetermined bus cycle time period Ytsoo 71
3. The data processing system according to claim 2, wherein the data processing system is a second. 5- [e/global bus system with a time slice and clock bus, a data bus, and an address bus, such that each bus has multiple connections;
A data processing system according to claim 1 or 4, wherein all of the processor modules have the same structure, and all of the module numbers are assigned in an arbitrary manner. Data processing system as described in Section. 7. The data processing system according to claim 1, wherein each of the first four modules is completely self-sufficient and can itself operate asynchronously with respect to the global bus. 8. A method of operating a synchronous data geography system having a plurality of processor modules each connected to a global bus system via an interface circuit, the method comprising: dividing a given bus cycle time period into X equal times; A method comprising: dividing into slices; and allowing each processor module access to the global bus during only one time slice during each bus cycle time period. 9. sequentially assigning a number from 0 to N-1 to each time slice; sequentially assigning a module number from 0 to N-1 to the processor module; and the number of the time slice. Corresponding to the module number, when the processor module with that number is
1. The method of claim sga further comprising: allowing access to a tallopal bus; 10. The patent further comprises: generating a count signal corresponding to the time slice number; outputting the count signal to the global bus; and comparing the count signal with the module number. The method according to claim 9.