JPS58153487A - Semiconductor switch - Google Patents

Abstract

PURPOSE:To decrease the number of electric wires which are necessary for wiring even in case the loads are separated from each other, by providing a data receiving part to each load, and unifying the data receiving part with a semiconductor switch part, and making it into an IC. CONSTITUTION:The signals formed into time series are sent to data receiving parts Rd1, Rd2- through a data transmission line Dp. These data receiving part is provided to each of loads P1, P2-. A data receiving part Rdi decodes a coded signal and recognizes the ON/OFF commands of loads P1-Pn. In this case, the part Rdi and a transistor TRi are formed on a semiconductor switch to obtain a monolithic IC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor switch that integrates a data receiving section that receives a coded signal and recognizes a command regarding its own device number, and a switch section that opens and closes a load.

In vehicles such as automobiles, airplanes, and trains that have a large number of loads in a limited space, the wiring that connects the switches and the loads tends to be complicated.

If the amount of wiring is large, there are many disadvantages such as requiring extra space and increasing the weight of the vehicle.

FIG. 4 is a circuit diagram of a conventional switch and load.

Switches Swl, , ..., Swn and load p
1, p2.

・・・・・・・・・Pn and each power supply El,
E2, ..., En are connected in series. In the simplest circuit, the i-th switch, load, and power supply are integrated into one, and each is isolated.

Although it is simple, in automobiles and the like, the switch and the load are quite far apart, so the cable between the switch and the load is long. In this method, long cables must be provided in proportion to the number of loads. Since this is a power line, it is thick in diameter, heavy, and bulky. As the number of electrical components in automobiles and the like increases, the number and weight of cables used to control them also increase.

Increasing the number of cables reduces the space inside the car and increases the weight of the car. With the development of electronics, the number of electrical components continues to increase, so it is necessary to find ways to reduce the number of cables.

FIG. 5 is a circuit diagram of a conventional switch/load. This does not directly connect the switch and the load. Instead of a switch, use a (power) transistor, etc.
Tr2. Connect ... to the load and power supply. transmit a coded signal, thereby causing loads p1,
p2, . . . are controlled.

The data transmitter DT encodes the open/close states of the input switches Sw, which are equal to the number n of loads, and transmits the encoded data.

Assuming that the number of loads is n, it is sufficient to specify the on/off state of each of the four loads that are controlled. A 1-bit signal is sufficient for each load. Coded data refers to data obtained by replacing signals for specifying the state of each load in time series.

The data transmitter DT includes 1. The old... has an encoder function that converts the open/closed state signals of the n switches from parallel to serial and expresses them into one frame of pulse train.

A known signal transmission format is used. As shown in Fig. 6, there is a voltage signal that represents 'o'9 and '1' for each load. For example, L level "'0" C, switch off, H level "1" Corresponds to switch on. Or, the reverse is also possible.

Furthermore, as shown in FIG. 7, each load state may be designated by the width of the pulse. A wide pulse can represent a switch on, a narrow pulse can represent a switch off, and so on. Of course, the opposite is also possible.

The data receiving section Rd receives a coded signal from the data transmission path Dp and decodes it. That is, a time series signal is converted into a parallel signal, and an opening/closing signal for each load is given to a semiconductor switching mechanism consisting of (power) transistors Trl, . . . , etc.

In this way, the transistor for the load to be driven is made conductive and the other transistors are made non-conductive.
The data receiving section Rd controls the switch mechanism.

With such a circuit, it is only necessary to connect the data transmission section DT and the data reception section Rd with one data transmission path Dp, so that many power lines can be omitted. There is a possibility that the wiring harness can be saved more than the individual control method shown in FIG.

However, each load P1. ...Pn are often not present close to each other. The ground wire is not shown in this figure. The frame of the vehicle body can be used for grounding, but in some cases a separate grounding wire may be required. If each load is separated, the control wiring Ll, L2, etc. connecting the data receiving section Rd and the load
・Ln becomes long. For this reason, there are many cases where the amount of wiring cannot be reduced that much.

The present invention aims to solve these drawbacks. The semiconductor switch of the present invention also includes the aforementioned data receiving section Rd.
The feature is that one is provided for each load and integrated with a semiconductor switch section (for example, a power transistor) as an IC.

FIG. 1 is an example of a circuit diagram of a semiconductor switch of the present invention.

Switches Swl and SW2 for controlling the load
.

..., Swn gives an input signal to the data transmitter DT. The data transmitter DT is the same as the previous example, and converts the open/close (binary) signal of the switch from parallel to serial.
It is a time-series (coded) signal. This is the 6th
Using an appropriate signaling system, such as that shown in FIG.

The time-series signals are transmitted through the data transmission path Dp to the data receiving units Rdl, Rd2 . Sent to...

The data receiving section is not single, but each load Pi, P2
.

...... especially provided.

The transistor Tri that controls the load Pi is provided with its own data receiving section Rdi.

The internal mechanism of the data receiving section Rdi is the same as that of the data receiving section Rd shown in FIG. This decodes the coded signal (serial-to-parallel conversion) and calculates the load p1, for device numbers 1, 2, mountain..., n.
p2, ...... Recognizes Pn on/off commands. All data receiving units Rdi receive all device numbers 1, 2 .・・・・・・Recognizes the command for n, but only the output terminal of your device number i,
It is connected to the transistor Tri. Remaining output terminal 1. ......, (i-x), ni-m,...
....

n is not connected to anything.

The data receiving section Rdi and the transistor Tri are integrated into one IC.

That is, the data receiving section Rdi and the transistor Tri are configured on one semiconductor chip, and are implemented as a monolithic IC.
It is possible to do this.

Further, the data receiving section Rdi includes a semiconductor chip, a resistor,
It consists of passive elements such as capacitors, and transistors Tr.
i can also be made of a semiconductor chip and mounted entirely on a ceramic thick film printed circuit board to form a hybrid IC.

The configurations of the data transmitting section and the data receiving section are well known;
For example, the circuit diagrams shown in FIGS. 2 and 3 can be used.

This is an example of transmitting and receiving a 16-bit signal.

FIG. 2 shows a circuit diagram of the data transmitter.

The data of the desired switch Swi is parallel input data 1
The signal is input to the 16-bit latch circuit 2 as follows. The number n of loads is allowed to be up to 16.

The 16-bit latch circuit 2 has device numbers 1, 2°...
. . , the on/off signals for n are stored as "0°" and "1" signals. This input signal is transferred to a 16-bit shift register 3.

A pulse with an appropriate pulse width is generated via a clock pulse generation circuit 4 and a frequency division circuit 5. This is converted into various pulses by the timing pulse generation circuit 6.

The frame pulse generation circuit 7 generates a pulse that defines the length of a frame including all one set of time-series signals.

The parity pit generating circuit 8 aligns the parity of each signal in one frame, so that erroneous signals can be detected.

The timing pulse generation circuit 6 outputs a load pulse to transfer the input signal of the latch circuit 2 to the shift register 3. Next, the timing pulse generation circuit sends a shift pulse to the shift register 3. The input signal in the shift register is sent to the next bit one by one, and then sent to the encoder circuit 9.
Go out in order.

A parity signal 10 is finally sent to the encoder circuit 9 from the parity pit generation circuit.

In this way, the transmission data SD is created, and the data transmission path Dp
It is transmitted by. Data transmission path Dp
It is also possible to send electrical signals as they are using coaxial cables. Further, it is also possible to use a light emitting diode and a laser diode in the transmitting section, a photodiode and an avalanche photodiode in the receiving section, and construct the data transmission line Dp with an optical fiber cable.

An example of the circuit of the data receiving section is shown in FIG.

The received data RD is configured to detect the leading edge of the signal frame by a leading edge detection circuit 11.

Oscillator 12 generates a suitable number of repetitions of reference pulses.

The frame pulse reproducing circuit 13 divides the frequency of the reference pulse several times to produce one frame of pulses.

The beginning of the frame is given by the timing signal of the leading edge detection circuit 11.

The clock pulse regeneration circuit 14 is connected to the leading edge detection circuit 11.
A clock pulse is generated from the time of the timing signal. This clock pulse signals the 17-bit shift register 15 to input the received data RD.

The data count check circuit 16 counts the number of input received data.

The parity check circuit 17 selects “
The number of 1'' signals or 0'' signals is counted and checked to see if they conform to a predetermined parity condition.

The pulse train of the received data RD is taken into the shift register 15 by the timing signal of the clock pulse recovery circuit 14.

When a 17-bit signal including parity pits is input into the shift register 15, the data 1 check circuit 1
6, the frame pulse regeneration circuit 13, and the parity check circuit 17 are opened.
to move to, to do so.

The latch circuit 19 stores open/close signals corresponding to each device number. The output buffer circuit 20 takes out this open/close signal and supplies it to the switch circuit.

In the conventional example (FIG. 5), only one data receiving section Rd is used, and the output Of of the output buffer circuit 20 is:
The signal was transmitted to the i-th switching circuit (Tri) through the control wiring Li.

However, in the present invention, the data receiving section Rdi is provided corresponding to the i-th load and switch section, and the data receiving section Rdi is provided corresponding to the i-th load and the switch section, and the output 01.・・・・・・Oi、・・・・・・、
01 of the On terminals are connected to the transistor Tri, and the others are empty terminals.

In the present invention, a data receiving section Rdi is provided for each load and a set of switch sections that control the opening/closing of the load, and since the switch section and the data receiving section are created together, the data transmission path Dp for transmitting signals is provided. Only one load would need to be wired to connect each load.

Because only a weak current flows through the data transmission path,
A thin wire will suffice. Furthermore, since an optical fiber cable can be used, it can be made lighter.

Since the thick cable through which a large current flows is used only between the power source Ei, the load, and the switch section Tri, it can be kept short.

Furthermore, in the example of FIG. 5 as well, individual switch units Trs, Tr2 .・・・・・・
One control wiring Ll, L2,...
required. In other words, the wiring was done in a radial pattern.

However, in the present invention, the data transmission path Dp only needs to send the same time-series signals (SD, RD) to the data receiving section Rdi, so there is no need for radial wiring. Data transmitter DT, data receiver Rdl.

Rd2. ......, just select the closest pair of Rdn and connect them. The length of the data transmission path Dp itself can be significantly reduced.

In this way, the number of electric wires required for wiring can be reduced, which is a useful invention.

[Brief explanation of the drawing]

FIG. 1 is a semiconductor switch circuit diagram of the present invention. FIG. 2 is an example circuit diagram of a data transmitter. FIG. 3 is an example circuit diagram of a data receiving section. FIG. 4 is a switch and load circuit diagram according to a conventional example. FIG. 5 is another switch and load circuit diagram according to the conventional example. FIG. 6 is a pulse waveform diagram illustrating a known mode of data transmission. FIG. 7 is a pulse waveform diagram illustrating a known mode of data transmission. 5wi... i-th switch Pi... i-th load Ei... power supply Tri for the i-th load
....i-th transistor DT .....data transmission section Dp .....data transmission line Rd .....data reception section Rdi .....i-th data reception section invention
Person 1) Masatoshi Naka Patent applicant
Sumitomo Electric Industries, Ltd.

Claims (4)

[Claims] (1) A data receiving unit that receives a hooded signal, decodes the received signal, and recognizes instructions regarding its own device number, and a semiconductor switch that opens and closes an electric circuit that drives a load according to the instructions of the data receiving unit. A semiconductor switch characterized by being configured by integrating the parts. (2) The semiconductor switch according to claim (1), in which the data receiving section and the semiconductor switch section are constructed on the same semiconductor chip and have a molithic IC structure. (3) The data receiving section is composed of one semiconductor chip and passive components such as capacitors and resistors, the semiconductor switch section is composed of one semiconductor chip, and the whole is mounted on one thick film printed circuit. A semiconductor switch according to claim 1, wherein the semiconductor switch is mounted and has a hybrid IC structure. (4) The semiconductor switch according to claim (1), wherein the coded signal is an optical signal and is transmitted through an optical fiber, and the data receiving section includes a light receiving element.