JPS58153361A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS58153361A JPS58153361A JP3614282A JP3614282A JPS58153361A JP S58153361 A JPS58153361 A JP S58153361A JP 3614282 A JP3614282 A JP 3614282A JP 3614282 A JP3614282 A JP 3614282A JP S58153361 A JPS58153361 A JP S58153361A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- terminal
- circuit
- transistor
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000006378 damage Effects 0.000 claims abstract description 10
- 230000002265 prevention Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は静電破壊防止回路を有する半導体集積大規模集
積回路あるいＦｉ杉大規模集積回路が極めて多量に使用
されているが、これらの部品をとル扱う上に於いてしば
しば静電気による破壊が生じ大きな問題と力ってきてい
る。しかも、最近牛導体集積回路の高集積密度化、スイ
ッチングの高速化を計るため、回路構成素子が微細寸法
化および浅い接合構成となり益々静電破壊が発生し易く
なってきている。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for handling these components, although semiconductor large-scale integrated circuits or Fisugi large-scale integrated circuits having electrostatic damage prevention circuits are used in extremely large quantities. Destruction due to static electricity often occurs, which has become a major problem. Moreover, in recent years, as conductor integrated circuits have become more densely integrated and have faster switching speeds, circuit elements have become smaller in size and have shallower junctions, making electrostatic damage more likely to occur.
例えば第１図に示すような従来回路において、接地端子
３に対し負の静電電圧が入力端子１に印加された場合は
、集積回路間の不整合によシ発生する反射波の負の電圧
を抑えるために、入力端子１と接地端子３との間に接続
された入力クランプショットキー・バリアー・ダイオー
ド４（以下人力クランプ８ＢＤと略記）によシ、入カゲ
ートショ、トキー・バリア−・ダイオード５（以下入力
ゲー）ＳＢＤと略記）が静電気から保護されるが、接地
端子３あるいは電源端子２に対し正の静電電圧が入力端
子１に印加されると、上記人力クランプ５ＢＤ４はほと
んど入力回路に対する保護効果を持たず、入力ゲー）８
ＢＤ５あるいは極端な場合人力クランプ８ＢＤ４までも
破壊されてしまう。For example, in the conventional circuit shown in Figure 1, if a negative electrostatic voltage is applied to the input terminal 1 with respect to the ground terminal 3, the negative voltage of the reflected wave generated due to the mismatch between the integrated circuits. In order to suppress (hereinafter referred to as SBD) is protected from static electricity, but if a positive electrostatic voltage is applied to the input terminal 1 with respect to the grounding terminal 3 or power supply terminal 2, the manual clamp 5BD4 will be No protection effect, input game) 8
BD5 or in extreme cases, even the manual clamp 8BD4 will be destroyed.
以下詳細に説明する。This will be explained in detail below.
ｇｔ図に示す従来回路に於いて、接地端子３Ｖｃ対し、
入力端子ｌに負の静電電圧が印加され念場合、静電気の
放電電流が入力クランプ８ＢＤ４ｔ−順方向に流れるた
め入力回路は静電気から保護される。In the conventional circuit shown in the gt diagram, for the ground terminal 3Vc,
In case a negative electrostatic voltage is applied to the input terminal l, the input circuit is protected from static electricity because a discharge current of static electricity flows in the forward direction of the input clamp 8BD4t.
しかしながら、これとは逆に接地端子３あるいは電源端
子２に対し正の大きな静電電圧が入力端子１に印加され
た場合は、入カゲー）８ＢＤ５お。However, on the contrary, if a large electrostatic voltage that is positive with respect to the ground terminal 3 or the power supply terminal 2 is applied to the input terminal 1, the input terminal 8BD5.
よび入力クランプ８ＢＤ４は極度に逆バイアス状態とが
る。ここで、通常人カクランプ８ＢＤ４ｆ１回路の正常
動作時の入力漏洩電流を小さくシ、シかも入力耐圧を高
めるためガードリング構造のＳＢＤが用いられその耐圧
は３０ボルト程ある。しかしながら、回路の閾値電圧が
低くならぬように入力ゲー）８ＢＤ５ｆｌ順方向電圧の
低い８ＢＤとする必要があり、同一構成面積に於いて順
方向電、圧が低いガードリングのない８ＢＤで構成され
る。従っておのずと入力ゲー）ＳＢＤ５のブレークダウ
ン電圧は低くな１５Ｖ程度となる。and input clamp 8BD4 are extremely reverse biased. Here, in order to reduce the input leakage current during normal operation of the normal human clamp 8BD4f1 circuit and to increase the input withstand voltage, an SBD with a guard ring structure is used, and its withstand voltage is about 30 volts. However, in order to prevent the threshold voltage of the circuit from becoming low, it is necessary to use 8BDs with low forward voltage (input gate) 8BD5fl, and it is necessary to use 8BDs with low forward voltage and low voltage in the same configuration area and without guard rings. . Therefore, the breakdown voltage of the input gate SBD5 is naturally low, about 15V.
このような集積回路構造に於いて、前述の如く入力端子
１に正の静電電圧が印加されると入カゲ−）ＳＢＤ５が
激しくブレークダウンし、静電電荷は入力端子１から、
入力ゲート５ＢＤ５、入カブルア、プ抵抗６を経て電源
端子２へ、あるいは入カゲ−）８ＢＤ５から次段トラン
ジスタ７のベースへと放電される。このとき、入力に印
加された静電電圧が高い場合はおのずと久方ゲー）ＳＢ
ＤＳを逆方向に流れる静電電荷放電電流が大きくな浸入
カゲー）ＳＢＤ５は破壊されてしまう。また極端な場合
は入力クランプ５ＢＤ４までも破壊されてしまう。In such an integrated circuit structure, when a positive electrostatic voltage is applied to the input terminal 1 as described above, the input SBD 5 will violently break down, and the electrostatic charge will be transferred from the input terminal 1.
It is discharged to the power supply terminal 2 via the input gate 5BD5, input cable, and resistor 6, or from the input gate 8BD5 to the base of the next stage transistor 7. At this time, if the electrostatic voltage applied to the input is high, it will naturally be
If the electrostatic discharge current flowing in the opposite direction through the DS is large, the SBD 5 will be destroyed. In extreme cases, even the input clamp 5BD4 may be destroyed.
これを改善するために入力ゲー）８ＢＤ５の面積を大き
くすることが考えられるが、５ＢＤ５の面積を大きくす
ることは、そのダイオードの容量が大きくなることを意
味し、多入力回路構成の場合次段トランジスタ７のベー
ス点の容量が増加し回路のスイッチングスピードの低下
をまねき好ましくない。また入力ゲート５ＢＤ５の面積
を大きくすることはチップ面積の増大をまねき高集積密
度化に極めて不利となる。しかもこの面積を大きくする
ことの効果そのものも多くは望めない。In order to improve this, it is possible to increase the area of 8BD5 (input gate), but increasing the area of 5BD5 means that the capacitance of the diode increases, and in the case of a multi-input circuit configuration, it is necessary to increase the area of 8BD5. This increases the capacitance at the base point of the transistor 7, which undesirably leads to a decrease in the switching speed of the circuit. Furthermore, increasing the area of the input gate 5BD5 increases the chip area, which is extremely disadvantageous for achieving high integration density. Moreover, it is not possible to expect much effect from increasing this area.
以上述べた通ル、第１図に示すような従来回路は、接地
端子あるいは電源端子に対し正の静電電圧が入力端子に
印加され几場合入方ゲー）Ｓ−ＨＤ。As described above, the conventional circuit as shown in FIG. 1 is connected to the S-HD when a positive electrostatic voltage is applied to the input terminal with respect to the ground terminal or the power supply terminal.
入力クランプＳＢＤ等の入力回路素子が破壊され易いと
いう大きな欠点を有していた。This had a major drawback in that input circuit elements such as the input clamp SBD were easily destroyed.
果的な静電破壊防止回路を具備した半導体集積回路を提
供することを目的とする。An object of the present invention is to provide a semiconductor integrated circuit equipped with an effective electrostatic damage prevention circuit.
本発明によれば、コレクタが入力端子に、エミ、りが接
地端子′ｔたは電源端子に接続されたトランジスタト該
トランジスタのベース、エミ、り間に接続された、ダイ
オードと抵抗の直列接続回路を含んでなる静電破壊防止
回路を有することを特徴とし、入力静電耐圧の大幅に改
善された半導体集積回路を得ることができる。According to the present invention, a transistor is connected in series with a diode and a resistor, the collector of which is connected to the input terminal, and the emitter of the transistor connected to the ground terminal or the power supply terminal. The present invention is characterized by having an electrostatic damage prevention circuit including a circuit, and it is possible to obtain a semiconductor integrated circuit with significantly improved input electrostatic breakdown voltage.
次に本発明をその実施例に従い図面音用いて詳細に説明
する。Next, the present invention will be explained in detail according to embodiments thereof with reference to the drawings.
第２図は本発明の一実施例を示す回路接続図である。本
発明回路が第１図に示す従来回路と異なるところは％
＊九に、ベース、エミ、４間に８ＢＤ９と抵抗ｌＯの直
列回路が接続された工電、４接地のトランジスタ８のコ
レクタを入力端子ＩＫ接続し几ことである。以下このよ
うな本発明静電破壊防止回路の１０作について述べる。FIG. 2 is a circuit connection diagram showing one embodiment of the present invention. The difference between the circuit of the present invention and the conventional circuit shown in FIG.
*Ninthly, connect the collector of the grounded transistor 8, which has a series circuit of 8BD9 and resistor 10 connected between the base, emitter, and 4, to the input terminal IK. Below, ten works of the electrostatic damage prevention circuit of the present invention will be described.
いま入力端子１に正の静電電圧が印加された場合、本発
明により新九に付加された静電破壊防止回路のトランジ
スタ８のコレクタ、ペース接合が逆バイアスとな〕、ま
ず逆バイアス漏洩電流がコレクターベース−８ＢＤ９−
抵抗１０を経て接地端子３へと流れる。入力端子１の電
圧の上昇に伴ない上記漏洩電流工、。３が増加し、８Ｂ
Ｄｇと抵抗１０のｉＫ列＊絖回路のｗ位降下が、トラン
ジスタ８のベース、二ン、タ間順方向閾値電圧Ｖｌｌｌ
ｌに達すると、漏洩電流ＩＬＯＢの一部がトランジスタ
８のベース端子へ流れ込みトランジスタ８が導通し、入
力端子へ流れ込んだ静電気放電電流の大部分がトランジ
スタ８の導通電流としてコレクタへ流れ込み、での工ｚ
、４から接地端子へと流れ出る。If a positive electrostatic voltage is now applied to the input terminal 1, the collector and paste junction of the transistor 8 of the electrostatic breakdown prevention circuit added to the new model according to the present invention will be reverse biased], and first the reverse bias leakage current will be is collector base-8BD9-
It flows through the resistor 10 to the ground terminal 3. The above leakage current leakage occurs as the voltage at the input terminal 1 increases. 3 increases, 8B
Dg and the iK series of resistors 10 *W level drop of the wire circuit is the forward threshold voltage Vllll between the base, pin, and pin of transistor 8.
When the leakage current ILOB reaches 1, a part of the leakage current ILOB flows into the base terminal of the transistor 8, making the transistor 8 conductive, and most of the electrostatic discharge current that has flowed into the input terminal flows into the collector as the conduction current of the transistor 8, and the z
, 4 to the ground terminal.
ここでトランジスタ８は静電破壊防止の目的のみで考え
るならばペース開放が望ましいが、この場合通常動作時
トランジスタ８のペースへ何らかの漏洩電流■Ｌが流れ
込むとやはりトランジスタ８が能動状態とな〕その漏洩
電流Ｉ、のｈＦ１倍のコレクタ電流が流れ込む。すなわ
ちトランジスタ８″ｆｔベース開放とすることは、通常
動作に於いて入力に高レベル電圧が印加されたときの高
しベランジスタ８０ペースが駆動されることがないよう
にするためトランジスタ８のペースと接地間に抵抗のみ
を接続することも考えられるが、この場合、抵抗が小さ
すぎると、入力端子１に靜電雷圧が印加され、トランジ
スタ８のコレクタ、ペース接合がブレークダウンし次と
きの電流が相当大きくならないと抵抗の電位降下≠トラ
ンジスタ８０ベース、エミッタ間接合順方向電圧以上と
ならないためトランジスタ８が動作し得ない。すなわち
１この抵抗が小さすぎると抵抗の電位降下がトランジス
タ８のペース、エミ、り間順方向電圧になる前にトラン
ジスタ８のコレクタ、ペース接合ブレークダウン電流が
トランジスタ８の破壊にいたる限界電流値を起えてしま
い、トランジスタ８が何ら回路の保護作用を呈し得ない
うちにトランジスタ８自身が破壊してしまう。従って、
トランジスタ８０ベースと接地間に抵抗のみ′ｆｒ、接
続する場合この抵抗値はシめて大きなものでなければな
らず、実験では１５にΩ程度必要でありた。このことは
、この抵抗を半導体集積回路として構成するに多大の面
積を必要とし高集積密度化に著るしく不向きであること
を示す。Here, it is desirable to open the transistor 8 to prevent electrostatic damage, but in this case, if some leakage current L flows into the transistor 8 during normal operation, the transistor 8 becomes active. A collector current that is hF1 times the leakage current I flows into the collector current. In other words, the reason for opening the base of transistor 8 is that the base of transistor 8 is connected to the ground in order to prevent the high verangister 80 pace from being driven when a high level voltage is applied to the input during normal operation. It is also possible to connect only a resistor between them, but in this case, if the resistor is too small, static lightning voltage will be applied to input terminal 1, and the collector and paste junction of transistor 8 will break down, causing the next current to increase considerably. If the resistor is not too large, the potential drop of the resistor will not exceed the junction forward voltage between the base and emitter of the transistor 80, and the transistor 8 will not be able to operate.In other words, if this resistor is too small, the potential drop of the resistor will cause the transistor 8's pace, emitter, The breakdown current at the collector and paste junction of the transistor 8 reaches a critical current value that destroys the transistor 8 before the voltage reaches the forward direction, and the transistor 8 It destroys itself.Therefore,
When only a resistor 'fr is connected between the base of the transistor 80 and the ground, this resistance value must be very large, and in experiments, about 15Ω was required. This indicates that constructing this resistor as a semiconductor integrated circuit requires a large area and is extremely unsuitable for high integration density.
本発明の場合８ＢＩ）９けこの改善を目的として挿入さ
れたものであり、８ＢＤ９の順方向電圧によりそれ金直
列接伏された抵抗１０の抵抗値が小さくともわずかのト
ランジスタ８のコレクタ、ペース接合ブレークダウン１
流が流れただけでこの直列回路の電位降下がトランジス
タ８のペース。In the case of the present invention, 8BI)9 is inserted for the purpose of improving the scale, and even if the resistance value of the resistor 10 connected in series with the metal is small due to the forward voltage of 8BD9, the collector of the transistor 8, the paste junction. breakdown 1
The potential drop in this series circuit is the pace of transistor 8 just by the current flowing.
エミッタ間を順方向バイアス以上になるという効果を有
する。従って本考案回路の抵抗１０け、トランジスタ８
のペースを抵抗のみで接地した場合に比較し著るしく小
さな抵抗値で十分となり、おのすと小面積にて集積回路
化が可能となる。This has the effect of creating more than a forward bias between the emitters. Therefore, the circuit of the present invention has 10 resistors and 8 transistors.
Compared to the case where the pace of the circuit is grounded using only a resistor, a significantly smaller resistance value is sufficient, making it possible to integrate the circuit in a smaller area.
例工ば、トランジスタ８のペース、エミッタ接合を順バ
イアスするに必要な電圧をＶＢ１１８％ トランジスタ
８が破壊にいたってしまうコレクタ、ペース接合ブレー
クダウン電流ｔｌ”ｌｏＢＤ％ 本発明回路の８ＢＤ９
の導通電流がｌ０ＢＤのときの順方向電圧を■３、抵抗
ｌＯの抵抗値ケＲ１およびトランジスタ８０ベースが抵
抗のみで接地された場合の抵抗値全Ｒ′ とすると、２
つの回路がそれぞれ静電破壊防止回路として動作する九
めには下式が成立しなければならない。For example, if the voltage required to forward bias the pace and emitter junction of transistor 8 is VB118%, the collector and pace junction breakdown current tl''loBD% that would destroy transistor 8 is 8BD9 of the circuit of the present invention.
If the forward voltage when the conduction current of is 10BD is 3, the resistance value of the resistor 10 is R1, and the total resistance value R' when the base of the transistor 80 is grounded only by the resistor, then 2
For each of the two circuits to operate as an electrostatic damage prevention circuit, the following formula must hold true.
トランジスタ８が抵抗のみで接地された場合；！
”’−Ｘ ＯＢ Ｄ＞ＶＢ １ｇ ・・
・・・・・・・ （１）本考案回路の場合
ＶＢ＋Ｒ４０ＢＢ＞ＶＢｌｇ ＋＋＋＋＋＋・
＋・ （２）１１ｉ１ＣＶｉｓｍｇ Ｈｏ、Ｔ Ｖ、
ＶＳ ｌｄｏ、６ Ｖ程度であり、この値ｔ：（１１，
（２１式に代入し整理するとＲ’：Ｒ。When transistor 8 is grounded only through a resistor;! ”'-X OB D>VB 1g...
・・・・・・・・・ (1) In the case of the circuit of the present invention, VB+R40BB>VBlg ++++++++・
+・ (2) 11i1CVism Ho, T V,
VS ldo is about 6 V, and this value t: (11,
(Substituting into equation 21 and rearranging gives R':R.
＝７：ｌとなり、本考案回路の場合は、５ＢＤＱを挿入
しない場合に比較し抵抗値は−で良いことになり、例え
８ＢＤ９の構成面積が余分に必要になるとはいえ、８Ｂ
Ｄ９と抵抗１０は回−の島内に小面積にて集積回路構成
することが可能であ夛、高集積密度化に極めて有利とな
る。= 7:l, and in the case of the circuit of the present invention, the resistance value can be - compared to the case where 5BDQ is not inserted, and even though an extra component area of 8BD9 is required, 8B
D9 and the resistor 10 can be integrated into a circuit in a small area within the circuit island, which is extremely advantageous for high integration density.
第３図は、第２図に示す本発明回路を集積回路にて構成
したときの５ＢＤ９と抵抗１０のみの構成断面図であり
、第４図はその平面パターン図を示す。図において、１
０１けＰ型半導体基板、１０２はＮ型エピタキシャル領
域、１０３．ＨＰ型絶絶縁領域１０４にＰ型半導体領域
、１０５は高不純物濃度のＮ型半導体領域、１０６Ｆｉ
シリコン酸化膜、１０７，１０７’ 、１０７“は金属
シリサイド層、１０８，１０８’、１０８“は配線領域
を示し、１０７“と１０２の間に８ＢＤ９が、Ｐ型半導
体領域１０４により抵抗１０が形成されている。図から
もわかる通り、高不純物濃度のＮ型半導体領域１０５、
金属シ１）サイド層１０７′、および配線領域１０８′
により、５ＢＤ９と抵抗１０が直列接続される。FIG. 3 is a cross-sectional view of only the 5BD9 and resistor 10 when the circuit of the present invention shown in FIG. 2 is constructed as an integrated circuit, and FIG. 4 is a plan pattern diagram thereof. In the figure, 1
01 is a P-type semiconductor substrate, 102 is an N-type epitaxial region, 103. The HP type insulating region 104 is a P type semiconductor region, 105 is a high impurity concentration N type semiconductor region, 106 Fi
Silicon oxide films, 107, 107' and 107'' are metal silicide layers, 108, 108' and 108'' are wiring regions, 8BD9 is formed between 107'' and 102, and a resistor 10 is formed by a P-type semiconductor region 104. As can be seen from the figure, the N-type semiconductor region 105 with a high impurity concentration,
Metal layer 1) Side layer 107' and wiring region 108'
5BD9 and the resistor 10 are connected in series.
尚試作実験により調査した結果、入力端子に、接地端子
あるいは電源端子に対し正の静電電圧を即加したとき、
第１図に示す従来回路の静電耐圧が１５０Ｖ程度しかな
かったのに対し本考案回路の静電耐圧は５００Ｖ以上と
なり大幅に静電耐圧が改善された。As a result of investigation through prototype experiments, when a positive electrostatic voltage is immediately applied to the input terminal with respect to the ground terminal or power supply terminal,
While the electrostatic withstand voltage of the conventional circuit shown in FIG. 1 was only about 150V, the electrostatic withstand voltage of the circuit of the present invention was over 500V, which was a significant improvement in electrostatic withstand voltage.
尚、以上の説明に於いては、ダイオード９が８ＢＤの場
合について述べ九が、ダイオード９がトランジスタ８の
ペース、エミッタ接合より低い順方向電圧であれば、本
発明の効果を有することはいうまでもない、また本発明
回路の静電破壊防止回路のトランジスタ８のエミッタと
抵抗の一端ヲ、接地端子に限らず電源端子に接続しても
発明の効果は変らない、なお又、抵抗１０はダイオード
９自を適用しうることは改めて説明するまでもがい。In the above explanation, the case where the diode 9 is 8BD is described. However, it goes without saying that the effect of the present invention is achieved if the forward voltage of the diode 9 is lower than the pace and emitter junction of the transistor 8. Furthermore, the effect of the invention does not change even if the emitter of the transistor 8 of the electrostatic breakdown prevention circuit of the circuit of the present invention and one end of the resistor are connected to the power supply terminal instead of the ground terminal.Furthermore, the resistor 10 is a diode. There is no need to explain again that 9-self can be applied.
以上述べた通り、本発明回路によれば、はとんど素子数
およびチップサイズを増加させることなしに、半導体集
積回路の静電耐圧を著しく高めるという極めて大きな効
果を奏することができる。As described above, according to the circuit of the present invention, it is possible to achieve the extremely large effect of significantly increasing the electrostatic withstand voltage of a semiconductor integrated circuit without increasing the number of elements or chip size.
第１図は従来の半導体集積回路入力部を示す回路接続図
、第２図は本発明の一実施例を示す入力回路接続図、第
３図は第２図の５ＢＤ９と抵抗１０に関する半導体集積
回路構成断面図、第４図は１第３図の平面パターン図で
ある。
１・・・・・・信号入力端子、２・・・・・・電源端子
、３・・・・・・接地端子、４，５．９・・・・・・Ｓ
ＢＤ、６．１０・・・・・・抵抗、 ７． ８・・・・
・・トランジスタ、１０１・・・・・・Ｐ型基板、１０
２・・・・・・Ｎ型エピタキシャル領域１１０３・・・
・・・Ｐ型絶縁領域、１０４・・・・・・Ｐ型半導体領
域、１０５・・・・・・高不純物濃度のＮ型半導体領域
、１０６・・・・・・シリコン酸化膜、１０７，１０７
’１０７“・・・・・・金属シリサイド層、１０８，１
０８’。
１０８“・・・・・・配線領域。
第１図
第２図
第３図
第４図FIG. 1 is a circuit connection diagram showing a conventional semiconductor integrated circuit input section, FIG. 2 is an input circuit connection diagram showing an embodiment of the present invention, and FIG. 3 is a semiconductor integrated circuit relating to 5BD9 and resistor 10 in FIG. The configuration cross-sectional view, FIG. 4, is a plan pattern diagram of FIG. 1 and FIG. 3. 1...Signal input terminal, 2...Power terminal, 3...Ground terminal, 4,5.9...S
BD, 6.10...Resistance, 7. 8...
...Transistor, 101...P-type substrate, 10
2...N-type epitaxial region 1103...
... P type insulating region, 104 ... P type semiconductor region, 105 ... N type semiconductor region with high impurity concentration, 106 ... silicon oxide film, 107, 107
'107''...Metal silicide layer, 108,1
08'. 108"...Wiring area. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
端子に接続されたトランジスタと該トランジスタのベー
ス、工ｆ、タ間に接続された、ダイオードと抵抗の直列
接続回路を含んでなる静電破壊防止回路金有することを
特徴とする半導体集積回路。Electrostatic discharge damage that includes a transistor whose collector is connected to an input terminal and whose emitter is connected to a ground or power supply terminal, and a series-connected circuit of a diode and a resistor connected between the base, terminals, and terminals of the transistor. A semiconductor integrated circuit characterized by having a prevention circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3614282A JPS58153361A (en) | 1982-03-08 | 1982-03-08 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3614282A JPS58153361A (en) | 1982-03-08 | 1982-03-08 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58153361A true JPS58153361A (en) | 1983-09-12 |
| JPH0258782B2 JPH0258782B2 (en) | 1990-12-10 |
Family
ID=12461536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3614282A Granted JPS58153361A (en) | 1982-03-08 | 1982-03-08 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58153361A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0144208A1 (en) * | 1983-11-30 | 1985-06-12 | Fujitsu Limited | A protecting circuit for a semiconductor device |
| JPH0327566A (en) * | 1989-03-15 | 1991-02-05 | Matsushita Electric Ind Co Ltd | Surge protecting device |
-
1982
- 1982-03-08 JP JP3614282A patent/JPS58153361A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0144208A1 (en) * | 1983-11-30 | 1985-06-12 | Fujitsu Limited | A protecting circuit for a semiconductor device |
| JPH0327566A (en) * | 1989-03-15 | 1991-02-05 | Matsushita Electric Ind Co Ltd | Surge protecting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0258782B2 (en) | 1990-12-10 |
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