JPS5815325A - Digital-to-analog converter - Google Patents

Abstract

PURPOSE:To exclude a ripple to a digital signal supplied in a slow speed, by latching an input digital signal and processing the signal with a clock frequency of a different system from a control system. CONSTITUTION:A latch circuit 8 latches data D at the generation of a latch pulse LP and the latch data is kept transmistted until the next latch pulse LP is supplied. On the other hand, a counter 9 counts a pulse CP from an oscillator 10 and when the counts reaches a predetermined value N, an outut signal n is transmitted for reset. A coincidence detecting circuit 11 detects the coincidence between the output of the latch circuit 8 and that of the counter 9 and opens a gate 12 until the coincidence is taken and the CP is applied to an active filter 4. Harmonics of the ouptut of the gate 12 is eliminated with a filter 4 and applied to an integration circuit 7 via an electronic switch 13 and converted into a tuning voltage of an analog signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital/analog converter, and more particularly to a digital/analog converter for converting a low-speed digital signal into an analog signal with less ripple.

FIG. 1 shows an example of a tuning voltage generation DO path using a single type of voltage synthesizer commonly used in the past. When a channel selection switch (not shown) with a key & keypad (not shown) is operated, the address of the internal memory corresponding to the output of the operated channel selection switch is designated and designated by the channel selection switch. reads out the information necessary to obtain the tuning voltage for receiving the TV broadcast channel
A pulse train with a period corresponding to this information is sent out. The nozzle array Fi output from the control unit 1 is supplied to the tuning circuit as a tuning voltage via the active filter 4.

In this case, if the tuning voltage contains ripples, the tuning state becomes unstable.The ripples are greatly affected by the generation period of the pulse train.In other words, the ripples contained in the tuning voltage as the digital-to-analog conversion output should be reduced. In order to achieve this, it is necessary to shorten the period of occurrence of the Nogurus train. Moreover, the number of bits that make up the nozzle array cannot be made small in terms of tuning voltage resolution. There is a trend toward microcomputers for the control unit, and especially when a microcomputer is used in the 0-MO8 configuration, its operation cannot be made very quickly, so the generation cycle of the A pulse train is The upper limit is also naturally limited.

Accordingly, an object of the present invention is to provide a digital-to-analog converter that can convert even a digital signal supplied at a slow speed into a high-precision analog signal that does not include ripples.

In order to achieve such an object, the present invention employs a method of latching the input digital signal and processing it at a clock frequency of a system different from that of the control system (same but higher frequency). In other words, a counter that sequentially counts high-frequency clock pulses and is reset when a predetermined count value is reached is provided, and an output is generated at - until the count output matches the latched data. By incorporating a high-frequency clock pulse train and integrating it only during the output generation period of this scattering output circuit, the period of the noggle train during integration is shortened and ripples are generated. This prevents

The digital/analog computer according to the present invention will be explained in detail below using an embodiment shown in one drawing.

FIG. 2 is a circuit diagram showing an embodiment of the digital/analog converter A-2 according to the present invention, and the same parts as in FIG. 1 are indicated using the same symbols.

In the figure, the control unit 1 is constituted by the -f microcomputer as described above, and reads out the tuning information by addressing the memory in response to the output of the channel selection switch.

It is output as a 9-rarel data/D together with a latch/9-rus LP. 8Ifi Latch circuit that latches data D by latch pulse LP supplied from control unit %
A counter 9 sequentially counts clock pulses OP supplied from the oscillator IO, and is configured to be reset by its output signal n when a set value NK is reached. 1M is a coincidence detection circuit which inputs the output of the latch circuit 8 and the count output of the counter 90, and inverts the output from 1H" to @L" when it detects a coincidence between the two, and uses the output signal n of the counter 9 as a reset signal. As.

This is a gate circuit that allows the clock signal OP to pass only while the output of the 12-digit coincidence detection circuit 11 is 1H'', and an electronic switch that opens only when a 13-digit latch pulse LP is generated.

With the circuit configured as described above, when the M-channel selection switch (not shown) provided on the key key 3 is operated to select a desired receiving television channel, the control section!
In response to the signal from the operated channel selection switch, the contents of the corresponding address in the memory are read out.

This read information is processed as data D by the latch pulse LP.
It is also supplied to the latch circuit 8.

The latch circuit 8 receives the data D when the latch pulse LP is generated.
is latched, and the latch data is applied to the next latch pulse LP.
Continue sending until supplied.

On the other hand, the 2 MH supplied from the counter S1 oscillator lO
The high-speed clock pulses CP of vs are sequentially counted, the sequentially increasing count output is supplied to the coincidence detection circuit 11, and when a predetermined value N is reached, the output signal n
A self-reset is performed by sending the . Therefore, the counter 9 is reset every N counts and starts counting again. -Scatter product output circuit! uses the output of the latch circuit 8 and the output of the counter 9 as inputs to detect a match between the two, and when the two power values match, the output is inverted from @H# to "L". As a result, -Scattered product output circuit Otori! From FIG. The guru sequence shown in (a) is output.No.1.
That will happen. On the other hand, the gate circuit 12 is connected to the coincidence detection circuit 1.
The output of 1 and the clock pulse OP of 2MH2 are input. K, and its output waveform is shown in Figure 3.
As shown in b+, during the period when the output of the coincidence detection circuit 11 is @H'', the time width portion corresponding to the output value of the latch circuit 8 is decomposed and read out with high precision as a short -) pulse string. Therefore, the latch circuit 8 absorbs the operating speed of the control unit 1 and the digital-to-analog converter.The third W!JlbJK of the gate circuit !2 read out in this way is After the high frequency component is removed from the output by the active filter 4,
The signal is supplied to the integration circuit 7 via the electronic switch 13 and converted into an analog signal tuning voltage.

In this case, the analog value tuning voltage output from the electronic switch 3 is the supply period of the clock pulse CP,
In other words, it changes depending on the latch circuit 80 launch output value. In the above configuration, the latch circuit 8
The pulse train, whose duty is determined by the latch output of The content rate is significantly reduced. Furthermore, since the high-speed pulse is read out using φ, an analog value tuning voltage with highly accurate resolution can be obtained.

On the other hand, the electronic switch 13 receives the latch pulse LP outputted from the control unit as a control input, and the output of the gate circuit jll12, which is supplied via the active filter 4 with the generation period of this latch pulse LP open, is connected to the integrating circuit. 7 and 1kvs. This is due to the force 4 that causes the latch path 8 to latch when the latch pulse LP is generated, but the latch output value becomes unstable at that moment, so in response to this, the analog conversion value Therefore, in a digital analyzer/controller configured in this way, the key/-PK1
It is only necessary to receive the data D necessary to generate the tuning voltage of the television broadcasting channel set to the channel selection switch operated by 1%/-h.
Therefore, even if a slow-acting controller is used as the controller, ripples included in the analog conversion signal will be extremely small. (9) After the data D is sent, the control unit 1 does not need to be involved in the digital-to-analog conversion operation until a new channel selection switch is operated and the data JD is changed. Other processing can be performed accordingly.

In the above-described embodiment, the data D is sent as parallel data, but it goes without saying that it may also be supplied to the latch circuit 8 as serial data.

As explained above, the digital analog controller according to the present invention fixes the output value by latching the digital value in the latch circuit.

An I# pulse train whose duty is determined by this latch output value is generated, this pulse train is decomposed using a high-speed nocellus, and the read output is converted into an analog value. Therefore, even for digital values supplied at a low speed, the present invention has an excellent effect of easily obtaining an analog conversion output having high precision resolution and having extremely low ripple content.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a case where a conventional digital/analog controller is used for tuning tuning control, and Fig. 2 is a circuit diagram showing a case where a digital fist analog controller according to the present invention is used for tuning tuning control. A circuit diagram showing an example of the case, FIG.
This is a diagram of the operation waveforms of each part of the circuit shown in the figure. ! -Control unit, 4-Active fill! , S-...resistance,
6.-Capacitor, 7.--Integrator circuit %8-.Uchi circuit %9.-Power load! o...oscillator, II...-
Several output circuits s12...gate circuit, 13...electronic switch. Figure 3 (b) J door fl

Claims (1)

[Claims] (1) A latch circuit that holds a digital input signal to be converted; a counter that sequentially counts a high-speed noggle and outputs the count value; and returns to the counting start state when a predetermined count value is reached; a coincidence detection circuit between the output value of the latch circuit and the output value of the counter; a gate circuit that sends out high-speed pulses only during the output sending period of the scattering and accumulation output circuit; and a gate circuit that integrates the output pulse train of the gate circuit. A digital/analog comperme characterized by being equipped with an integrating circuit that outputs an analog value.